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REV. A Structure Silicon Monolithic Integrated Circuit Product Name Step-up DC/DC conv erter for medium size LCD panel Type BD6150MUV Features High efficiency PWM step- up DC/DC converter (fsw=1.25MHz) High accuracy and good matching current driver 6ch (MAX 30mA/ch) Drive up to 10 in series x 6 strings in parallel =60 white LEDs

  • Absolute Maximum Ratings (Ta=25°C) Parameter Symbol Rating Unit Condition Maximum applied voltage 1 VMAX1 7 V VREG, ISET, PWMDRV, FSEL, OCPSET, VDET, TEST Maximum applied voltage 2 VMAX2 25 V LED1, LED2, LED3 LED4, LED5, LED6 Maximum applied voltage 3 VMAX3 30.5 V VBAT, FAILFLAG, PWMPOW Maximum applied voltage 4 VMAX4 41 V SW Power dissipation 1 Pd1 500 mW *1 Power dissipation 2 Pd2 780 mW *2 Power dissipation 3 Pd3 1510 mW *3 Operating temperature range Topr -40 ~ +85 °C - Storage temperature range Tstg -55 ~ +150 °C - *1 Reduced 4.0mW/°C With Ta>25°C w hen not mounted on a heat radiation Board. *2 1 layer (ROHM Standard board) has been mounted. Copper foil area 0mm 2, When it’s used by more than Ta=25°C, it’s reduced by 6.2mW/°C. *3 4 layer (JEDEC Compliant board) has bee n mounted. Copper foil area 1layer 6.28mm2, Copper foil area 2~4layers 5655.04mm2, When it’s used by more than Ta=25°C, it’s reduced by 12.1mW/°C.
  • Operating conditions (Ta=-40 to +85°C) Parameter Symbol Rating Unit Condition Min. Typ Max Supply voltage VBAT 4.2 12.0 26.0 V This product isn’t designed to protect itself against radioactive rays.

REV. A

  • Electrical Characteristics (Unless otherwise noted, VBAT=12V, Ta = +25°C) Parameter Symbol Limits Unit Condition Min. Typ. Max. Quiescent current Iq - 1.6 4.4 µA PWMPOW=PWMDRV=0V Current consumption Idd - 3.6 5.4 mA VDET=0V,ISET=22k Ω [PWMPOW Terminal] Low input voltage range1 POWL 0 - 0.9 V High input voltage range1 POWH 2.1 - VBAT V Pull down resistor1 POWR 100 300 500 k Ω PWMPOW=2.5V [PWMDRV Terminal] Low input voltage range2 PDRVL 0 - 0.9 V High input voltage range2 PDRVH 2.1 - 6.0 V Pull down resistor2 DRVR 100 300 500 k Ω PWMDRV=2.5V [FSEL Terminal] Low input voltage range3 FSL 0 - 0.9 V High input voltage range3 FSH 2.1 - 6.0 V Pull down resistor3 FSR 100 300 500 k Ω FSEL=2.5V [FAILFLAG] Input resistor FFIR 1.0 2.0 3.0 k Ω FAILFLAG=2.5V Off current FFIST - 0.1 2.0 µA PWMPOW=0V [Regulator] VREG voltage VREG 4.2 5.0 6.0 V No load Under voltage lock out UVLO 3.3 3.7 4.1 V VBAT falling edge [Switching Regulator] LED control voltage VLED 0.56 0.70 0.84 V Switching frequency fsw 1.00 1.25 1.50 MHz FSEL=L (GND short) Duty cycle limit Duty 91.0 95.0 99.0 % LED1-6=0.3V SW Nch FET RON RON - 0.48 0.58 Ω ISW=80mA [Protection] Over current limit Ocp 1.4 2.0 2.6 A *1 OCPSET=68kΩ OCPSET open protect OOP - 0.0 0.1 A OCPSET=2M Ω Over voltage limit Input Ovl 0.96 1.00 1.04 V Detect voltage of VDET pin SBD open protect Sop 0.02 0.05 0.08 V Detect voltage of VDET pin VDET leak current OVIL - 0.1 1.0 µA [Current driver] LED maximum current ILMAX - - 30 mA LED current accuracy ILACCU - - ±3.0 % ILED=16~20mA LED current matching ILMAT - - ±1.5 % Each LED current/Average (LED1-6) ILED=16~20mA LED current limiter ILOCP - 0 0.1 mA Current limit value at ISET resistor 1kΩ setting LED terminal Over voltage protect LEDOVP 10.0 11.5 13.0 V PWMDRV=2.5V ISET voltage Iset 0.5 0.6 0.7 V *1 This parameter is tested with dc measurement.

REV. A

  • Package outline drawing ●Terminals PIN PIN Name 1 SW 2 SW 3 N.C.

4 PGND

5 FAILFLAG

6 OCPSET

7 VDET

8 TEST

9 FSEL

10 ISET

11 GND

12 N.C.

13 LED1

14 LED2

15 LED3

16 LED4

17 LED5

18 LED6

19 N.C.

20 GND

21 PWMDRV

22 VREG

23 PWMPOW

24 VBAT

  • Block diagram VQFN024V4040 ( Unit : mm ) D6150 LOT No. Type VBAT VREG REG TSD Internal Power Supply Clamp PWMPOW Internal Power Control UVLO Internal Reset FSEL FAULT DETECTOR FAILFLAG SW SW SBD OPEN/ Output short PROTECT Output Over Voltage PROTECT LED TERMINAL OPEN/SHORT DETECTOR LED RETURN SELECT LED1 LED2 LED3 LED4 LED5 LED6 VDET Current SENCE Over Current Protect PGND Soft start Control SENCE OSC + ERRAMP PWM COMP 6ch GND Current Driver PWMDRV ISET ISET Resistor driver GND TEST OCPSET N.C.

REV. A

  • Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open ci rcuit. If any special mode excee ding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Operating conditions These conditions represent a range within which characteristics can be provided approx imately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from t hat for the analog block, thus s uppressing the diffraction of dig ital noises to the analog block power supply resulting from impedan ce common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a ca pacitor between the power supply and the GND terminal. At the sam e time, in order to use an electrolytic capacitor, thoroughly che ck to be sure the characteristics of the capacitor to be used pr esent no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furtherm ore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between term inals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to forei gn matters entering between terminals or between the terminal and t he power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals In terms of the construction of IC, para sitic elements are inevitably formed in relation to potential. The operation of the par asitic element can cause interference wi th circuit operation, thus resulting in a ma lfunction and then breakdown of the input terminal . Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower th an the GND respectively, so that any parasitic element will operate. Fu rthermore, do not apply a voltage to the input terminals when n o power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from t he small-signal GND pattern and establish a single ground at the refer ence point of the set PCB so that resistance to the wiring p attern and voltage fluctuations due to a large current will cause no fluc tuations in voltages of the small-signal GND. Pay attention n ot to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (12) Thermal shutdown circuit (TSD) When junction temperatures becom e 175°C (typ) or higher, the thermal shutdown circuit operates and turns a switch OFF. The thermal shutdown circuit, which is aimed at isolating the LSI from thermal runaway as much as possible, is not aimed at the protection or guarantee of the LSI. Therefore, do not continuously use the LSI with this circuit operating or use the LSI assuming its operation. (13) Thermal design Perform thermal design in which there are adequate margins by taking into account the permissible dissipation (Pd) in actual states of use. (14) Selection of coil Select the low DCR inductors to decrease power loss for DC/DC converter.

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