Memory

B8132B4PB-8D-F

Micron Technology

Embedded LPDDR2 SDRAM Rev. C 1/16 EN

Manufacturer: Micron Technology

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Features

Ultra-low-voltage core and I/O power supplies
Frequency range – 400 MHz (data rate: 800 Mb/s/pin)
4 n prefetch DDR architecture
8 internal banks for concurrent operation
Multiplexed, double data rate, command/address inputs; commands entered on each CK_t/CK_c edge
Bidirectional/differential data strobe per byte of data (DQS_t/DQS_c)
Programmable READ and WRITE latencies (RL/WL)
Burst length: 4, 8, and 16
Per-bank refresh for concurrent operation
Auto temperature-compensated self refresh (ATCSR) by built-in temperature sensor
Partial-array self refresh (PASR)
Deep power-down mode (DPD)
Selectable output drive strength (DS)
Clock-stop capability
Lead-free (RoHS-compliant) and halogen-free packaging Options Marking
Density/Chip select – 8Gb/2-CS - dual die 81
Organization – x32 32
V DD1/VDD2/VDDQ: 1.8V/1.2V/1.2V B
Revision 4
FBGA “green” package – 12mm x 12mm x 0.8mm, 168-ball PB
Timing – cycle time – 2.5ns @ RL = 6 -8D
Operating temperature range – From –30°C to +85°C Blank Table 1: Key Timing Parameters Speed Grade Clock Rate (MHz) Data Rate (Mb/s/pin) RL WL 8D 400 800 6 3 Embedded LPDDR2 SDRAM

PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Configuration Addressing – Single-Channel Package Architecture 256 Meg x 32 Density per package 8Gb Die per package 2 Ranks per channel 1 Die per rank 2 Configuration 32 Meg x 16 x 8 banks x 2 Row addressing 16K A[13:0] Column addressing 2K A[10:0] Table 3: Part Number Description Part Number Total Density Configuration Ranks Channels Package Size Ball Pitch EDB8132B4PB-8D-F-R, EDB8132B4PB-8D-F-D 8Gb 256 Meg x 32 1 1 12mm x 12mm (0.80mm MAX height) 0.50mm Figure 1: Marketing Part Number Chart EDB 8 1 3 2 B F Micron Technology Type D = Packaged device Product Family B = Mobile LPDDR2 SDRAM Density/Chip Select 81 = 8Gb/2-CS Organization 32 = x32 Power Supply Interface B = VDD1 = 1.8V, VDD2 = VDDQ = 1.2V, S4B device, HSUL

4 PB 8D-- D

D = Dry Pack (Tray) R = Tape and Reel Environment Code F = Lead-free (RoHS-compliant) and halogen-free Speed 8D = 800 Mb/s Package PB = BGA for PoP Revision Note: 1. The characters highlighted in gray indicate the physical part marking found on the device. Embedded LPDDR2 SDRAM PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

LPDDR2 Array Configuration The 4Gb Mobile Low-Power DDR2 SDRAM (LPDDR2) is a high-speed CMOS, dynamic random-access memory containing 4,294,967,296-bits. The device is internally config- ured as an eight-bank DRAM. Each of the x16’s 536,870,912-bit banks is organized as 16,384 rows by 2048 columns by 16 bits. Each of the x32’s 536,870,912-bit banks is or- ganized as 16,384 rows by 1024 columns by 32 bits. General Notes Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be inter- preted as any or all DQ collectively, unless specifically stated otherwise. “DQS” and “CK” should be interpreted as DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise. “BA” includes all BA pins used for a given density. Complete functionality may be described throughout the entire document. Any page or diagram may have been simplified to convey a topic and may not be inclusive of all re- quirements. Any specific requirement takes precedence over a general statement. Any functionality not specifically stated herein is considered undefined, illegal, is not supported, and will result in unknown operation. Embedded LPDDR2 SDRAM LPDDR2 Array Configuration PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

IDD Specifications – Dual Die, Single Channel Table 4: IDD Specifications VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –30°C to +85°C Symbol Supply Speed Unit Parameter/Condition800 IDD01 VDD1 8 mA One device in operating one bank active-precharge; Another device in deep power-down. tCK = tCK(avg) MIN; tRC = tRC (MIN); CKE is HIGH; CS_n is HIGH between valid commands; CA bus inputs are SWITCHING; Data bus inputs are STABLE I DD02 VDD2 45 IDD0,in VDDQ 0.6 IDD2P1 VDD1 0.8 mA All devices in idle power-down standby current tCK = tCK(avg) MIN; CKE is LOW; CS_n is HIGH; All banks idle; CA bus inputs are SWITCHING; Data bus inputs are STABLE I DD2P2 VDD2 1.8 IDD2P,in VDDQ 0.2 IDD2PS1 VDD1 0.8 mA All devices in idle power-down standby current with clock stop. CK_t = LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; All banks idle; CA bus inputs are STABLE; Data bus inputs are STABLE I DD2PS2 VDD2 1.8 IDD2PS,in VDDQ 0.2 IDD2N1 VDD1 1.2 mA All devices in idle non power-down standby current. tCK = tCK(avg) MIN; CKE is HIGH; CS_n is HIGH; All banks idle; CA bus inputs are SWITCHING; Data bus inputs are STABLE I DD2N2 VDD2 22 IDD2N,in VDDQ 1.2 IDD2NS1 VDD1 1.2 mA All devices in idle non power-down standby current with clock stop CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS_n is HIGH; All banks idle; CA bus inputs are STABLE; Data bus inputs are STABLE I DD2NS2 VDD2 12 IDD2NS,in VDDQ 1.2 IDD3P1 VDD1 1.6 mA All devices in active power-down standby current tCK = tCK(avg) MIN; CKE is LOW; CS_n is HIGH; One bank active; CA bus inputs are SWITCHING; Data bus inputs are STABLE I DD3P2 VDD2 10 IDD3P,in VDDQ 0.2 IDD3PS1 VDD1 1.6 mA All devices in active power-down standby current with clock stop CK_t = LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; One bank active; CA bus inputs are STABLE; Data bus inputs are STABLE I DD3PS2 VDD2 10 IDD3PS,in VDDQ 0.2 Embedded LPDDR2 SDRAM IDD Specifications – Dual Die, Single Channel PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 4: IDD Specifications (Continued) VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –30°C to +85°C Symbol Supply Speed Unit Parameter/Condition800 IDD3N1 VDD1 2.4 mA All devices in active non power-down standby current tCK = tCK(avg) MIN; CKE is HIGH; CS_n is HIGH; One bank active; CA bus inputs are SWITCHING; Data bus inputs are STABLE I DD3N2 VDD2 34 IDD3N,in VDDQ 1.2 IDD3NS1 VDD1 2.4 mA All devices in active non power-down standby current with clock stop CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS_n is HIGH; One bank active; CA bus inputs are STABLE; Data bus inputs are STABLE I DD3NS2 VDD2 24 IDD3NS,in VDDQ 1.2 IDD4R1 VDD1 2 mA One device in operating burst read; Another device in deep power-down. Conditions for operating devices are: tCK = tCK(avg) MIN; CS_n is HIGH between valid commands; One bank active; BL = 4; RL = RL (MIN); CA bus inputs are SWITCHING; 50% data change each burst transfer I DD4R2 VDD2 130 IDD4W1 VDD1 2 mA One device in operating burst write; Another device in deep power-down. Conditions for operating devices are: tCK = tCK(avg) MIN; CS_n is HIGH between valid commands; One bank active; BL = 4; WL = WL (MIN); CA bus inputs are SWITCHING; 50% data change each burst transfer I DD4W2 VDD2 120 IDD4W,in VDDQ 1 IDD51 VDD1 20 mA One device in all bank auto-refresh; Another device in deep power-down. Conditions for operating devices are: tCK = tCK(avg) MIN; CKE is HIGH between valid commands; tRC = tRFCab (MIN); Burst refresh; CA bus inputs are SWITCHING; Data bus inputs are STABLE I DD52 VDD2 120 IDD5,in VDDQ 0.6 IDD5AB1 VDD1 2 mA One device in all bank auto-refresh; Another device in deep power-down. Conditions for operating devices are: tCK = tCK(avg) MIN; CKE is HIGH between valid commands; tRC = tREFI; CA bus inputs are SWITCHING; Data bus inputs are STABLE I DD5AB2 VDD2 15 IDD5AB,in VDDQ 0.6 Embedded LPDDR2 SDRAM IDD Specifications – Dual Die, Single Channel PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 4: IDD Specifications (Continued) VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –30°C to +85°C Symbol Supply Speed Unit Parameter/Condition800 IDD5PB1 VDD1 2 mA One device in per bank auto-refresh; Another device in deep power-down. Conditions for operating devices are: tCK = tCK(avg) MIN; CKE is HIGH between valid commands; tRC = tREFIpb; CA bus inputs are SWITCHING; Data bus inputs are STABLE I DD5PB2 VDD2 15 IDD5PB,in VDDQ 0.6 IDD81 VDD1 32 μA All devices in deep power-down. CK_t = LOW, CK _c = HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE I DD82 VDD2 12 IDD8,in VDDQ 24 Notes: 1. Published I DD values are the maximum of the distribution of the arithmetic mean. 2. I DD current specifications are tested after the device is properly initialized. Table 5: IDD6 Partial-Array Self Refresh Current at 45°C VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V PASR Supply Value Unit Parameter/Conditions Full array V DD1 400 μA All devices in self refresh CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE V DD2 1600 VDDQ 20 1/2 array V DD1 320 VDD2 1000 VDDQ 20 1/4 array V DD1 260 VDD2 600 VDDQ 20 1/8 array V DD1 240 VDD2 400 VDDQ 20 Note: 1. I DD6 45°C is the typical of the distribution of the arithmetic mean. Embedded LPDDR2 SDRAM IDD Specifications – Dual Die, Single Channel PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 6: IDD6 Partial-Array Self Refresh Current at 85°C VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V PASR Supply Value Unit Parameter/Conditions Full array V DD1 1800 μA All devices in self refresh CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE V DD2 6400 VDDQ 24 1/2 array V DD1 1300 VDD2 4400 VDDQ 24 1/4 array V DD1 1100 VDD2 3400 VDDQ 24 1/8 array V DD1 1000 VDD2 2800 VDDQ 24 Note: 1. I DD6 85°C is the maximum of the distribution of the arithmetic mean. Embedded LPDDR2 SDRAM IDD Specifications – Dual Die, Single Channel PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 2: Single-Rank, Dual-Die, Single-Channel Package Block Diagram Die 0 Die 1 CA[9:0] DQ[15:0] x16 DQ[31:16] x16 CS_n CKE CK_t CK_c DM[3:2] DM[1:0] DQ[31:16], DQS[3:2]_t, DQS[3:2]_c DQ[15:0], DQS[1:0]_t, DQS[1:0]_c ZQ0 RZQ0 ZQ1 RZQ1 VDD1 VDD2 VDDQ VSS VREFDQ VREFCA Embedded LPDDR2 SDRAM Package Block Diagrams PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 3: 168-Ball PoP FBGA (12mm x 12mm) Seating plane 0.08 A Ball A1 ID A

0.2 MIN

0.7 ±0.1

11 CTR

12 ±0.1

0.5 TYP

12 ±0.1 168X Ø0.325 Dimensions apply to solder balls post- reflow on Ø0.27 SMD ball pads. — 0.08 A B C D E F G H J K L M N P R T U V W Y AA AB AC 23 21 19 17 15 13 11 9 7 5 3 1 22 20 18 16 14 12 10 8 6 4 2 Note: 1. All dimensions are in millimeters. Embedded LPDDR2 SDRAM Package Dimensions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 4: 168-Ball PoP Single-Channel FBGA – 2 x 4Gb Die, 12mm x 12mm 7RS9LHZ EDOOGRZQ 966 966 &.BF &.BW 966 966 966 1& 1& &.( 966 966 966 966 966 966 966 966 966 '46 BF '46 BW '46 BW '46 BF &6BQ 966 966 966 966 1& 1&1& 966 966 966 9'' 9''9'' 9'' 9''4 9''4 9''4 9''4 9''4 9''4 9''4 9''49''4 9''4 95()'4 966 9'' 9''4 '46 BF '46 BW 966 966966966966 9'' 9'' 9'' 95()&$ 9'' 9'' 9'' '46 BW '46 BF 9''4 9'' 9'' Embedded LPDDR2 SDRAM Ball Assignments PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

The ball/pad description table below is a comprehensive list of signals for the device family. All signals listed may not be supported on this device. See Ball Assignments for information specific to this device. Table 7: Ball/Pad Descriptions Symbol Type Description CA[9:0] Input Command/address inputs: Provide the command and address inputs according to the command truth table. CK_t, CK_c Input Clock: Differential clock inputs. All CA inputs are sampled on both rising and falling edges of CK. CS and CKE inputs are sampled at the rising edge of CK. AC timings are ref- erenced to clock. CKE Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, in- put buffers, and output drivers. Power-saving modes are entered and exited via CKE tran- sitions. CKE is considered part of the command code. CKE is sampled on the rising edge of CK. CS_n Input Chip select: Considered part of the command code and is sampled on the rising edge of CK. DM[3:0] Input Input data mask: Input mask signal for write data. Although DM balls are input-only, the DM loading is designed to match that of DQ and DQS balls. DM[3:0] is DM for each of the four data bytes, respectively. DQ[31:0] I/O Data input/output: Bidirectional data bus. DQS[3:0]_t, DQS[3:0]_c I/O Data strobe: Bidirectional (used for read and write data) and complementary (DQS_t and DQS_c). It is edge-aligned output with read data and centered input with write data. DQS[3:0]_t/DQS[3:0]_c is DQS for each of the four data bytes, respectively. V DDQ Supply DQ power supply: Isolated on the die for improved noise immunity. VSSQ Supply DQ ground: Isolated on the die for improved noise immunity. VDD1 Supply Core power: Supply 1. VDD2 Supply Core power: Supply 2. VSS Supply Common ground. VREFCA, VREFDQ Supply Reference voltage: VREFCA is reference for command/address input buffers, VREFDQ is ref- erence for DQ input buffers. ZQ[1:0] Reference External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. NU – Not usable: Do not connect. NC – No connect: Not internally connected. (NC) – No connect: Balls indicated as (NC) are no connects; however, they could be connected together internally. Embedded LPDDR2 SDRAM Ball Descriptions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Mobile LPDDR2 is a high-speed SDRAM internally configured as a 4- or 8-bank memory device. The device uses a double data rate architecture on the command/address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus is used to transmit command, address, and bank information. Each command uses one clock cy- cle, during which command information is transferred on both the rising and falling edges of the clock. The LPDDR2-S4 device uses a double data rate architecture on the DQ pins to achieve high- speed operation. The double data rate architecture is essentially a 4n prefetch ar- chitecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR2-S4 effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal SDRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. Read and write access is burst oriented; access starts at a selected location and contin- ues for a programmed number of locations in a programmed sequence. Access begins with the registration of an ACTIVATE command followed by a READ or WRITE command. Registered address and BA bits that coincide with the ACTIVATE command are used to select the row and bank to be accessed. Registered address bits that coincide with the READ or WRITE command are used to select the bank and the starting column location for the burst access. Embedded LPDDR2 SDRAM Functional Description PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 5: Functional Block Diagram CS_n CA[9:0] Address/command decoder Input and Output buffer Latch circuit Data control circuit Control logic Column address buffer and burst counter Row address buffer and refresh counter Mode register Clock generator DQ CK_t CK_c CKE DQS_t DQS_c DM Bank n Column decoder Row decoder Memory cell array Bank 0 Sense amp. Note: 1. 512Mb is a 4-bank only. Simplified State Diagram The state diagram provides a simplified illustration of allowed state transitions and the related commands to control them. For a complete definition of the device behavior, the information provided by the state diagram should be integrated with the truth ta- bles and timing specification. The truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all the banks. Embedded LPDDR2 SDRAM Simplified State Diagram PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 6: Simplified State Diagram Power applied Resetting Self refreshing Refreshing Power-on Resetting MR reading Idle MR reading Active MR reading Active power-down Idle power-down Deep power-down Idle1 Active BSTBST PR,PRA Precharging MR writing Writing Reading Reading with auto precharge Writing with auto precharge Resetting power-down RESET MRR RESET MRR MRW MRR WR RD PD PDX PDX PD PDX PD DPDX DPD SREF REF WRA WRA RDA RDA SREFX RDWR Automatic sequence Command sequence PR = PRECHARGE PRA = PRECHARGE ALL ACT = ACTIVATE WR(A) = WRITE (with auto precharge) RD(A) = READ (with auto precharge) BST = BURST TERMINATE RESET = RESET is achieved through MRW command MRW = MODE REGISTER WRITE MRR = MODE REGISTER READ PD = enter power-down PDX = exit power-down SREF = enter self refresh SREFX = exit self refresh DPD = enter deep power-down DPDX = exit deep power-down REF = REFRESH PR, PRA ACT Note: 1. All banks are precharged in the idle state. Embedded LPDDR2 SDRAM Simplified State Diagram PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Power-Up and Initialization The device must be powered up and initialized in a predefined manner. Power-up and initialization by means other than those specified will result in undefined operation. Voltage Ramp and Device Initialization The following sequence must be used to power up the device. Unless specified other- wise, this procedure is mandatory (see the Voltage Ramp and Initialization Sequence figure). Power-up and initialization by means other than those specified will result in undefined operation. 1. Voltage Ramp Beginning While applying power (after Ta), CKE must be held LOW (≤0.2 × V DD2), and all other in- puts must be between VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW . On or before the completion of the voltage ramp (Tb), CKE must be held LOW . DQ, DM, DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latchup. CK_t, CK_c, CS_n, and CA input levels must be between VSS and VDD2 during voltage ramp to avoid latchup. The following conditions apply for voltage ramp:

Ta is the point when any power supply first reaches 300mV .
Noted conditions apply between Ta and power-down (controlled or uncontrolled).
Tb is the point at which all supply and reference voltages are within their defined op- erating ranges.
Power ramp duration tINIT0 (Tb - Ta) must not exceed 20ms.
For supply and reference voltage operating conditions, see the Recommended DC Operating Conditions table.
The voltage difference between any of V SS, and VSSQ pins must not exceed 100mV . 2. Voltage Ramp Completion After Ta is reached: DD1 must be greater than VDD2 - 200mV
V DD1 and VDD2 must be greater than VDDQ - 200mV
V REF must always be less than all other supply voltages Beginning at Tb, CKE must remain LOW for at least tINIT1 = 100ns, after which CKE can be asserted HIGH. The clock must be stable at least tINIT2 = 5 × tCK prior to the first CKE LOW-to-HIGH transition (Tc). CKE, CS_n, and CA inputs must observe setup and hold requirements (tIS, tIH) with respect to the first rising clock edge (and to subse- quent falling and rising edges). If any MRRs are issued, the clock period must be within the range defined for tCKb (18ns to 100ns). MRWs can be issued at normal clock frequencies as long as all AC tim- ings are met. Some AC parameters (for example, tDQSCK) could have relaxed timings (such as tDQSCKb) before the system is appropriately configured. While keeping CKE HIGH, NOP commands must be issued for at least tINIT3 = 200μs (Td). Embedded LPDDR2 SDRAM Power-Up and Initialization PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

RESET Command After tINIT3 is satisfied, the MRW RESET command must be issued (Td). An optional PRECHARGE ALL command can be issued prior to the MRW RESET command. Wait at least tINIT4 while keeping CKE asserted and issuing NOP commands. 4. MRRs and Device Auto Initialization (DAI) Polling After tINIT4 is satisfied (Te), only MRR commands and power-down entry/exit com- mands are supported. After Te, CKE can go LOW in alignment with power-down entry and exit specifications (see Power-Down). The MRR command can be used to poll the DAI bit, which indicates when device auto initialization is complete; otherwise, the controller must wait a minimum of tINIT5 or until the DAI bit is set before proceeding. Because the memory output buffers are not properly configured by Te, some AC param- eters must use relaxed timing specifications before the system is appropriately config- ured. After the memory device sets the DAI bit (MR0, DAI) to zero, indicating DAI complete, the device is in the idle state (Tf). DAI status can be determined by issuing the MRR command to MR0. The device sets the DAI bit no later than tINIT5 after the RESET command. The control- ler must wait at least tINIT5 or until the DAI bit is set before proceeding. 5. ZQ Calibration After tINIT5 (Tf), the MRW initialization calibration (ZQ calibration) command can be issued to the memory (MR10). This command is used to calibrate output impedance over process, voltage, and tem- perature. In systems where more than one Mobile LPDDR2 device exists on the same bus, the controller must not overlap MRW ZQ calibration commands. The device is ready for normal operation after tZQINIT . 6. Normal Operation After (Tg), the MRW command must be used to properly configure the memory, includ- ing, for example, output buffer drive strength, latencies,and so on. Specifically, MR1, MR2, and MR3 must be set to configure the memory for the target frequency and mem- ory configuration. After the initialization sequence is complete, the device is ready for any valid command. After Tg, the clock frequency can be changed using the procedure described in Input Clock Frequency Changes and Stop Events. Embedded LPDDR2 SDRAM Power-Up and Initialization PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 7: Voltage Ramp and Initialization Sequence Ta Tb Tc Td Te Tf Tg RESET MRR ZQ_CAL Valid CK_c tINIT0 tINIT1 tINIT3 tINIT4 tZQINIT tINIT5 tISCKE PD tINIT2 CK_t Supplies CKE CA DQ Note: 1. High-Z on the CA bus indicates valid NOP. Table 8: Initialization Timing Parameters Parameter Value Unit CommentMin Max tINIT0 – 20 ms Maximum voltage ramp time tINIT1 100 – ns Minimum CKE LOW time after completion of voltage ramp tINIT2 5 – tCK Minimum stable clock before first CKE HIGH tINIT3 200 – μs Minimum idle time after first CKE assertion tINIT4 1 – μs Minimum idle time after RESET command tINIT5 – 10 μs Maximum duration of device auto initialization tZQINIT 1 – μs ZQ initial calibration (S4 devices only) tCKb 18 100 ns Clock cycle time during boot Note: 1. The tINIT0 maximum specification is not a tested limit and should be used as a general guideline. For voltage ramp times exceeding tINIT0 MAX, contact the factory. Initialization After RESET (Without Voltage Ramp) If the RESET command is issued before or after the power-up initialization sequence, the reinitialization procedure must begin at Td. Power-Off Sequence While powering off, CKE must be held LOW (≤0.2 × VDD2); all other inputs must be be- tween VILmin and VIHmax. The device outputs remain at High-Z while CKE is held LOW . Embedded LPDDR2 SDRAM Power-Off Sequence PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

DQ, DM, DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during the power-off sequence to avoid latchup. CK_t, CK_c, CS_n, and CA input levels must be be- tween VSS and VDD2 during the power-off sequence to avoid latchup. Tx is the point where any power supply drops below the minimum value specified in the Recommended DC Operating Conditions table. Tz is the point where all power supplies are below 300mV . After Tz, the device is pow- ered off. Required Power Supply Conditions Between Tx and Tz:

V DD1 must be greater than VDD2 - 200mV
V DD1 must be greater than VDDQ - 200mV
V REF must always be less than all other supply voltages The voltage difference between VSS and VSSQ must not exceed 100mV . For supply and reference voltage operating conditions, see Recommended DC Operat- ing Conditions table. Uncontrolled Power-Off Sequence When an uncontrolled power-off occurs, the following conditions must be met:
At Tx, when the power supply drops below the minimum values specified in the Rec- ommended DC Operating Conditions table, all power supplies must be turned off and all power-supply current capacity must be at zero, except for any static charge re- maining in the system.
After Tz, the point at which all power supplies first reach 300mV , the device must pow- er off. The time between Tx and Tz must not exceed tPOFF . During this period, the rel- ative voltage between power supplies is uncontrolled. VDD1 and VDD2 must decrease with a slope lower than 0.5 V/μs between Tx and Tz. An uncontrolled power-off sequence can occur a maximum of 400 times over the life of the device. Table 9: Power-Off Timing Parameter Symbol Min Max Unit Maximum power-off ramp time tPOFF – 2 sec Mode Register Definition The LPDDR2 device contains a set of mode registers used for programming device op- erating parameters, reading device information and status, and for initiating special op- erations such as DQ calibration, ZQ calibration, and device reset. Mode Register Assignments and Definitions The MRR command is used to read from a register. The MRW command is used to write to a register. An “R” in the access column of the mode register assignment table indi- cates read-only; a “W” indicates write-only; “R/W” indicates read or write capable or enabled. Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 10: Mode Register Assignments Notes 1–5 apply to all parameters and conditions MR# MA[7:0] Function Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link 0 00h Device info R RFU RZQI RFU DI DAI go to MR0 1 01h Device feature 1 W nWR (for AP) WC BT BL go to MR1 2 02h Device feature 2 W RFU RL and WL go to MR2 3 03h I/O config-1 W RFU DS go to MR3 4 04h SDRAM refresh rate R TUF RFU Refresh rate go to MR4 5 05h Basic config-1 R LPDDR2 Manufacturer ID go to MR5 6 06h Basic config-2 R Revision ID1 go to MR6 7 07h Basic config-3 R Revision ID2 go to MR7 8 08h Basic config-4 R I/O width Density Type go to MR8 9 09h Test mode W Vendor-specific test mode go to MR9 10 0Ah I/O calibration W Calibration code go to MR10 11–15 0Bh ≈ 0Fh Reserved – RFU go to MR11 16 10h PASR_Bank W Bank mask go to MR16 17 11h PASR_Seg W Segment mask go to MR17 18–31 12h–1Fh Reserved – RFU go to MR18 32 20h DQ calibration pattern A R See Data Calibration Pattern Description table go to MR32 33–39 21h–27h Do not use go to MR33 40 28h DQ calibration pattern B R See Data Calibration Pattern Description table go to MR40 41–47 29h–2Fh Do not use go to MR41 48–62 30h–3Eh Reserved – RFU go to MR48 63 3Fh RESET W X go to MR63 64–126 40h–7Eh Reserved – RFU go to MR64 127 7Fh Do not use go to MR127 128–190 80h–BEh Reserved for vendor use RVU go to MR128

191 BFh Do not use go to MR191

192–254 C0h–FEh Reserved for vendor use RVU go to MR192

255 FFh Do not use go to MR255

Notes: 1. RFU bits must be set to 0 during MRW. 2. RFU bits must be read as 0 during MRR. 3. For READs to a write-only or RFU register, DQS will be toggled and undefined data is returned. 4. RFU mode registers must not be written. 5. WRITEs to read-only registers must have no impact on the functionality of the device. Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 11: MR0 Device Information (MA[7:0] = 00h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU RZQI RFU DI DAI Table 12: MR0 Op-Code Bit Definitions Notes 1–4 apply to all parameters and conditions Register Information Tag Type OP Definition Device auto initialization status DAI Read-only OP0 0b: DAI complete 1b: DAI in progress Device information DI Read-only OP1 0b:DDR2 Mobile RAM (S4 SDRAM) Built-in self test for RZQ information RZQI Read-only OP[4:3] 01b: ZQ pin might be connected to V DD2 or left floating 10b: ZQ pin might be shorted to ground 11b: ZQ pin self test complete; no error condition de- tected(ZQ-pin may not connect to VDD or float nor short to GND) Notes: 1. If RZQI is supported, it will be set upon completion of the MRW ZQ initialization calibra- tion. 2. If ZQ is connected to V DD2 to set default calibration, OP[4:3] must be set to 01. If ZQ is not connected to VDD2, either OP[4:3] = 01 or OP[4:3] = 10 could indicate a ZQ-pin as- sembly error. It is recommended that the assembly error be corrected. 3. In the case of a possible assembly error (either OP[4:3] = 01 or OP[4:3] = 10, as defined above), the device will default to factory trim settings for RON(output impedance) and will ignore ZQ calibration commands. In either case, the system might not function as intended. 4. If a ZQ self test returns a value of 11b, this indicates that the device has detected a resis- tor connection to the ZQ pin. Note that this result cannot be used to validate the ZQ resistor value, nor does it indicate that the ZQ resistor tolerance meets the specified lim- its (240 ohms ±1%). Table 13: MR1 Device Feature 1 (MA[7:0] = 01h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 nWR (for AP) WC BT BL Table 14: MR1 Op-Code Bit Definitions Feature Type OP Definition Notes BL = burst length Write-only OP[2:0] 010b: BL4 (default) 1 011b: BL8 100b: BL16 All others: Reserved Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 14: MR1 Op-Code Bit Definitions (Continued) Feature Type OP Definition Notes BT = burst type Write-only OP3 0b: Sequential (default) 1b: Interleaved WC = wrap control Write-only OP4 0b: Wrap (default) 1b: No wrap (allowed for BL4 only) nWR = number of tWR clock cycles Write-only OP[7:5] 001b: nWR = 3 (default) 2 010b: nWR = 4 011b: nWR = 5 100b: nWR = 6 101b: nWR = 7 110b: nWR = 8 All others: Reserved Notes: 1. BL16, interleaved is not an official combination to be supported. 2. The programmed value in nWR register is the number of clock cycles that determines when to start internal precharge operation for a WRITE burst with AP enabled. It is de- termined by RU (tWR/tCK). Table 15: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC) Notes 1–5 apply to all parameters and conditions BL BT C3 C2 C1 C0 WC Burst Cycle Number and Burst Address Sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 4A n y X X0 b 0 b W r a p 0123 X X1 b 0 b 2301 Any X X X 0b No wrap yy + y + y + 8S e qX0 b 0 b 0 b W r a p 01234567 X0 b 1 b 0 b 23456701 X1 b 0 b 0 b 45670123 X1 b 1 b 0 b 67012345 I n tX0 b 0 b 0 b 01234567 X0 b 1 b 0 b 23016745 X1 b 0 b 0 b 45670123 X1 b 1 b 0 b 67452301 Any X X X 0b No wrap Illegal (not supported) Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 15: Burst Sequence by Burst Length (BL), Burst Type (BT), and Wrap Control (WC) (Continued) Notes 1–5 apply to all parameters and conditions BL BT C3 C2 C1 C0 WC Burst Cycle Number and Burst Address Sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 6 S e q 0 b 0 b 0 b 0 b W r a p 0123456789ABCDEF 0 b 0 b 1 b 0 b 23456789ABCDEF01 0 b 1 b 0 b 0 b 456789ABCDEF0123 0 b 1 b 1 b 0 b 6789ABCDEF012345 1 b 0 b 0 b 0 b 89ABCDEF01234567 1 b 0 b 1 b 0 b ABCDEF0123456789 1 b 1 b 0 b 0 b CDEF0123456789AB 1 b 1 b 1 b 0 b EF0123456789ABCD Int X X X 0b Illegal (not supported) Any X X X 0b No wrap Illegal (not supported) Notes: 1. C0 input is not present on CA bus. It is implied zero. 2. For BL = 4, the burst address represents C[1:0]. 3. For BL = 8, the burst address represents C[2:0]. 4. For BL = 16, the burst address represents C[3:0]. 5. For no-wrap, BL4, the burst must not cross the page boundary or the sub-page boun- dary. The variable y can start at any address with C0 equal to 0, but must not start at any address shown in the following table. Table 16: No-Wrap Restrictions Width 64Mb 128Mb/256Mb 512Mb/1Gb/2Gb 4Gb/8Gb Cannot cross full-page boundary x16 FE, FF, 00, 01 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001 7FE, 7FF, 000, 001 x32 7E, 7F, 00, 01 FE, FF, 00, 01 1FE, 1FF, 000, 001 3FE, 3FF, 000, 001 Cannot cross sub-page boundary x16 7E, 7F, 80, 81 0FE, 0FF, 100, 101 1FE, 1FF, 200, 201 3FE, 3FF, 400, 401 x32 None None None None Note: 1. No-wrap BL = 4 data orders shown are prohibited. Table 17: MR2 Device Feature 2 (MA[7:0] = 02h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU RL and WL Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 18: MR2 Op-Code Bit Definitions Feature Type OP Definition RL and WL Write-only OP[3:0] 0001b: RL3/WL1 (default) 0010b: RL4/WL2 0011b: RL5/WL2 0100b: RL6/WL3 0101b: RL7/WL4 0110b: RL8/WL4 All others: Reserved Table 19: MR3 I/O Configuration 1 (MA[7:0] = 03h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 RFU DS Table 20: MR3 Op-Code Bit Definitions Feature Type OP Definition DS Write-only OP[3:0] 0000b: Reserved 0001b: 34.3 ohm typical 0010b: 40 ohm typical (default) 0011b: 48 ohm typical 0100b: 60 ohm typical 0101b: Reserved 0110b: 80 ohm typical 0111b: 120 ohm typical All others: Reserved Table 21: MR4 Device Temperature (MA[7:0] = 04h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 TUF RFU SDRAM refresh rate Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 22: MR4 Op-Code Bit Definitions Notes 1–8 apply to all parameters and conditions Feature Type OP Definition SDRAM refresh rate Read-only OP[2:0] 000b: SDRAM low temperature operating limit exceeded 001b: 4 × tREFI, 4 × tREFIpb, 4 × tREFW 010b: 2 × tREFI, 2 × tREFIpb, 2 × tREFW 011b: 1 × tREFI, 1 × tREFIpb, 1 × tREFW (≤85˚C) 100b: Reserved 101b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, do not derate SDRAM AC timing 110b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, derate SDRAM AC timing 111b: SDRAM high temperature operating limit exceeded Temperature up- date flag (TUF) Read-only OP7 0b: OP[2:0] value has not changed since last read of MR4 1b: OP[2:0] value has changed since last read of MR4 Notes: 1. A MODE REGISTER READ from MR4 will reset OP7 to 0. 2. OP7 is reset to 0 at power-up. 3. If OP2 = 1, the device temperature is greater than 85˚C. 4. OP7 is set to 1 if OP[2:0] has changed at any time since the last MR4 read. 5. The device might not operate properly when OP[2:0] = 000b or 111b. 6. For specified operating temperature range and maximum operating temperature, refer to the Operating Temperature Range table. 7. LPDDR2 devices must be derated by adding 1.875ns to the following core timing param- eters: tRCD, tRC, tRAS, tRP, and tRRD. The tDQSCK parameter must be derated as speci- fied in AC Timing. Prevailing clock frequency specifications and related setup and hold timings remain unchanged. 8. The recommended frequency for reading MR4 is provided in Temperature Sensor. Table 23: MR5 Basic Configuration 1 (MA[7:0] = 05h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 LPDDR2 Manufacturer ID Table 24: MR5 Op-Code Bit Definitions Feature Type OP Definition Manufacturer ID Read-only OP[7:0] 00000011b All others: Reserved Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 25: MR6 Basic Configuration 2 (MA[7:0] = 06h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Note: 1. MR6 is vendor-specific. Table 26: MR6 Op-Code Bit Definitions Feature Type OP Definition 0000 0001b: Version B 0000 0010b: Version C 0000 0010b: Version D(512Mb only) 0000 0011b: Version D Table 27: MR7 Basic Configuration 3 (MA[7:0] = 07h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Table 28: MR7 Op-Code Bit Definitions Feature Type OP Definition Note: 1. MR7 is vendor-specific. Table 29: MR8 Basic Configuration 4 (MA[7:0] = 08h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 I/O width Density Type Table 30: MR8 Op-Code Bit Definitions Feature Type OP Definition Type Read-only OP[1:0] 00b: S4 SDRAM 01b: S2 SDRAM 10b: Reserved 11b: Reserved Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 30: MR8 Op-Code Bit Definitions (Continued) Feature Type OP Definition Density Read-only OP[5:2] 0000b: 64Mb 0001b: 128Mb 0010b: 256Mb 0011b: 512Mb 0100b: 1Gb 0101b: 2Gb 0110b: 4Gb 0111b: 8Gb 1000b: 16Gb 1001b: 32Gb All others: Reserved I/O width Read-only OP[7:6] 00b: x32 01b: x16 10b: x8 11b: not used Table 31: MR9 Test Mode (MA[7:0] = 09h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Vendor-specific test mode Table 32: MR10 Calibration (MA[7:0] = 0Ah) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 S4 Calibration code Table 33: MR10 Op-Code Bit Definitions Notes 1–6 apply to all parameters and conditions Feature Type OP Definition Calibration code Write-only OP[7:0] 0xFF: Calibration command after initialization 0xAB: Long calibration 0x56: Short calibration 0xC3: ZQRESET All others: Reserved Notes: 1. Host processor must not write MR10 with reserved values. 2. The device ignores calibration commands when a reserved value is written into MR10. 3. See AC timing table for the calibration latency. Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

If ZQ is connected to V SS through RZQ, either the ZQ calibration function (see MODE REGISTER WRITE command) or default calibration (through the ZQRESET command) is supported. If ZQ is connected to VDD2, the device operates with default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection must not change after power is supplied to the device. 5. LPDDR2 devices that do not support calibration shall ignore the ZQ Calibration com- mand. 6. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. Table 34: MR[11:15] Reserved (MA[7:0] = 0Bh–0Fh) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Reserved Table 35: MR16 PASR Bank Mask (MA[7:0] = 010h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Bank mask (4-bank or 8-bank) Table 36: MR16 Op-Code Bit Definitions Feature Type OP Definition Bank[7:0] mask Write-only OP[7:0] 0b: refresh enable to the bank = unmasked (default) 1b: refresh blocked = masked Note: 1. For 4-bank devices, only OP[3:0] are used. Table 37: MR16 Bank and OP corresponding table Feature Type OP 4-Bank Mask 8-Bank Mask Bank # Bank Address Bank # Bank Address Bank[7:0] mask Write-only

0 Bank 0 000b Bank 0 000b

1 Bank 1 001b Bank 1 001b

2 Bank 2 010b Bank 2 010b

3 Bank 3 011b Bank 3 011b

Note: 1. Each bank can be masked independently by setting each OP value. Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 38: MR17 PASR Segment Mask (MA[7:0] = 011h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Segment mask Note: 1. This table applies for 1Gb to 8Gb devices only. Table 39: MR17 PASR Segment Mask Definitions (1Gb - 8Gb only) Feature Type OP Definition Segment[7:0] mask Write-only OP[7:0] 0b: refresh enable to the segment: = unmasked (default) 1b: refresh blocked: = masked Table 40: MR17 PASR Row Address Ranges in Masked Segments Segment OP Segment Mask 1Gb 2Gb, 4Gb 8Gb 0 0 XXXXXXX1 000b 1 1 XXXXXX1X 001b 2 2 XXXXX1XX 010b 3 3 XXXX1XXX 011b 4 4 XXX1XXXX 100b 5 5 XX1XXXXX 101b 6 6 X1XXXXXX 110b 7 7 1XXXXXXX 111b Note: 1. X is “Don’t Care” for the designated segment. Embedded LPDDR2 SDRAM Mode Register Definition PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 41: Reserved Mode Registers Mode Reg- ister MA Address Restriction OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 MR[18:19] MA[7:0] 12h–13h RFU Reserved MR[20:31] 14h–1Fh NVM 1 MR[33:39] 21h–27h DNU 1 MR[41:47] 29h–2Fh MR[48:62] 30h–3Eh RFU MR[64:126] 40h–7Eh RFU MR127 7Fh DNU MR[128:190] 80h–BEh RVU 1 MR191 BFh DNU MR[192:254] C0h–FEh RVU MR255 FFh DNU Note: 1. NVM = nonvolatile memory use only; DNU = Do not use; RVU = Reserved for vendor use. Table 42: MR32 DQ Calibration Pattern A (MA[7:0] = 20H) MR32 Reads Reads to MR32 return DQ Calibration Pattern A Table 43: MR40 DQ Calibration Pattern B (MA[7:0] = 28H) MR40 Reads Reads to MR40 return DQ Calibration Pattern B Table 44: MR63 RESET (MA[7:0] = 3Fh) – MRW Only OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 X Note: 1. For additional information on MRW RESET see MODE REGISTER WRITE Command. Commands and Timing The setup and hold timings shown in the figures below apply for all commands. Embedded LPDDR2 SDRAM Commands and Timing PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

cycle time of the device (tRC). The minimum time interval between ACTIVATE com- mands to different banks is tRRD. Figure 10: ACTIVATE Command Bank n row addr Row addr ACTIVATE NOP ACTIVATE READ PRECHARGE ACTIVATENOP NOP Bank m row addr Row addr Bank n col addr Col addr Bank n Bank n row addr Row addr T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CK_c CK_t CA[9:0] CMD tRRD tRCD tRC tRAS tRP Notes: 1. tRCD = 3, tRP = 3, tRRD = 2. 2. A PRECHARGE ALL command uses tRPab timing, and a single-bank PRECHARGE com- mand uses tRPpb timing. In this figure, tRP is used to denote either an all-bank PRE- CHARGE or a single-bank PRECHARGE. 8-Bank Device Operation Two rules regarding 8-bank device operation must be observed: One rule restricts the number of sequential ACTIVATE commands that can be issued; the second rule pro- vides additional RAS precharge time for a PRECHARGE ALL command. The 8-Bank Device Sequential Bank Activation Restriction: No more than four banks can be activated (or refreshed, in the case of REFpb) in a rolling tFAW window. To con- vert to clocks, divide tFAW[ns] by tCK[ns], and round up to the next integer value. For example, if RU(tFAW/tCK) is 10 clocks, and an ACTIVATE command is issued in clock n, no more than three further ACTIVATE commands can be issued at or between clock n + 1 and n + 9. REFpb also counts as bank activation for purposes of tFAW. The 8-Bank Device PRECHARGE ALL Provision: tRP for a PRECHARGE ALL command must equal tRPab, which is greater than tRPpb. Embedded LPDDR2 SDRAM ACTIVATE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 11: tFAW Timing (8-Bank Devices) CK_c CK_t CA[9:0] Tn Tn+ Tm Tm+ Tx Tx+ Ty Ty + 1 Ty + 2 Tz Tz + 1 Tz + 2 Bank A ACTIVATE NOPCMD Bank A Bank B ACTIVATE NOP Bank B Bank C ACTIVATE NOP Bank C Bank D ACTIVATE NOP Bank D NOP NOP Bank E ACTIVATE NOP Bank E tRRD tFAW tRRD tRRD Note: 1. Exclusively for 8-bank devices. Read and Write Access Modes After a bank is activated, a READ or WRITE command can be issued with CS_n LOW, CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine whether the access cycle is a READ operation (CA2 HIGH) or a WRITE operation (CA2 LOW). A single READ or WRITE command initiates a burst READ or burst WRITE operation on successive clock cycles. A new burst access must not interrupt the previous 4-bit burst operation when BL = 4. When BL = 8 or BL = 16, a READ can be interrupted by a READ and a WRITE can be interrupted by a WRITE, provided that the interrupt occurs on a 4-bit boundary and that tCCD is met. Burst READ Command The burst READ command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2 HIGH at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and CA1f–CA9f, determine the starting column address for the burst. The read latency (RL) is defined from the rising edge of the clock on which the READ command is issued to the rising edge of the clock from which the tDQSCK delay is measured. The first valid data is available RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock when the READ command is issued. The data strobe output is driven LOW tRPRE before the first valid rising strobe edge. The first bit of the burst is synchronized with the first rising edge of the data strobe. Each subsequent data-out appears on each DQ pin, edge- aligned with the data strobe. The RL is programmed in the mode registers. Pin input timings for the data strobe are measured relative to the crosspoint of DQS and its complement, DQS#. Embedded LPDDR2 SDRAM Read and Write Access Modes PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 16: tDQSCKDL Timing Col addrBank n col addr READ NOP Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 Tm + 8 CA [9:0] CMD DQS# DQS DQ RL = 5 Transitioning data NOP NOP NOP NOP tDQSCKm NOP DOUT A0 D OUT A1 D OUT A2 D OUT A3 NOP NOP CK# CK Col addrBank n col addr READ NOP Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 CA [9:0] CMD DQS# DQS DQ RL = 5 …32ms maximum 32ms maximum… NOP NOP NOP NOP tDQSCKn NOP DOUT A0 D OUT A1 D OUT A2 D OUT A3 NOP NOP CK# CK Notes: 1. tDQSCKDL = (tDQSCKn - tDQSCKm). 2. tDQSCKDL (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm) pair within any 32ms rolling window. Embedded LPDDR2 SDRAM Burst READ Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 17: tDQSCKDM Timing Col addrBank n col addr READ NOP Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 Tm + 8 CA [9:0] CMD DQS# DQS DQ RL = 5 Transitioning data NOP NOP NOP NOP tDQSCKm NOP DOUT A0 D OUT A1 D OUT A2 D OUT A3 NOP NOP CK# CK Col addrBank n col addr READ NOP Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 CA [9:0] CMD DQS# DQS DQ RL = 5 …1.6μs maximum 1.6μs maximum… NOP NOP NOP NOP tDQSCKn NOP DOUT A0 D OUT A1 D OUT A2 D OUT A3 NOP NOP CK# CK Notes: 1. tDQSCKDM = (tDQSCKn - tDQSCKm). 2. tDQSCKDM (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm) pair within any 1.6μs rolling window. Embedded LPDDR2 SDRAM Burst READ Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 18: tDQSCKDS Timing Col addrBank n col addr READ NOP Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 Tm + 8 CA [9:0] CMD DQS# DQS DQ RL = 5 Transitioning data NOP NOP NOP NOP tDQSCKm NOP DOUT A0 D OUT A1 D OUT A2 D OUT A3DOUT A0 DOUT A1 DOUT A2 D OUT A3DOUT A0 D OUT A1 D OUT A2 D OUT A3DOUT A0 D OUT A1 D OUT A2 D OUT A3DOUT A2 D OUT A3 NOP NOP CK# CK Col addrBank n col addr READ NOP Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 CA [9:0] CMD DQS# DQS DQ RL = 5 …160ns maximum 160ns maximum… NOP NOP NOP NOP tDQSCKn NOP DOUT A0 D OUT A1 D OUT A2 D OUT A3 DOUT A4 NOP NOP CK# CK Notes: 1. tDQSCKDS = (tDQSCKn - tDQSCKm). 2. tDQSCKDS (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any (tDQSCKn, tDQSCKm) pair for READs within a consecutive burst, within any 160ns rolling window. Embedded LPDDR2 SDRAM Burst READ Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

READs Interrupted by a READ A burst READ can be interrupted by another READ with a 4-bit burst boundary, provi- ded that tCCD is met. Figure 21: READ Burst Interrupt Example – RL = 3, BL = 8, tCCD = 2 READ NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK# CK CA[9:0] CMD DQS# DQS DQ RL = 3 Transitioning data READ NOP NOP NOP tCCD = 2 NOP DOUT B0 D OUT B1 D OUT B2 D OUT B3 DOUT B4 D OUT B5DOUT A0 DOUT A1 DOUT A2 D OUT A3 NOP NOP Bank n col addr a Col addr a Bank n col addr b Col addr b Note: 1. READs can only be interrupted by other READs or the BST command. Burst WRITE Command The burst WRITE command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2 LOW at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and CA1f–CA9f, determine the starting column address for the burst. Write latency (WL) is defined from the rising edge of the clock on which the WRITE command is issued to the rising edge of the clock from which the tDQSS delay is measured. The first valid data must be driven WL × tCK + tDQSS from the rising edge of the clock from which the WRITE command is issued. The data strobe signal (DQS) must be driven LOW tWPRE prior to data input. The burst cycle data bits must be applied to the DQ pins tDS prior to the associated edge of the DQS and held valid until tDH after that edge. Burst data is sampled on successive edges of the DQS until the 4-, 8-, or 16-bit burst length is com- pleted. After a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the same bank can be issued. Pin input timings are measured relative to the crosspoint of DQS and its complement, DQS#. Embedded LPDDR2 SDRAM Burst WRITE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

WRITEs Interrupted by a WRITE A burst WRITE can only be interrupted by another WRITE with a 4-bit burst boundary, provided that tCCD (MIN) is met. A WRITE burst interrupt can occur on even clock cycles after the initial WRITE com- mand, provided that tCCD (MIN) is met. Figure 26: WRITE Burst Interrupt Timing – WL = 1, BL = 8, tCCD = 2 Bank m col addr a Col addr a WRITE NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK# CK CA[9:0] CMD DQS# DQS DQ WL = 1 Transitioning data WRITE NOP NOP NOP tCCD = 2 NOP DIN B0 DIN B1 DIN B2 DIN B3 DIN B4 DIN B5 DIN B6 DIN B7DIN A0 DIN A1 DIN A2 DIN A3 NOP NOP Bank n col addr b Col addr b Notes: 1. WRITEs can only be interrupted by other WRITEs or the BST command. 2. The effective burst length of the first WRITE equals two times the number of clock cycles between the first WRITE and the interrupting WRITE. BURST TERMINATE Command The BURST TERMINATE (BST) command is initiated with CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 LOW at the rising edge of the clock. A BST command can be issued only to terminate an active READ or WRITE burst. Therefore, a BST command can be issued only up to and including BL/2 - 1 clock cycles after a READ or WRITE command. The effective burst length of a READ or WRITE command truncated by a BST command is as follows:

Effective burst length = 2 × (number of clock cycles from the READ or WRITE com- mand to the BST command).
If a READ or WRITE burst is truncated with a BST command, the effective burst length of the truncated burst should be used for BL when calculating the minimum READ- to-WRITE or WRITE-to-READ delay.
The BST command only affects the most recent READ or WRITE command. The BST command truncates an ongoing READ burst RL × tCK + tDQSCK + tDQSQ after the ris- ing edge of the clock where the BST command is issued. The BST command truncates an ongoing WRITE burst WL × tCK + tDQSS after the rising edge of the clock where the BST command is issued. Embedded LPDDR2 SDRAM BURST TERMINATE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

The 4-bit prefetch architecture enables BST command assertion on even clock cycles following a WRITE or READ command. The effective burst length of a READ or WRITE command truncated by a BST command is thus an integer multiple of four. Figure 27: Burst WRITE Truncated by BST – WL = 1, BL = 16 Bank m col addr a Col addr a WRITE NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_c CK_t CA[9:0] CMD DQS_c DQS_t DQ WL = 1 Transitioning dataBST prohibited NOP NOP BST NOP WL × tCK + tDQSS NOP DIN A4 D IN A5 D IN A6 D IN A7DIN A0 D IN A1 D IN A2 D IN A3 NOP NOP Notes: 1. The BST command truncates an ongoing WRITE burst WL × tCK + tDQSS after the rising edge of the clock where the BST command is issued. 2. BST can only be issued an even number of clock cycles after the WRITE command. 3. Additional BST commands are not supported after T4 and must not be issued until after the next READ or WRITE command. Embedded LPDDR2 SDRAM BURST TERMINATE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 30: Write Data Mask – Second Data Bit Masked DQS_c CK_c DQ Don’t Care DM CMD WL = 2 tDQSSmax tDQSSmin DIN 0 DIN 2 DIN 3 WRITE tWTR tWR DQ DM DIN 0 DIN 2 DIN 3 Case 1: tDQSSmin Case 2: tDQSSmax DIN 1 DIN 1 CK_t DQS_t DQS_c DQS_t Note: 1. For the data mask function, WL = 2, BL = 4 is shown; the second data bit is masked. PRECHARGE Command The PRECHARGE command is used to precharge or close a bank that has been activa- ted. The PRECHARGE command is initiated with CS_n LOW, CA0 HIGH, CA1 HIGH, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The PRECHARGE command can be used to precharge each bank independently or all banks simultaneously. For a 4- bank device, the AB flag and bank address bits BA0 and BA1 are used to determine which bank(s) to precharge. For an 8-bank device, the AB flag and the bank address bits BA0, BA1, and BA2 are used to determine which bank(s) to precharge. The precharged bank(s) will be available for subsequent row access tRPab after an all bank PRECHARGE command is issued, or tRPpb after a single-bank PRECHARGE command is issued. To ensure that an 8-bank device can meet the instantaneous current demand required to operate, the row precharge time ( tRP) for an all bank PRECHARGE in an 8-bank de- vice (tRPab) will be longer than the row precharge time for a single-bank PRECHARGE (tRPpb). For a 4-bank device, tRPab is equal to tRPpb. ACTIVATE to PRECHARGE timing is shown in ACTIVATE Command. Embedded LPDDR2 SDRAM PRECHARGE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 45: Bank Selection for PRECHARGE by Address Bits AB (CA4r) BA2 (CA9r) BA1 (CA8r) BA0 (CA7r) Precharged Bank(s) 4- Bank Device Precharged Bank(s) 8- Bank Device

0000 Bank 0 only Bank 0 only

0001 Bank 1 only Bank 1 only

0010 Bank 2 only Bank 2 only

0011 Bank 3 only Bank 3 only

0100 Bank 0 only Bank 4 only

0101 Bank 1 only Bank 5 only

0110 Bank 2 only Bank 6 only

0111 Bank 3 only Bank 7 only

1 Don’t Care Don’t Care Don’t Care All banks All banks

READ Burst Followed by PRECHARGE For the earliest possible precharge, the PRECHARGE command can be issued BL/2 clock cycles after a READ command. A new bank ACTIVATE command can be issued to the same bank after the row precharge time ( tRP) has elapsed. A PRECHARGE com- mand cannot be issued until after tRAS is satisfied. The minimum READ-to-PRECHARGE time (tRTP) must also satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a READ com- mand. tRTP begins BL/2 - 2 clock cycles after the READ command. If the burst is truncated by a BST command, the effective BL value is used to calculate when tRTP begins. Figure 31: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(tRTP(MIN)/tCK) = 2 Bank m col addr a Col addr a READ NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_c CK_t CA[9:0] CMD DQS_c DQS_t DQ RL = 3 tRP Transitioning data NOP NOP PRECHARGE NOP tRTP NOP DOUT A4 D OUT A5 D OUT A6 DOUT A7DOUT A0 D OUT A1 D OUT A2 D OUT A3 ACTIVATE NOP Bank m Bank m row addr Row addr BL/2 Embedded LPDDR2 SDRAM PRECHARGE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 32: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 3 Bank m col addr a Col addr a READ NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_c CK_t CA[9:0] CMD DQS_c DQS_t DQ RL = 3 tRP Transitioning data NOP PRECHARGE NOPNOP tRTP = 3 BL/2 ACTIVATE DOUT A0 D OUT A1 D OUT A2 D OUT A3 NOP NOP Bank m Bank m row addr Row addr WRITE Burst Followed by PRECHARGE For WRITE cycles, a WRITE recovery time (tWR) must be provided before a PRECHARGE command can be issued. tWR delay is referenced from the completion of the burst WRITE. The PRECHARGE command must not be issued prior to the tWR delay. For WRITE-to-PRECHARGE timings, see the PRECHARGE and Auto Precharge Clarification table. These devices write data to the array in prefetch quadruples (prefetch = 4). An internal WRITE operation can only begin after a prefetch group has been completely latched. The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL + BL/2 + 1 + RU(tWR/tCK) clock cycles. For untruncated bursts, BL is the value set in the mode register. For truncated bursts, BL is the effective burst length. Embedded LPDDR2 SDRAM PRECHARGE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 33: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 Bank n col addr Col addr WRITE NOP T0 T1 T2 T3 T4 Tx Tx + 1 Ty Ty + 1 CK_c CK_t CA[9:0] CMD DQS_c DQS_t DQ WL = 1 tWR Completion of burst WRITE Transitioning data NOP NOP NOP PRECHARGE tDQSSmax NOP DIN A0 D IN A1 D IN A2 D IN A3 ACTIVATE NOP Bank n Bank n row addr Row addr DQS_c DQS_t DQ tDQSSmin ≥tRP DIN A0 D IN A1 D IN A2 D IN A3 Case 1: tDQSSmax Case 2: tDQSSmin Auto Precharge operation Before a new row can be opened in an active bank, the active bank must be precharged using either the PRECHARGE command or the auto precharge function. When a READ or WRITE command is issued to the device, the auto precharge bit (AP) can be set to enable the active bank to automatically begin precharge at the earliest possible mo- ment during the burst READ or WRITE cycle. If AP is LOW when the READ or WRITE command is issued, then normal READ or WRITE burst operation is executed and the bank remains active at the completion of the burst. If AP is HIGH when the READ or WRITE command is issued, the auto precharge func- tion is engaged. This feature enables the PRECHARGE operation to be partially or com- pletely hidden during burst READ cycles (dependent upon READ or WRITE latency), thus improving system performance for random data access. READ Burst with Auto Precharge If AP (CA0f) is HIGH when a READ command is issued, the READ with auto precharge function is engaged. This device starts an auto precharge on the rising edge of the clock BL/2 or BL/2 - 2 + RU( tRTP/tCK) clock cycles later than the READ with auto precharge command, which- ever is greater. For auto precharge calculations, see the PRECHARGE and Auto Pre- charge Clarification table. Embedded LPDDR2 SDRAM PRECHARGE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Following an auto precharge operation, an ACTIVATE command can be issued to the same bank if the following two conditions are satisfied simultaneously:

The RAS precharge time ( tRP) has been satisfied from the clock at which the auto pre- charge begins.
The RAS cycle time ( tRC) from the previous bank activation has been satisfied. Figure 34: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 2 Bank m col addr a Col addr a READ w/AP NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_c CK_t CA[9:0] CMD DQS_c DQS_t DQ RL = 3 Transitioning data NOP NOP NOP ACTIVATE tRTP BL/2 NOP DOUT A0 D OUT A1 D OUT A2 D OUT A3 NOP NOP Bank m row addr Row addr ≥tRPpb WRITE Burst with Auto Precharge If AP (CA0f) is HIGH when a WRITE command is issued, the WRITE with auto precharge function is engaged. The device starts an auto precharge at the clock rising edge tWR cycles after the completion of the burst WRITE. Following a WRITE with auto precharge, an ACTIVATE command can be issued to the same bank if the following two conditions are met:
The RAS precharge time ( tRP) has been satisfied from the clock at which the auto pre- charge begins.
The RAS cycle time ( tRC) from the previous bank activation has been satisfied. Embedded LPDDR2 SDRAM PRECHARGE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 35: WRITE Burst with Auto Precharge – WL = 1, BL = 4 Bank n col addr Col addr WRITE NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_c CK_t CA[9:0] CMD DQS_c DQS_t DQ WL = 1 tWR Transitioning data NOP NOP NOP NOP NOP DIN A0 D IN A1 D IN A2 D IN A3 ACTIVATE NOP Bank n row addr Row addr ≥tRPpb Table 46: PRECHARGE and Auto Precharge Clarification From Command To Command Minimum Delay Between Commands Unit Notes READ PRECHARGE to same bank as READ BL/2 + MAX(2, RU( tRTP/tCK)) - 2 CLK 1 PRECHARGE ALL BL/2 + MAX(2, RU(tRTP/tCK)) - 2 CLK 1 BST PRECHARGE to same bank as READ 1 CLK 1 PRECHARGE ALL 1 CLK 1 READ w/AP PRECHARGE to same bank as READ w/AP BL/2 + MAX(2, RU( tRTP/tCK)) - 2 CLK 1, 2 PRECHARGE ALL BL/2 + MAX(2, RU(tRTP/tCK)) - 2 CLK 1 ACTIVATE to same bank as READ w/AP BL/2 + MAX(2, RU( tRTP/tCK)) - 2 + RU(tRPpb/ tCK) CLK 1 WRITE or WRITE w/AP (same bank) Illegal CLK 3 WRITE or WRITE w/AP (different bank) RL + BL/2 + RU( tDQSCKmax/tCK) - WL + 1 CLK 3 READ or READ w/AP (same bank) Illegal CLK 3 READ or READ w/AP (different bank) BL/2 CLK 3 WRITE PRECHARGE to same bank as WRITE WL + BL/2 + RU( tWR/tCK) + 1 CLK 1 PRECHARGE ALL WL + BL/2 + RU(tWR/tCK) + 1 CLK 1 BST PRECHARGE to same bank as WRITE WL + RU( tWR/tCK) + 1 CLK 1 PRECHARGE ALL WL + RU(tWR/tCK) + 1 CLK 1 Embedded LPDDR2 SDRAM PRECHARGE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 46: PRECHARGE and Auto Precharge Clarification (Continued) From Command To Command Minimum Delay Between Commands Unit Notes WRITE w/AP PRECHARGE to same bank as WRITE w/AP WL + BL/2 + RU( tWR/tCK) + 1 CLK 1, 2 PRECHARGE ALL WL + BL/2 + RU(tWR/tCK) + 1 CLK 1 ACTIVATE to same bank as WRITE w/AP WL + BL/2 + RU( tWR/tCK) + 1 + RU(tRPpb/tCK) CLK 1 WRITE or WRITE w/AP (same bank) Illegal CLK 3 WRITE or WRITE w/AP (different bank) BL/2 CLK 3 READ or READ w/AP (same bank) Illegal CLK 3 READ or READ w/AP (different bank) WL + BL/2 + RU( tWTR/tCK) + 1 CLK 3 PRECHARGE PRECHARGE to same bank as PRECHARGE 1 CLK 1 PRECHARGE ALL 1 CLK 1 PRECHARGE ALL PRECHARGE 1 CLK 1 PRECHARGE ALL 1 CLK 1 Notes: 1. For a given bank, the PRECHARGE period should be counted from the latest PRECHARGE command—either a one-bank PRECHARGE or PRECHARGE ALL—issued to that bank. The PRECHARGE period is satisfied after tRP, depending on the latest PRECHARGE com- mand issued to that bank. 2. Any command issued during the specified minimum delay time is illegal. 3. After READ with auto precharge, seamless READ operations to different banks are sup- ported. After WRITE with auto precharge, seamless WRITE operations to different banks are supported. READ with auto precharge and WRITE with auto precharge must not be interrupted or truncated. REFRESH Command The REFRESH command is initiated with CS_n LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. A per-bank REFRESH command is initiated with CA3 LOW at the rising edge of the clock. The all-bank REFRESH command is initiated with CA3 HIGH at the rising edge of the clock. A per-bank REFRESH is only supported in devices with eight banks. A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to the bank scheduled by the bank counter in the memory device. The bank sequence for per-bank REFRESH is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The bank count is synchronized between the controller and the SDRAM by resetting the bank count to zero. Synchronization can occur upon issuing a RESET command or at every exit from self refresh. A bank must be idle before it can be refreshed. The controller must track the bank being refreshed by the per-bank REFRESH command. The REFpb command must not be issued to the device until the following conditions have been met: tRFCab has been satisfied after the prior REFab command

tRFCpb has been satisfied after the prior REFpb command
tRP has been satisfied after the prior PRECHARGE command to that bank Embedded LPDDR2 SDRAM REFRESH Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

tRRD has been satisfied after the prior ACTIVATE command (when applicable, for ex- ample after activating a row in a different bank than the one affected by the REFpb command) The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb); howev- er, other banks within the device are accessible and can be addressed during the cycle. During the REFpb operation, any of the banks other than the one being refreshed can be maintained in an active state or accessed by a READ or WRITE command. When the per-bank REFRESH cycle has completed, the affected bank will be in the idle state. After issuing REFpb, the following conditions must be met: tRFCpb must be satisfied before issuing a REFab command

tRFCpb must be satisfied before issuing an ACTIVATE command to the same bank
tRRD must be satisfied before issuing an ACTIVATE command to a different bank
tRFCpb must be satisfied before issuing another REFpb command An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All banks must be idle when REFab is issued (for instance, by issuing a PRECHARGE ALL command prior to issuing an all-bank REFRESH command). REFab also synchronizes the bank count between the controller and the SDRAM to zero. The REFab command must not be issued to the device until the following conditions have been met: tRFCab has been satisfied following the prior REFab command
tRFCpb has been satisfied following the prior REFpb command
tRP has been satisfied following the prior PRECHARGE commands After an all-bank REFRESH cycle has completed, all banks will be idle. After issuing RE- Fab:
tRFCab latency must be satisfied before issuing an ACTIVATE command
tRFCab latency must be satisfied before issuing a REFab or REFpb command Table 47: REFRESH Command Scheduling Separation Requirements Symbol Minimum Delay From To Notes tRFCab REFab REFab ACTIVATE command to any bank REFpb tRFCpb REFpb REFab ACTIVATE command to same bank as REFpb REFpb Embedded LPDDR2 SDRAM REFRESH Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 47: REFRESH Command Scheduling Separation Requirements (Continued) Symbol Minimum Delay From To Notes tRRD REFpb ACTIVATE command to a different bank than REFpb ACTIVATE REFpb affecting an idle bank (different bank than activate) 1 ACTIVATE command to a different bank than the prior ACTIVATE com- mand Note: 1. A bank must be in the idle state before it is refreshed, so REFab is prohibited following an ACTIVATE command. REFpb is supported only if it affects a bank that is in the idle state. REFRESH Requirements 1. Minimum Number of REFRESH Commands Mobile LPDDR2 requires a minimum number, R, of REFRESH (REFab) commands with- in any rolling refresh window (tREFW = 32 ms @ MR4[2:0] = 011 or TC ≤ 85˚C). For actual values per density and the resulting average refresh interval (tREFI), see Refresh Re- quirements. For tREFW and tREFI refresh multipliers at different MR4 settings, see the MR4 Device Temperature (MA[7:0] = 04h) table. For devices supporting per-bank REFRESH, a REFab command can be replaced by a full cycle of eight REFpb commands. 2. Burst REFRESH Limitation To limit current consumption, a maximum of eight REFab commands can be issued in any rolling tREFBW (tREFBW = 4 × 8 × tRFCab). This condition does not apply if REFpb commands are used. 3. REFRESH Requirements and Self Refresh If any time within a refresh window is spent in self refresh mode, the number of re- quired REFRESH commands in that window is reduced to the following: R´ = R - RU tSRF tREFI Where RU represents the round-up function = R - RU R × tSRF tREFW Embedded LPDDR2 SDRAM REFRESH Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 36: tSRF Definition Example A1 CKE Example B2 CKE Example C3 CKE Example D4 CKE tSRF tSRF tREFW tSRF2tSRF1 tSRF Exit self refresh modeEnter self refresh mode Exit self refresh modeEnter self refresh mode Exit self refresh modeEnter self refresh mode Exit self refresh modeEnter self refresh mode Exit self refresh mode tREFW tREFW tREFW Notes: 1. Time in self refresh mode is fully enclosed in the refresh window ( tREFW). 2. At self refresh entry. 3. At self refresh exit. 4. Several intervals in self refresh during one tREFW interval. In this example, tSRF = tSRF1 + tSRF2. The mobile LPDDR2 device provides significant flexibility in scheduling a REFRESH command as long as the required boundary conditions are met (see the tSRF Definition figure). In the most straightforward implementations, a REFRESH command should be sched- uled every tREFI. In this case, self refresh can be entered at any time. Users may choose to deviate from this regular refresh pattern, for instance, to enable a period in which no refresh is required. As an example, using a 1Gb LPDDR2 device, the user can choose to issue a refresh burst of 4096 REFRESH commands at the maximum supported rate (limited by tREFBW), followed by an extended period without issuing any REFRESH commands, until the refresh window is complete. The maximum suppor- ted time without REFRESH commands is calculated as follows: tREFW - (R/8) × tREFBW = tREFW - R × 4 × tRFCab. For example, a 1Gb device at TC ≤ 85˚C can be operated without a refresh for up to 32ms - 4096 × 4 × 130ns ≈ 30ms. Both the regular and the burst/pause patterns can satisfy refresh requirements if they are repeated in every 32ms window. It is critical to satisfy the refresh requirement in Embedded LPDDR2 SDRAM REFRESH Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

every rolling refresh window during refresh pattern transitions. The supported transi- tion from a burst pattern to a regular distributed pattern is shown in the Supported Transition from Repetitive REFRESH Burst figure. If this transition occurs immediately after the burst refresh phase, all rolling tREFW intervals will meet the minimum re- quired number of REFRESH commands. A nonsupported transition is shown below. In this example, the regular refresh pattern starts after the completion of the pause phase of the burst/pause refresh pattern. For several rolling tREFW intervals, the minimum number of REFRESH commands is not satisfied. Understanding this pattern transition is extremely important, even when only one pat- tern is employed. In self refresh mode, a regular distributed refresh pattern must be as- sumed. Micron recommends entering self refresh mode immediately following the burst phase of a burst/pause refresh pattern; upon exiting self refresh, begin with the burst phase (see the Recommended Self Refresh Entry and Exit figure). Embedded LPDDR2 SDRAM REFRESH Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 37: Regular Distributed Refresh Pattern 0ms 32ms 64ms 96ms tREFBW tREFBW tREFI tREFI 4,096 4,097 8,192 8,193 12,288 12,289 16,384 Notes: 1. Compared to repetitive burst REFRESH with subsequent REFRESH pause. 2. As an example, in a 1Gb LPDDR2 device at T C ≤ 85˚C, the distributed refresh pattern has one REFRESH command per 7.8μs; the burst refresh pattern has one REFRESH command per 0.52μs, followed by ≈ 30ms without any REFRESH command. Embedded LPDDR2 SDRAM REFRESH Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 38: Supported Transition from Repetitive REFRESH Burst 0ms 32ms 64ms 96ms tREFBW tREFBW tREFI tREFI 4,096 4,097 8,192 10,240 12,288 16,384 Notes: 1. Shown with subsequent REFRESH pause to regular distributed refresh pattern. 2. As an example, in a 1Gb LPDDR2 device at T C ≤ 85˚C, the distributed refresh pattern has one REFRESH command per 7.8μs; the burst refresh pattern has one REFRESH command per 0.52μs, followed by ≈ 30ms without any REFRESH command. Embedded LPDDR2 SDRAM REFRESH Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 39: Nonsupported Transition from Repetitive REFRESH Burst 0ms 32ms 64ms 96ms tREFBW tREFBW tREFI tREFI tREFW = 32ms2 Insufficient REFRESH commands in this refresh window! 4,096 4,097 8,192 8,193 10,240 12,288 Notes: 1. Shown with subsequent REFRESH pause to regular distributed refresh pattern. 2. There are only ≈ 2048 REFRESH commands in the indicated tREFW window. This does not provide the required minimum number of REFRESH commands (R). Embedded LPDDR2 SDRAM REFRESH Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 40: Recommended Self Refresh Entry and Exit 0ms 32ms Self refresh tREFBW tREFBW 4,096 4,097 8,192 Note: 1. In conjunction with a burst/pause refresh pattern. Embedded LPDDR2 SDRAM REFRESH Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

VREFDQ must be within their respective minimum/maximum operating ranges (see the Single-Ended AC and DC Input Levels for DQ and DM table). VREFDQ can be at any level between 0 and VDDQ; VREFCA can be at any level between 0 and VDD2 during self refresh. Before exiting self refresh, VREFDQ and VREFCA must be within specified limits (See AC and DC Logic Input Measurement Levels for Single-Ended Signals for details). After en- tering self refresh mode, the device initiates at least one all-bank REFRESH command internally during tCKESR. The clock is internally disabled during SELF REFRESH opera- tion to save power. The device must remain in self refresh mode for at least tCKESR. The user can change the external clock frequency or halt the external clock one clock after self refresh entry is registered; however, the clock must be restarted and stable before the device can exit SELF REFRESH operation. Exiting self refresh requires a series of commands. First, the clock must be stable prior to CKE returning HIGH. After the self refresh exit is registered, a minimum delay, at least equal to the self refresh exit interval ( tXSR), must be satisfied before a valid command can be issued to the device. This provides completion time for any internal refresh in progress. For proper operation, CKE must remain HIGH throughout tXSR. NOP com- mands must be registered on each rising clock edge during tXSR. Using self refresh mode introduces the possibility that an internally timed refresh event could be missed when CKE is driven HIGH for exit from self refresh mode. Upon exiting self refresh, at least one REFRESH command (one all-bank command or eight per-bank commands) must be issued before issuing a subsequent SELF REFRESH command. Figure 43: SELF REFRESH Operation Exit SR ValidNOPNOPEnter SR NOP Enter self refresh mode Input clock frequency can be changed or clock can be stopped during self refresh. Valid tCKESR (MIN) tXSR (MIN) tIHCKE tIHCKE tISCKE tISCKE Exit self refresh mode Don’t Care 2 t (MIN)CK CK_t CS_n CK_c CMD CKE Notes: 1. Input clock frequency can be changed or stopped during self refresh, provided that upon exiting self-refresh, a minimum of two cycles of stable clocks are provided, and the clock frequency is between the minimum and maximum frequencies for the particular speed grade. 2. The device must be in the all banks idle state prior to entering self refresh mode. tXSR begins at the rising edge of the clock after CKE is driven HIGH. 4. A valid command can be issued only after tXSR is satisfied. NOPs must be issued during tXSR. Embedded LPDDR2 SDRAM SELF REFRESH Operation PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Partial-Array Self Refresh – Bank Masking Any device of densities of 64Mb–512Mb is comprised of four banks; a device of 1Gb density or higher is comprised of eight banks. Each bank can be configured independ- ently whether or not a SELF REFRESH operation will occur in that bank. One 8-bit mode register (accessible via the MRW command) is assigned to program the bank- masking status of each bank up to eight banks. For bank masking bit assignments, see the MR16 PASR Bank Mask (MA[7:0] = 010h) and MR16 Op-Code Bit Definitions tables. The mask bit to the bank enables or disables a refresh operation of the entire memory space within the bank. If a bank is masked using the bank mask register, a REFRESH op- eration to the entire bank is blocked and bank data retention is not guaranteed in self refresh mode. To enable a REFRESH operation to a bank, the corresponding bank mask bit must be programmed as “unmasked.” When a bank mask bit is unmasked, the array space being refreshed within that bank is determined by the programmed status of the segment mask bits. Partial-Array Self Refresh – Segment Masking Programming segment mask bits is similar to programming bank mask bits. For a den- sity of 1Gb or higher, eight segments are used for masking (see the MR17 PASR Segment Mask (MA[7:0] = 011h) and MR17 PASR Segment Mask Definitions tables). A mode reg- ister is used for programming segment mask bits up to eight bits. For a density of less than 1Gb, segment masking is not supported. When the mask bit to an address range (represented as a segment) is programmed as “masked,” a REFRESH operation to that segment is blocked. Conversely, when a seg- ment mask bit to an address range is unmasked, refresh to that segment is enabled. A segment masking scheme can be used in place of or in combination with a bank masking scheme. Each segment mask bit setting is applied across all banks. For seg- ment masking bit assignments, see the tables noted above. Table 48: Bank and Segment Masking Example Segment Mask (MR17) Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank Mask (MR16) 0 100000 1 Segment 2 1 M M M M M M M M Segment 7 1 M M M M M M M M Note: 1. This table provides values for an 8-bank device with REFRESH operations masked to banks 1 and 7, and segments 2 and 7. Embedded LPDDR2 SDRAM SELF REFRESH Operation PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

The MODE REGISTER READ (MRR) command is used to read configuration and status data from SDRAM mode registers. The MRR command is initiated with CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode reg- ister is selected by CA1f–CA0f and CA9r–CA4r. The mode register contents are available on the first data beat of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ and following the ris- ing edge of the clock where MRR is issued. Subsequent data beats contain valid but un- defined content, except in the case of the DQ calibration function, where subsequent data beats contain valid content as described in the Data Calibration Pattern Descrip- tion table. All DQS_t,DQS_c are toggled for the duration of the mode register READ burst. The MRR command has a burst length of four. MRR operation (consisting of the MRR command and the corresponding data traffic) must not be interrupted. The MRR com- mand period ( tMRR) is two clock cycles. The MRR command issued to reserved and write-only registers should returns valid but undefined content on all data beats, and DQS_t, DQS_c should be toggled. Figure 44: MRR Timing – RL = 3, tMRR = 2 Register A Register A MRR1 NOP2 NOP2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_c CK_t CA[9:0] CMD DQS_c DQS_t DQ[7:0]3 RL = 3 MRR1 Valid tMRR = 2 tMRR = 2 DQ[MAX:8] Register B Register B DOUT BDOUT A Transitioning data Undefined Notes: 1. MRRs to DQ calibration registers MR32 and MR40 are described in the Data Calibration Pattern Description table. 2. Only the NOP command is supported during tMRR. 3. Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain valid but undefined data. DQ[MAX:8] contain valid but undefined data for the duration of the MRR burst. 4. Minimum MRR to write latency is RL + RU( tDQSCKmax/tCK) + 4/2 + 1 - WL clock cycles. 5. Minimum MRR to MRW latency is RL + RU( tDQSCKmax/tCK) + 4/2 + 1 clock cycles. READ bursts and WRITE bursts cannot be truncated by MRR. Following a READ com- mand, the MRR command must not be issued before BL/2 clock cycles have completed. Embedded LPDDR2 SDRAM MODE REGISTER READ PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Following a WRITE command, the MRR command must not be issued before WL + 1 + BL/2 + RU(tWTR/tCK) clock cycles have completed. If a READ or WRITE burst is trunca- ted with a BST command, the effective burst length of the truncated burst should be used for the BL value. Figure 45: READ to MRR Timing – RL = 3, tMRR = 2 Bank m col addr a Col addr a READ NOP2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_c CK_t CA[9:0] CMD DQS_c DQS_t DQ[7:0] DQ[MAX:8] RL = 3 Transitioning data Undefined tMRR = 2 BL/21 DOUT BDOUT A0 D OUT A1 D OUT A2 D OUT A3 DOUT A0 D OUT A1 D OUT A2 D OUT A3 Valid Register B Register B MRR Notes: 1. The minimum number of clock cycles from the burst READ command to the MRR com- mand is BL/2. 2. Only the NOP command is supported during tMRR. Embedded LPDDR2 SDRAM MODE REGISTER READ PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 46: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 Bank n col addr a Col addr a WRITE T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_c CA[9:0] CMD DQS_c DQ WL = 1 tWTR Transitioning data tMRR = 2 RL = 3 DIN A0 D IN A1 D IN A2 D IN A3 Valid Register B Register B MRR1 NOP2 CK_t DQS_t Notes: 1. The minimum number of clock cycles from the burst WRITE command to the MRR com- mand is [WL + 1 + BL/2 + RU(tWTR/tCK)]. 2. Only the NOP command is supported during tMRR. Temperature Sensor The mobile LPDDR2 device features a temperature sensor whose status can be read from MR4. This sensor can be used to determine an appropriate refresh rate, determine whether AC timing derating is required in the extended temperature range, and/or monitor the operating temperature. Either the temperature sensor or the device operat- ing temperature can be used to determine whether operating temperature require- ments are being met (see Operating Temperature Range table). Temperature sensor data can be read from MR4 using the mode register read protocol. Upon exiting self-refresh or power-down, the device temperature status bits will be no older than tTSI. When using the temperature sensor, the actual device case temperature may be higher than the operating temperature specification that applies for the standard or extended temperature ranges (see table noted above). For example, T CASE could be above 85˚C when MR4[2:0] equals 011b. To ensure proper operation using the temperature sensor, applications must accommo- date the parameters in the temperature sensor definitions table. Embedded LPDDR2 SDRAM MODE REGISTER READ PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 49: Temperature Sensor Definitions and Operating Conditions Parameter Description Symbol Min/Max Value Unit System temperature gradient Maximum temperature gradient experi- enced by the memory device at the temper- ature of interest over a range of 2˚C TempGradient MAX System-dependent ˚C/s MR4 READ interval Time period between MR4 READs from the system ReadInterval MAX System-dependent ms Temperature sensor interval Maximum delay between internal updates of MR4 tTSI MAX 32 ms System response delay Maximum response time from an MR4 READ to the system response SysRespDelay MAX System-dependent ms Device temperature margin Margin above maximum temperature to support controller response TempMargin MAX 2 ˚C The mobile LPDDR2 device accommodates the temperature margin between the point at which the device temperature enters the extended temperature range and the point at which the controller reconfigures the system accordingly. To determine the required MR4 polling frequency, the system must use the maximum TempGradient and the max- imum response time of the system according to the following equation: TempGradient × (ReadInterval + tTSI + SysResp Delay) ≤ 2°C For example, if TempGradient is 10˚C/s and the SysRespDelay is 1ms: 10°C s × (ReadInterval + 32ms + 1ms) ≤ 2°C In this case, ReadInterval must not exceed 167ms. Embedded LPDDR2 SDRAM MODE REGISTER READ PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 47: Temperature Sensor Timing Host MR4 READ Device Temp Margin MR4 Trip Level 2°C MR4 = 0x03 MRR MR4 = 0x03 MRR MR4 = 0x86 tTSI < (tTSI + ReadInterval + SysRespDelay) ReadInterval SysRespDelay MR4 = 0x86 MR4 = 0x86 MR4 = 0x86 MR4 = 0x06 Time Temp TempGradient Temperture sensor update DQ Calibration The mobile LPDDR2 device features a DQ calibration function that outputs one of two predefined system timing calibration patterns. For a x16 device, pattern A (MRR to MRR32), and pattern B (MRR to MRR40), will return the specified pattern on DQ0 and DQ8; a x32 device returns the specified pattern on DQ0, DQ8, DQ16, and DQ24. For a x16 device, DQ[7:1] and DQ[15:9] drive the same information as DQ0 during the MRR burst. For a x32 device, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] drive the same information as DQ0 during the MRR burst. MRR DQ calibration commands can occur only in the idle state. Embedded LPDDR2 SDRAM MODE REGISTER READ PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 48: MR32 and MR40 DQ Calibration Timing – RL = 3, tMRR = 2 MRR NOP1 NOP T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_c CK_t CA[9:0] CMD DQS_c DQS_t DQ0 DQ[7:1] DQ8 DQ[15:9] DQ16 DQ[23:17] DQ24 DQ[31:25] RL = 3 Transitioning data Optionally driven the same as DQ0 or 0b tMRR = 2tMRR = 2 00111010 Reg 40Reg 40Reg 32Reg 32 MRR 00111010 00111010 00111010 00111010 00111010 00111010 00111010 Pattern A Pattern B x32 x16 Notes: 1. The MRR command has a burst length of four. 2. The MRR operation must not be interrupted. 3. A MRR to MR32 and MR40 drives valid data on DQ[0] during the entire burst. For a x16 device, DQ[8] drives the same information as DQ[0] during the burst. For a x32 device, DQ[8], DQ[16], and DQ[24] drive the same information as DQ[0] during the burst. 4. For a x16 device, DQ[7:1] and DQ[15:9] may optionally drive the same information as DQ[0], or they may drive 0b during the burst. For a x32 device, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] may optionally drive the same information as DQ[0], or they may drive 0b during the burst. 5. The MODE REGISTER command period is tMRR. No command (other than NOP) is al- lowed during this period. Embedded LPDDR2 SDRAM MODE REGISTER READ PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 50: Data Calibration Pattern Description Pattern MR# Bit Time Bit Time Bit Time Bit Time

3 Description

Pattern A MR32 1 0 1 0 Reads to MR32 return DQ calibration pattern A Pattern B MR40 0 0 1 1 Reads to MR40 return DQ calibration pattern B MODE REGISTER WRITE Command The MODE REGISTER WRITE (MRW) command is used to write configuration data to the mode registers. The MRW command is initiated with CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3 LOW at the rising edge of the clock. The mode register is selec- ted by CA1f–CA0f, CA9r–CA4r. The data to be written to the mode register is contained in CA9f–CA2f. The MRW command period is defined by tMRW . A MRW command to read-only registers has no impact on the functionality of the device. MRW can be issued only when all banks are in the idle precharge state. One method of ensuring that the banks are in this state is to issue a PRECHARGE ALL command. Figure 49: MODE REGISTER WRITE Timing – RL = 3, tMRW = 5 05GDWD05DGGU 05: 123 05: &.BF &.BW &$> &0' 9DOLG W05: W05: 05GDWD05DGGU 123 123 123 Notes: 1. At time Ty, the device is in the idle state. 2. Only the NOP command is supported during tMRW. Table 51: Truth Table for MRR and MRW Current State Command Intermediate State Next State All banks idle MRR Reading mode register, all banks idle All banks idle MRW Writing mode register, all banks idle All banks idle MRW (RESET) Resetting, device auto initialization All banks idle Bank(s) active MRR Reading mode register, bank(s) active Bank(s) active MRW Not allowed Not allowed MRW (RESET) Not allowed Not allowed MRW RESET Command The MRW RESET command brings the device to the device auto initialization (reset- ting) state in the power-on initialization sequence (see step 2. of the RESET Command Embedded LPDDR2 SDRAM MODE REGISTER WRITE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

under Voltage Ramp and Initialization Sequence). The MRW RESET command can be issued from the idle state. This command resets all mode registers to their default val- ues. Only the NOP command is supported during tINIT4. After MRW RESET , boot tim- ings must be observed until the device initialization sequence is complete and the de- vice is in the idle state. Array data is undefined after the MRW RESET command has completed. For MRW RESET timing, see Voltage Ramp and Initialization Sequence. MRW ZQ Calibration Commands The MRW command is used to initiate a ZQ calibration command that calibrates output driver impedance across process, temperature, and voltage. LPDDR2-S4 devices sup- port ZQ calibration. To achieve tighter tolerances, proper ZQ calibration must be per- formed. There are four ZQ calibration commands and related timings: tZQINIT , tZQRESET , tZQCL, and tZQCS. tZQINIT is used for initialization calibration; tZQRESET is used for resetting ZQ to the default output impedance; tZQCL is used for long calibration(s); and tZQCS is used for short calibration(s). See the MR10 Calibration (MA[7:0] = 0Ah) table for ZQ calibration command code definitions. ZQINIT must be performed for LPDDR2 devices. ZQINIT provides an output impe- dance accuracy of ±15%. After initialization, the ZQ calibration long (ZQCL) can be used to recalibrate the system to an output impedance accuracy of ±15%. A ZQ calibration short (ZQCS) can be used periodically to compensate for temperature and voltage drift in the system. ZQRESET resets the output impedance calibration to a default accuracy of ±30% across process, voltage, and temperature. This command is used to ensure output impedance accuracy to ±30% when ZQCS and ZQCL commands are not used. One ZQCS command can effectively correct at least 1.5% (ZQ correction) of output im- pedance errors within tZQCS for all speed bins if maximum sensitivities are met as specified in Output Driver Sensitivity Definition and Output Driver Temperature and Voltage Sensitivity. The appropriate interval between ZQCS commands can be deter- mined using these tables and system-specific parameters. Mobile LPDDR2 devices are subject to temperature drift rate (T driftrate) and voltage drift rate (Vdriftrate) in various applications. To accommodate drift rates and calculate the necessary interval between ZQCS commands, apply the following formula: ZQcorrection (Tsens × Tdriftrate ) + (Vsens × Vdriftrate ) Where Tsens = MAX (dRONdT) and Vsens = MAX (dRONdV) define temperature and volt- age sensitivities. For example, if T sens = 0.75%/˚C, Vsens = 0.20%/mV , Tdriftrate = 1˚C/sec, and Vdriftrate = 15 mV/sec, then the interval between ZQCS commands is calculated as: 1.5 = 0.4s A ZQ calibration command can only be issued when the device is in the idle state with all banks precharged. No other activities can be performed on the data bus during calibration periods Embedded LPDDR2 SDRAM MODE REGISTER WRITE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

(tZQINIT , tZQCL, or tZQCS). The quiet time on the data bus helps to calibrate output im- pedance accurately. There is no required quiet time after the ZQRESET command. If multiple devices share a single ZQ resistor, only one device can be calibrating at any giv- en time. After calibration is complete, the ZQ ball circuitry is disabled to reduce power consumption. In systems sharing a ZQ resistor between devices, the controller must prevent tZQINIT , tZQCS, and tZQCL overlap between the devices. ZQRESET overlap is acceptable. If the ZQ resistor is absent from the system, ZQ must be connected to VDD2. In this situation, the device must ignore ZQ calibration commands and the device will use the default calibration settings. Figure 50: ZQ Timings 05GDWD05DGGU 05: 123 7 7 7 7 7 7 7[ 7[ 7[ &.BF &.BW &$> &0' 9DOLG W=4,1,7 123 123 123 123 05:&0' 9DOLG W=4&6 05:&0' 9DOLG W=4&/ 05:&0' 9DOLG W=45(6(7 =4,1,7 =4&6 =4&/ =45(6(7 123 123 123 123 123 123 123 123 123 123 123 123 123 123 123 Notes: 1. Only the NOP command is supported during ZQ calibrations tZQINIT: ZQ calibration initialization period tZQCS: ZQ calibration short period t ZQCL: ZQ calibration long period tZQRESET: ZQ calibration reset period Embedded LPDDR2 SDRAM MODE REGISTER WRITE Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

CKE must be registered HIGH continuously during the calibration period. 3. All devices connected to the DQ bus should be High-Z during the calibration process. ZQ External Resistor Value, Tolerance, and Capacitive Loading To use the ZQ calibration function, a 240 ohm (±1% tolerance) external resistor must be connected between the ZQ pin and ground. A single resistor can be used for each device or one resistor can be shared between multiple devices if the ZQ calibration timings for each device do not overlap. The total capacitive loading on the ZQ pin must be limited (see the Input/Output Capacitance table). Power-Down Power-down is entered synchronously when CKE is registered LOW and CS_n is HIGH at the rising edge of clock. A NOP command must be driven in the clock cycle following power-down entry. CKE must not go LOW while MRR, MRW, READ, or WRITE opera- tions are in progress. CKE can go LOW while any other operation such as ACTIVATE, PRECHARGE, auto precharge, or REFRESH are in progress, but the power-down I DD specification will not be applied until such operations are complete. If power-down occurs when all banks are idle, this mode is referred to as idle power- down; if power-down occurs when there is a row active in any bank, this mode is refer- red to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK_t, CK_c, and CKE. In power-down mode, CKE must be held LOW; all other input signals are “Don’t Care.” CKE LOW must be maintained until tCKE is satisfied. VREFCA must be maintained at a valid level during power-down. VDDQ can be turned off during power-down. If VDDQ is turned off, VREFDQ must also be turned off. Prior to exiting power-down, both VDDQ and VREFDQ must be within their re- spective minimum/maximum operating ranges (see AC and DC Operating Conditions). No refresh operations are performed in power-down mode. The maximum duration in power-down mode is limited only by the refresh requirements outlined in REFRESH Command. The power-down state is exited when CKE is registered HIGH. The controller must drive CS_n HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE HIGH must be maintained until tCKE is satisfied. A valid, executable command can be applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit laten- cy is defined in the AC Timing section. Embedded LPDDR2 SDRAM Power-Down PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 54: READ to Power-Down Entry CK_c CKE1, 2 T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9 CMD DQ DQS_c READ DOUT DOUT DOUT DOUT RL tISCKE CKE1, 2 T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9 CMD DQ READ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT RL tISCKE BL = 4 BL = 8 CK_t CK_c CK_t DQS_t DQS_c DQS_t Notes: 1. CKE must be held HIGH until the end of the burst operation. 2. CKE can be registered LOW at (RL + RU( tDQSCK(MAX)/tCK) + BL/2 + 1) clock cycles after the clock on which the READ command is registered. Embedded LPDDR2 SDRAM Power-Down PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 80 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 55: READ with Auto Precharge to Power-Down Entry CK_c CKE1, 2 T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9 CMD DQ DQS_c READ w/AP PRE4 DOUT DOUT DOUT DOUT RL tISCKE BL/23 READ w/AP PRE4 BL/23 CKE1, 2 T0 T1 T2 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 Tx + 7 Tx + 8 Tx + 9 CMD DQ DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT RL tISCKE BL = 4 BL = 8 CK_t DQS_t CK_c DQS_c CK_t DQS_t Notes: 1. CKE must be held HIGH until the end of the burst operation. 2. CKE can be registered LOW at (RL + RU( tDQSCK/tCK)+ BL/2 + 1) clock cycles after the clock on which the READ command is registered. 3. BL/2 with tRTP = 7.5ns and tRAS (MIN) is satisfied. 4. Start internal PRECHARGE. Embedded LPDDR2 SDRAM Power-Down PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 56: WRITE to Power-Down Entry CK_c CKE1 T0 T1 Tm Tm + 1 Tm + 2 Tm + 3 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 CMD DQ DQS_c WRITE DIN DIN DIN DIN WL tWR tWR CK_t CKE1 T0 T1 Tm Tm +m1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 CMD DQ DQS_t WRITE DIN DIN DIN DIN DIN DIN DIN DIN WL tISCKE BL/2 BL/2 tISCKE BL = 4 BL = 8 CK_c DQS_c CK_t DQS_t Note: 1. CKE can be registered LOW at (WL + 1 + BL/2 + RU( tWR/tCK)) clock cycles after the clock on which the WRITE command is registered. Embedded LPDDR2 SDRAM Power-Down PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 57: WRITE with Auto Precharge to Power-Down Entry CK_c CKE1 T0 T1 Tm Tm + 1 Tm + 2 Tm + 3 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 Tx + 5 Tx + 6 CMD DQ DQS_c WRITE w/AP PRE2 DIN DIN DIN DIN WL BL/2 BL/2 CK_t CKE1 T0 T1 Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tx Tx + 1 Tx + 2 Tx + 3 Tx + 4 CMD DQ DQS_t DIN DIN DIN DIN DIN DIN DIN DIN WL tISCKE tWR tWR PRE2 BL = 4 BL = 8 WRITE w/AP CK_c DQS_c CK_t DQS_t tISCKE Notes: 1. CKE can be registered LOW at (WL + 1 + BL/2 + RU( tWR/tCK + 1) clock cycles after the WRITE command is registered. 2. Start internal PRECHARGE. Embedded LPDDR2 SDRAM Power-Down PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 83 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

To exit DPD, CKE must be HIGH, tISCKE must be complete, and the clock must be sta- ble. To resume operation, the device must be fully reinitialized using the power-up initi- alization sequence. Figure 63: Deep Power-Down Entry and Exit Timing RESETNOPEnter DPD NOP Enter DPD mode Input clock frequency can be changed or the input clock can be stopped during DPD. NOP CK_c CKE CS_n CMD tDPD tINIT31, 2tIHCKE tISCKE tRP tISCKE Exit DPD mode Don’t Care 2 tCK (MIN) Exit DPD CK_t Notes: 1. The initialization sequence can start at any time after Tx + 1. 2. tINIT3 and Tx + 1 refer to timings in the initialization sequence. For details, see Mode Register Definition. Input Clock Frequency Changes and Stop Events Input Clock Frequency Changes and Clock Stop with CKE LOW During CKE LOW, the mobile LPDDR2 device supports input clock frequency changes and clock stop under the following conditions:

Refresh requirements are met
Only REFab or REFpb commands can be in process
Any ACTIVATE or PRECHARGE commands have completed prior to changing the fre- quency
Related timing conditions, tRCD and tRP , have been met prior to changing the fre- quency
The initial clock frequency must be maintained for a minimum of two clock cycles af- ter CKE goes LOW
The clock satisfies tCH(abs) and tCL(abs) for a minimum of two clock cycles prior to CKE going HIGH For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock cycle. After the input clock frequency is changed and CKE is held HIGH, additional MRW commands may be required to set the WR, RL, etc. These settings may require adjust- ment to meet minimum timing requirements at the target clock frequency. For clock stop, CK_t is held LOW and CK_c is held HIGH. Embedded LPDDR2 SDRAM Input Clock Frequency Changes and Stop Events PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Input Clock Frequency Changes and Clock Stop with CKE HIGH During CKE HIGH, the LPDDR2 device supports input clock frequency changes and clock stop under the following conditions:

REFRESH requirements are met
Any ACTIVATE, READ, WRITE, PRECHARGE, MRW, or MRR commands must have completed, including any associated data bursts, prior to changing the frequency
Related timing conditions, tRCD, tWR, tRP , tMRW, and tMRR, etc., are met
CS_n must be held HIGH
Only REFab or REFpb commands can be in process The device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs) for a minimum of 2 × tCK + tXP . For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock cycle. After the input clock frequency is changed, additional MRW commands may be re- quired to set the WR, RL, etc. These settings may require adjustment to meet minimum timing requirements at the target clock frequency. For clock stop, CK_t is held LOW and CK_c is held HIGH. NO OPERATION Command The NO OPERATION (NOP) command prevents the device from registering any unwan- ted commands issued between operations. A NOP command can be issued only at clock cycle N when the CKE level is constant for clock cycle N-1 and clock cycle N. The NOP command has two possible encodings: CS_n HIGH at the clock rising edge N; and CS_n LOW with CA0, CA1, CA2 HIGH at the clock rising edge N. The NOP command will not terminate a previous operation that is still in process, such as a READ burst or WRITE burst cycle. Truth Tables Truth tables provide complementary information to the state diagram. They also clarify device behavior and applicable restrictions when considering the actual state of the banks. Unspecified operations and timings are illegal. To ensure proper operation after an ille- gal event, the device must be powered down and then restarted using the specified initi- alization sequence before normal operation can continue. Table 52: Command Truth Table Notes 1–13 apply to all parameters conditions Command Command Pins CA Pins CK Edge CKE CS_n CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9CK(n-1) CK(n) MRW H H L L L L L MA0 MA1 MA2 MA3 MA4 MA5 H H X MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 Embedded LPDDR2 SDRAM NO OPERATION Command PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 52: Command Truth Table (Continued) Notes 1–13 apply to all parameters conditions Command Command Pins CA Pins CK Edge CKE CS_n CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9CK(n-1) CK(n) MRR H H L L L L H MA0 MA1 MA2 MA3 MA4 MA5 H H X MA6 MA7 X REFRESH (per bank) HH L L L H L X HH X X REFRESH (all banks) HH L L L H H X HH X X Enter self refresh HL L L L H X XL X X ACTIVATE (bank) H H L L H R8 R9 R10 R11 R12 BA0 BA1 BA2 H H X R0 R1 R2 R3 R4 R5 R6 R7 R13 R14 WRITE (bank) H H L H L L RFU RFU C1 C2 BA0 BA1 BA2 H H X AP C3 C4 C5 C6 C7 C8 C9 C10 C11 READ (bank) H H L H L H RFU RFU C1 C2 BA0 BA1 BA2 H H X AP C3 C4 C5 C6 C7 C8 C9 C10 C11 PRECHARGE (bank) HH L H H L H A B X X BA0 BA1 BA2 HH X X BST H H L H H L L X HH X X Enter DPD H L L H H L X XL X X NOP H H L H H H X HH X X Maintain PD, SREF, DPD, (NOP) LL L H H H X LL X X NOP H H H X HH X X Maintain PD, SREF, DPD, (NOP) LL H X LL X X Enter power- down HL H X XL X X Embedded LPDDR2 SDRAM Truth Tables PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 52: Command Truth Table (Continued) Notes 1–13 apply to all parameters conditions Command Command Pins CA Pins CK Edge CKE CS_n CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9CK(n-1) CK(n) Exit PD, SREF, DPD LH H X XH X X Notes: 1. All commands are defined by the current state of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock. 2. Bank addresses (BA) determine which bank will be operated upon. 3. AP HIGH during a READ or WRITE command indicates that an auto precharge will occur to the bank associated with the READ or WRITE command. 4. X indicates a “Don’t Care” state, with a defined logic level, either HIGH (H) or LOW (L). 5. Self refresh exit and DPD exit are asynchronous. 6. V REF must be between 0 and VDDQ during self refresh and DPD operation. 7. CAxr refers to command/address bit “x” on the rising edge of clock. 8. CAxf refers to command/address bit “x” on the falling edge of clock. 9. CS_n and CKE are sampled on the rising edge of the clock. 10. Per-bank refresh is supported only in devices with eight banks. 11. The least-significant column address C0 is not transmitted on the CA bus, and is inferred to be zero. 12. RFU needs to input “H” or “L“ (but a defined logic level). 13. AB “high”during Precharge command indicates that all bank Precharge will occur. In this case, Bank Address is don’t care. Table 53: CKE Truth Table Notes 1–5 apply to all parameters and conditions; L = LOW, H = HIGH, X = “Don’t Care” Current State CKEn-1 CKEn CS_n Command n Operation n Next State Notes Active power-down L L X X Maintain active power-down Active power-down L H H NOP Exit active power-down Active 6, 7 Idle power- down L L X X Maintain idle power-down Idle power-down L H H NOP Exit idle power-down Idle 6, 7 Resetting idle power-down L L X X Maintain resetting power-down Resetting power-down L H H NOP Exit resetting power-down Idle or resetting 6, 7, 8 Deep power- down L L X X Maintain deep power-down Deep power-down L H H NOP Exit deep power-down Power-on 9 Self refresh L L X X Maintain self refresh Self refresh L H H NOP Exit self refresh Idle 10, 11 Bank(s) active H L H NOP Enter active power-down Active power-down Embedded LPDDR2 SDRAM Truth Tables PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 53: CKE Truth Table (Continued) Notes 1–5 apply to all parameters and conditions; L = LOW, H = HIGH, X = “Don’t Care” Current State CKEn-1 CKEn CS_n Command n Operation n Next State Notes All banks idle H L H NOP Enter idle power-down Idle power-down H L L Enter self re- fresh Enter self refresh Self refresh H L L DPD Enter deep power-down Deep power-down Resetting H L H NOP Enter resetting power-down Resetting power-down Other states H H Refer to the command truth table Notes: 1. Current state = the state of the device immediately prior to the clock rising edge n. 2. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 3. CKEn = the logic state of CKE at clock rising edge n; CKEn-1 was the state of CKE at the previous clock edge. 4. CS_n= the logic state of CS_n at the clock rising edge n. 5. Command n = the command registered at clock edge n, and operation n is a result of command n. 6. Power-down exit time ( tXP) must elapse before any command other than NOP is issued. 7. The clock must toggle at least twice prior to the tXP period. 8. Upon exiting the resetting power-down state, the device will return to the idle state if tINIT5 has expired. 9. The DPD exit procedure must be followed as described in Deep Power Down. 10. Self refresh exit time ( tXSR) must elapse before any command other than NOP is issued. 11. The clock must toggle at least twice prior to the tXSR time. Table 54: Current State Bank n to Command to Bank n Truth Table Notes 1–5 apply to all parameters and conditions Current State Command Operation Next State Notes Any NOP Continue previous operation Current state Idle ACTIVATE Select and activate row Active Refresh (per bank) Begin to refresh Refreshing (per bank) 6 Refresh (all banks) Begin to refresh Refreshing (all banks) 7 MRW Load value to mode register MR writing 7 MRR Read value from mode register Idle, MR reading RESET Begin device auto initialization Resetting 7, 8 PRECHARGE Deactivate row(s) in bank or banks Precharging 9, 10 Row active READ Select column and start read burst Reading WRITE Select column and start write burst Writing MRR Read value from mode register Active MR reading PRECHARGE Deactivate row(s) in bank or banks Precharging 9 Embedded LPDDR2 SDRAM Truth Tables PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 54: Current State Bank n to Command to Bank n Truth Table (Continued) Notes 1–5 apply to all parameters and conditions Current State Command Operation Next State Notes Reading READ Select column and start new read burst Reading 11, 12 WRITE Select column and start write burst Writing 11, 12, 13 BST Read burst terminate Active 14 Writing WRITE Select column and start new write burst Writing 11, 12 READ Select column and start read burst Reading 11, 12, 15 BST Write burst terminate Active 14 Power-on RESET Begin device auto initialization Resetting 7, 9 Resetting MRR Read value from mode register Resetting MR reading Notes: 1. Values in this table apply when both CKEn -1 and CKEn are HIGH, and after tXSR or tXP has been met, if the previous state was power-down. 2. All states and sequences not shown are illegal or reserved. 3. Current state definitions: Idle: The bank or banks have been precharged, and tRP has been met. Active: A row in the bank has been activated, and tRCD has been met. No data bursts or accesses and no register accesses are in progress. Reading: A READ burst has been initiated with auto precharge disabled and has not yet terminated or been terminated. Writing: A WRITE burst has been initiated with auto precharge disabled and has not yet terminated or been terminated. 4. These states must not be interrupted by a command issued to the same bank. NOP com- mands or supported commands to the other bank must be issued on any clock edge oc- curring during these states. Supported commands to the other banks are determined by that bank’s current state and the definitions given here. Precharge: Starts with registration of a PRECHARGE command and ends when tRP is met. After tRP is met, the bank is in the idle state. Row activate: Starts with registration of an ACTIVATE command and ends when tRCD is met. After tRCD is met, the bank is in the active state. READ with AP enabled: Starts with registration of a READ command with auto pre- charge enabled and ends when tRP is met. After tRP is met, the bank is in the idle state. WRITE with AP enabled: Starts with registration of a WRITE command with auto pre- charge enabled and ends when tRP is met. After tRP is met, the bank is in the idle state. 5. These states must not be interrupted by any executable command. NOP commands must be applied to each rising clock edge during these states. Refresh (per bank): Starts with registration of a REFRESH (per bank) command and ends when tRFCpb is met. After tRFCpb is met, the bank is in the idle state. Refresh (all banks): Starts with registration of a REFRESH (all banks) command and ends when tRFCab is met. After tRFCab is met, the device is in the all banks idle state. Idle MR reading: Starts with registration of the MRR command and ends when tMRR is met. After tMRR is met, the device is in the all banks idle state. Embedded LPDDR2 SDRAM Truth Tables PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Resetting MR reading: Starts with registration of the MRR command and ends when tMRR is met. After tMRR is met, the device is in the all banks idle state. Active MR reading: Starts with registration of the MRR command and ends when tMRR is met. After tMRR is met, the bank is in the active state. MR writing: Starts with registration of the MRW command and ends when tMRW is met. After tMRW is met, the device is in the all banks idle state. Precharging all: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. After tRP is met, the device is in the all banks idle state. 6. Bank-specific; requires that the bank is idle and no bursts are in progress. 7. Not bank-specific; requires that all banks are idle and no bursts are in progress. 8. Not bank-specific. 9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 10. If a PRECHARGE command is issued to a bank in the idle state, tRP still applies. 11. A command other than NOP should not be issued to the same bank while a burst READ or burst WRITE with auto precharge is enabled. 12. The new READ or WRITE command could be auto precharge enabled or auto precharge disabled. 13. A WRITE command can be issued after the completion of the READ burst; otherwise, a BST must be issued to end the READ prior to asserting a WRITE command. 14. Not bank-specific. The BST command affects the most recent READ/WRITE burst started by the most recent READ/WRITE command, regardless of bank. 15. A READ command can be issued after completion of the WRITE burst; otherwise, a BST must be used to end the WRITE prior to asserting another READ command. Table 55: Current State Bank n to Command to Bank m Truth Table Notes 1–6 apply to all parameters and conditions Current State of Bank n Command to Bank m Operation Next State for Bank m Notes Any NOP Continue previous operation Current state of bank m Idle Any Any command supported to bank m –7 Row activating, active, or pre- charging ACTIVATE Select and activate row in bank m Active 8 READ Select column and start READ burst from bank m Reading 9 WRITE Select column and start WRITE burst to bank m Writing 9 PRECHARGE Deactivate row(s) in bank or banks Precharging 10 MRR READ value from mode register Idle MR reading or active MR reading 11, 12, 13 BST READ or WRITE burst terminates an on- going READ/WRITE from/to bank m Active 7 Embedded LPDDR2 SDRAM Truth Tables PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 55: Current State Bank n to Command to Bank m Truth Table (Continued) Notes 1–6 apply to all parameters and conditions Current State of Bank n Command to Bank m Operation Next State for Bank m Notes Reading (auto precharge disabled) READ Select column and start READ burst from bank m Reading 9 WRITE Select column and start WRITE burst to bank m Writing 9, 14 ACTIVATE Select and activate row in bank m Active PRECHARGE Deactivate row(s) in bank or banks Precharging 10 Writing (auto precharge disabled) READ Select column and start READ burst from bank m Reading 9, 15 WRITE Select column and start WRITE burst to bank m Writing 9 ACTIVATE Select and activate row in bank m Active PRECHARGE Deactivate row(s) in bank or banks Precharging 10 Reading with auto precharge READ Select column and start READ burst from bank m Reading 9, 16 WRITE Select column and start WRITE burst to bank m Writing 9, 14, 16 ACTIVATE Select and activate row in bank m Active PRECHARGE Deactivate row(s) in bank or banks Precharging 10 Writing with auto precharge READ Select column and start READ burst from bank m Reading 9, 15, 16 WRITE Select column and start WRITE burst to bank m Writing 9, 16 ACTIVATE Select and activate row in bank m Active PRECHARGE Deactivate row(s) in bank or banks Precharging 10 Power-on RESET Begin device auto initialization Resetting 17, 18 Resetting MRR Read value from mode register Resetting MR reading Notes: 1. This table applies when: the previous state was self refresh or power-down; after tXSR or tXP has been met; and both CKEn -1 and CKEn are HIGH. 2. All states and sequences not shown are illegal or reserved. 3. Current state definitions: Idle: The bank has been precharged and tRP has been met. Active: A row in the bank has been activated, tRCD has been met, no data bursts or ac- cesses and no register accesses are in progress. Read: A READ burst has been initiated with auto precharge disabled and the READ has not yet terminated or been terminated. Write: A WRITE burst has been initiated with auto precharge disabled and the WRITE has not yet terminated or been terminated. 4. Refresh, self refresh, and MRW commands can be issued only when all banks are idle. Embedded LPDDR2 SDRAM Truth Tables PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

A BST command cannot be issued to another bank; it applies only to the bank represen- ted by the current state. 6. These states must not be interrupted by any executable command. NOP commands must be applied during each clock cycle while in these states: Idle MRR: Starts with registration of the MRR command and ends when tMRR has been met. After tMRR is met, the device is in the all banks idle state. Reset MRR: Starts with registration of the MRR command and ends when tMRR has been met. After tMRR is met, the device is in the all banks idle state. Active MRR: Starts with registration of the MRR command and ends when tMRR has been met. After tMRR is met, the bank is in the active state. MRW: Starts with registration of the MRW command and ends when tMRW has been met. After tMRW is met, the device is in the all banks idle state. 7. BST is supported only if a READ or WRITE burst is ongoing. 8. tRRD must be met between the ACTIVATE command to bank n and any subsequent ACTIVATE command to bank m. 9. READs or WRITEs listed in the command column include READs and WRITEs with or without auto precharge enabled. 10. This command may or may not be bank-specific. If all banks are being precharged, they must be in a valid state for precharging. 11. MRR is supported in the row-activating state. 12. MRR is supported in the precharging state. 13. The next state for bank m depends on the current state of bank m (idle, row-activating, precharging, or active). 14. A WRITE command can be issued after the completion of the READ burst; otherwise a BST must be issued to end the READ prior to asserting a WRITE command. 15. A READ command can be issued after the completion of the WRITE burst; otherwise, a BST must be issued to end the WRITE prior to asserting another READ command. 16. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be followed by any valid command to other banks provided that the timing restrictions in the PRECHARGE and Auto Precharge Clarification table are met. 17. Not bank-specific; requires that all banks are idle and no bursts are in progress. 18. RESET command is achieved through MODE REGISTER WRITE command. Table 56: DM Truth Table Functional Name DM DQ Notes Write enable L Valid 1 Write inhibit H X 1 Note: 1. Used to mask write data, and is provided simultaneously with the corresponding input data. Embedded LPDDR2 SDRAM Truth Tables PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Stresses greater than those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 57: Absolute Maximum DC Ratings Parameter Symbol Min Max Unit Notes VDD1 supply voltage relative to VSS VDD1 –0.4 +2.3 V 1 VDD2 supply voltage relative to VSS VDD2 (1.2V) –0.4 +1.6 V 1 VDDQ supply voltage relative to VSSQ VDDQ –0.4 +1.6 V 1, 3 Voltage on any ball relative to VSS VIN, VOUT –0.4 +1.6 V Storage temperature TSTG –55 +125 ˚C 4 Notes: 1. See 1. Voltage Ramp under Power Up. 2. V REFCA 0.6 ≤ VDD2; however, VREFCA may be ≥ VDD2 provided that VREFCA ≤ 300mV. 3. V REFDQ 0.6 ≤ VDDQ; however, VREFDQ may be ≥ VDDQ provided that VREFDQ ≤ 300mV. 4. Storage temperature is the case surface temperature on the center/top side of the de- vice. For measurement conditions, refer to the JESD51-2 standard. Embedded LPDDR2 SDRAM Absolute Maximum Ratings PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 58: Input/Output Capacitance Note 1 applies to all parameters and conditions Parameter Symbol MIN MAX Unit Notes Input capacitance, CK and CK# C L1 1.0 3.0 pF 2 Input capacitance, all other LPDDR2 input only balls C L2 1.0 3.0 pF 2 Input/output capacitance, DQ, DM, DQS, DQS# CI/O 2.0 3.5 pF 2, 3 Input/output capacitance, ZQ C ZQ 2.0 3.0 pF 2, 3 Notes: 1. This parameter is not subject to production testing. It is verified by design and character- ization. The capacitance is measured according to JEP147 (procedure for measuring in- put capacitance using a vector network analyzer), with VDD1, VDD2, VDDQ, VSS, and VSSQ applied; all other pins are left floating. 2. These parameters are measured on f = 100 MHz, V OUT = VDDQ2, TA = 25°C. 3. D OUT circuits are disabled. Embedded LPDDR2 SDRAM Input/Output Capacitance PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Electrical Specifications – IDD Specifications and Conditions The following definitions and conditions are used in the IDD measurement tables unless stated otherwise:

LOW: V IN ≤ VIL(DC)max
HIGH: V IN ≥ VIH(DC)min
STABLE: Inputs are stable at a HIGH or LOW level
SWITCHING: See the following three tables Table 59: Switching for CA Input Signals Notes 1–3 apply to all parameters and conditions CK_t Rising/ CK_c Fall- ing CK_t Fall- ing/ CK_c Rising CK_t Rising/ CK_c Fall- ing CK_t Fall- ing/ CK_c Rising CK_t Rising/ CK_c Fall- ing CK_t Fall- ing/ CK_c Rising CK_t Rising/ CK_c Fall- ing CK_t Fall- ing/ CK_c Rising Cycle N N + 1 N + 2 N + 3 CS_n HIGH HIGH HIGH HIGH CA0 H L L L L H H H CA1 H H H L L L L H CA2 H L L L L H H H CA3 H H H L L L L H CA4 H L L L L H H H CA5 H H H L L L L H CA6 H L L L L H H H CA7 H H H L L L L H CA8 H L L L L H H H CA9 H H H L L L L H Notes: 1. CS# must always be driven HIGH. 2. For each clock cycle, 50% of the CA bus is changing between HIGH and LOW. 3. The noted pattern (N, N + 1, N + 2, N + 3...) is used continuously during I DD measure- ment for IDD values that require switching on the CA bus. Table 60: Switching for IDD4R Clock CKE CS_n Clock Cycle Number Command CA[2:0] CA[9:3] All DQ Rising H L N Read_Rising HLH LHLHLHL L Falling H L N Read_Falling LLL LLLLLLL L Rising H H N +1 NOP LLL LLLLLLL H Falling H H N + 1 NOP HLH HLHLLHL L Rising H L N + 2 Read_Rising HLH HLHLLHL H Falling H L N + 2 Read_Falling LLL HHHHHHH H Rising H H N + 3 NOP LLL HHHHHHH H Embedded LPDDR2 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 60: Switching for IDD4R (Continued) Clock CKE CS_n Clock Cycle Number Command CA[2:0] CA[9:3] All DQ Falling H H N + 3 NOP HLH LHLHLHL L Notes: 1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle. Table 61: Switching for IDD4W Clock CKE CS_n Clock Cycle Number Command CA[2:0] CA[9:3] All DQ Rising H L N Write_Rising HLL LHLHLHL L Falling H L N Write_Falling LLL LLLLLLL L Rising H H N +1 NOP LLL LLLLLLL H Falling H H N + 1 NOP HLH HLHLLHL L Rising H L N + 2 Write_Rising HLL HLHLLHL H Falling H L N + 2 Write_Falling LLL HHHHHHH H Rising H H N + 3 NOP LLL HHHHHHH H Falling H H N + 3 NOP HLH LHLHLHL L Notes: 1. Data strobe (DQS) is changing between HIGH and LOW with every clock cycle. 2. Data masking (DM) must always be driven LOW. 3. The noted pattern (N, N + 1...) is used continuously during I DD measurement for IDD4W. Table 62: IDD Specification Parameters and Operating Conditions Notes 1–3 apply to all parameters and conditions Parameter/Condition Symbol Power Supply Notes Operating one bank active-precharge current (SDRAM): tCK = tCKmin; tRC = tRCmin; CKE is HIGH; CS_n is HIGH between valid commands; CA bus in- puts are switching; Data bus inputs are stable IDD01 VDD1 IDD02 VDD2 IDD0in VDDQ 4 Idle power-down standby current: tCK = tCKmin; CKE is LOW; CS_n is HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are sta- ble IDD2P1 VDD1 IDD2P2 VDD2 IDD2P,in VDDQ 4 Idle power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; All banks are idle; CA bus inputs are stable; Data bus inputs are stable I DD2PS1 VDD1 IDD2PS2 VDD2 IDD2PS,in VDDQ 4 Idle non-power-down standby current: tCK = tCKmin; CKE is HIGH; CS_n is HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are sta- ble I DD2N1 VDD1 IDD2N2 VDD2 IDD2N,in VDDQ 4 Embedded LPDDR2 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 62: IDD Specification Parameters and Operating Conditions (Continued) Notes 1–3 apply to all parameters and conditions Parameter/Condition Symbol Power Supply Notes Idle non-power-down standby current with clock stopped: CK_t = LOW; CK_c = HIGH; CKE is HIGH; CS_n is HIGH; All banks are idle; CA bus inputs are stable; Data bus inputs are stable IDD2NS1 VDD1 IDD2NS2 VDD2 IDD2NS,in VDDQ 4 Active power-down standby current: tCK = tCKmin; CKE is LOW; CS_n is HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are stable I DD3P1 VDD1 IDD3P2 VDD2 IDD3P,in VDDQ 4 Active power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; One bank is active; CA bus inputs are sta- ble; Data bus inputs are stable I DD3PS1 VDD1 IDD3PS2 VDD2 IDD3PS,in VDDQ 4 Active non-power-down standby current: tCK = tCKmin; CKE is HIGH; CS_n is HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are stable I DD3N1 VDD1 IDD3N2 VDD2 IDD3N,in VDDQ 4 Active non-power-down standby current with clock stopped: CK_t = LOW, CK_c = HIGH CKE is HIGH; CS_n is HIGH; One bank is active; CA bus in- puts are stable; Data bus inputs are stable I DD3NS1 VDD1 IDD3NS2 VDD2 IDD3NS,in VDDQ 4 Operating burst READ current: tCK = tCKmin; CS_n is HIGH between valid commands; One bank is active; BL = 4; RL = RL (MIN); CA bus inputs are switching; 50% data change each burst transfer I DD4R1 VDD1 IDD4R2 VDD2 Operating burst WRITE current: tCK = tCKmin; CS_n is HIGH between valid commands; One bank is active; BL = 4; WL = WLmin; CA bus inputs are switch- ing; 50% data change each burst transfer I DD4W1 VDD1 IDD4W2 VDD2 IDD4W,in VDDQ 4 All-bank REFRESH burst current: tCK = tCKmin; CKE is HIGH between valid commands; tRC = tRFCabmin; Burst refresh; CA bus inputs are switching; Data bus inputs are stable IDD51 VDD1 IDD52 VDD2 IDD5IN VDDQ 4 All-bank REFRESH average current: tCK = tCKmin; CKE is HIGH between valid commands; tRC = tREFI; CA bus inputs are switching; Data bus inputs are stable IDD5AB1 VDD1 IDD5AB2 VDD2 IDD5AB,in VDDQ 4 Per-bank REFRESH average current: tCK = tCKmin; CKE is HIGH between valid commands; tRC = tREFI/8; CA bus inputs are switching; Data bus inputs are stable IDD5PB1 VDD1 5 IDD5PB2 VDD2 5 IDD5PB,in VDDQ 4, 5 Self refresh current (–30˚C to +85˚C): CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are stable; Maximum 1x self refresh rate I DD61 VDD1 6 IDD62 VDD2 6 IDD6IN VDDQ 4, 6 Self refresh current (+85˚C to +105˚C): CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are stable I DD6ET1 VDD1 6, 7 IDD6ET2 VDD2 6, 7 IDD6ET,in VDDQ 4, 6, 7 Embedded LPDDR2 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 62: IDD Specification Parameters and Operating Conditions (Continued) Notes 1–3 apply to all parameters and conditions Parameter/Condition Symbol Power Supply Notes Deep power-down current: CK_t = LOW, CK_c = HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are stable IDD81 VDD1 7 IDD82 VDD2 7 IDD8IN VDDQ 4, 7 Notes: 1. I DD values are the maximum of the distribution of the arithmetic mean. 2. I DD current specifications are tested after the device is properly initialized. 3. The 1x self refresh rate is the rate at which the device is refreshed internally during self refresh before going into the extended temperature range. 4. Measured currents are the sum of V DDQ and VDD2. 5. Per-bank REFRESH is only applicable for LPDDR2-S4 device densities 1Gb or higher. 6. This is the general definition that applies to full-array self refresh. Refer to "IDD6 Full and Partial Array Self-Refresh Current" for details of Partial Array Self Refresh IDD6 specification. 7. I DD6ET and IDD8 are typical values, sampled only and not tested. AC and DC Operating Conditions An operation or timing that is not specified is illegal. To ensure proper operation, the device must be initialized properly. Table 63: Recommended DC Operating Conditions Symbol LPDDR2-S4B Power Supply UnitMin Typ Max VDD11 1.70 1.80 1.95 Core power 1 V VDD2 1.14 1.20 1.30 Core power 2 V VDDQ 1.14 1.20 1.30 I/O buffer power V Note: 1. V DD1 uses significantly less power than VDD2. Table 64: Input Leakage Current Parameter/Condition Symbol Min Max Unit Notes Input leakage current: For CA, CKE, CS_n, CK_t, CK_c; Any input 0V ≤ VIN ≤ VDD2; (All other pins not under test = 0V) IL –2 2 μA1 VREF supply leakage current: VREFDQ = VDDQ/2, or VREFCA = VDD2/2; (All other pins not under test = 0V) IVREF –1 1 μA2 Notes: 1. Although DM is for input only, the DM leakage must match the DQ and DQS_t/DQS_c output leakage specification. 2. The minimum limit requirement is for testing purposes. The leakage current on V REFCA and VREFDQ pins should be minimal. Embedded LPDDR2 SDRAM AC and DC Operating Conditions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 100 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 65: Operating Temperature Range Parameter/Condition Symbol Min Max Unit Standard (WT) temperature range T CASE1 –30 +85 ˚C Industrial (IT) temperature range –40 +85 ˚C Notes: 1. Operating temperature is the case surface temperature at the center of the top side of the device. For measurement conditions, refer to the JESD51-2 standard. 2. Some applications require operation in the maximum case temperature range, between 85˚C and 105˚C. For some LPDDR2 devices, derating may be necessary to operate in this range (see the MR4 Device Temperature (MA[7:0] = 04h) table). 3. Either the device operating temperature or the temperature sensor can be used to set an appropriate refresh rate, determine the need for AC timing derating, and/or monitor the operating temperature (see Temperature Sensor). When using the temperature sen- sor, the actual device case temperature may be higher than the T CASE rating that applies for the operating temperature range. For example, TCASE could be above 85˚C when the temperature sensor indicates a temperature of less than 85˚C. AC and DC Logic Input Measurement Levels for Single-Ended Signals Table 66: Single-Ended AC and DC Input Levels for CA and CS_n Inputs Symbol Parameter LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Unit NotesMin Max Min Max VIHCA(AC) AC input logic HIGH V REF + 0.220 Note 2 V REF + 0.300 Note 2 V 1, 2 VILCA(AC) AC input logic LOW Note 2 V REF - 0.220 Note 2 V REF - 0.300 V 1, 2 VIHCA(DC) DC input logic HIGH V REF + 0.130 V DD2 VREF + 0.200 V DD2 V1 VILCA(DC) DC input logic LOW VSS VREF - 0.130 V SS VREF - 0.200 V 1 VREFCA(DC) Reference voltage for CA and CS_n inputs 0.49 × VDD2 0.51 × VDD2 0.49 × VDD2 0.51 × VDD2 V 3, 4 Notes: 1. For CA and CS_n input-only pins. V REF = VREFCA(DC). 2. See Overshoot and Undershoot Definition. 3. The AC peak noise on V REFCA could prevent VREFCA from deviating more than ±1% VDD2 from VREFCA(DC) (for reference, approximately ±12mV). 4. For reference, approximately V DD2/2 ±12mV. Table 67: Single-Ended AC and DC Input Levels for CKE Symbol Parameter Min Max Unit Notes VIHCKE CKE input HIGH level 0.8 × VDD2 Note 1 V 1 VILCKE CKE input LOW level Note 1 0.2 × VDD2 V1 Note: 1. See Overshoot and Undershoot Definition. Embedded LPDDR2 SDRAM AC and DC Logic Input Measurement Levels for Single-Ended Signals PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 101 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 68: Single-Ended AC and DC Input Levels for DQ and DM Symbol Parameter LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Unit NotesMin Max Min Max VIHDQ(AC) AC input logic HIGH V REF + 0.220 Note 2 V REF + 0.300 Note 2 V 1, 2 VILDQ(AC) AC input logic LOW Note 2 V REF - 0.220 Note 2 V REF - 0.300 V 1, 2 VIHDQ(DC) DC input logic HIGH V REF + 0.130 V DDQ VREF + 0.200 V DDQ V1 VILDQ(DC) DC input logic LOW VSS VREF - 0.130 V SS VREF - 0.200 V 1 VREFDQ(DC) Reference voltage for DQ and DM inputs 0.49 × VDDQ 0.51 × VDDQ 0.49 × VDDQ 0.51 × VDDQ V 3, 4 Notes: 1. For DQ input-only pins. V REF = VREFDQ(DC). 2. See Overshoot and Undershoot Definition. 3. The AC peak noise on V REFDQ could prevent VREFDQ from deviating more than ±1% VDDQ from VREFDQ(DC) (for reference, approximately ±12mV). 4. For reference, approximately. V DDQ/2 ±12mV. VREF Tolerances The DC tolerance limits and AC noise limits for the reference voltages VREFCA and VREFDQ are illustrated below. This figure shows a valid reference voltage VREF(t) as a function of time. VDD is used in place of VDD2 for VREFCA, and VDDQ for VREFDQ. VREF(DC) is the linear average of VREF(t) over a very long period of time (for example, 1 second) and is specified as a fraction of the linear average of VDDQ or VDD2, also over a very long period of time (for example, 1 second). This average must meet the MIN/MAX require- ments in the Single-Ended AC and DC Input Levels for CA and CS_n Inputs table. Addi- tionally, V REF(t) can temporarily deviate from VREF(DC) by no more than ±1% VDD. VREF(t) cannot track noise on VDDQ or VDD2 if doing so would force VREF outside these specifica- tions. Figure 64: VREF DC Tolerance and VREF AC Noise Limits VREF(DC) VREF(DC)max VDD/2 VDD VSS VREF(DC)min Voltage Time VREF(AC) noise VREF(t) Embedded LPDDR2 SDRAM AC and DC Logic Input Measurement Levels for Single-Ended Signals PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 102 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on VREF. VREF DC variations affect the absolute voltage a signal must reach to achieve a valid HIGH or LOW, as well as the time from which setup and hold times are measured. When VREF is outside the specified levels, devices will function correctly with appropriate tim- ing deratings as long as:

V REF is maintained between 0.44 x VDDQ (or VDD2) and 0.56 x VDDQ (or VDD2), and
the controller achieves the required single-ended AC and DC input levels from instan- taneous VREF (see the Single-Ended AC and DC Input Levels for CA and CS_n Inputs table). System timing and voltage budgets must account for VREF deviations outside this range. The setup/hold specification and derating values must include time and voltage associ- ated with VREF AC noise. Timing and voltage effects due to AC noise on VREF up to the specified limit (±1% VDD) are included in LPDDR2 timings and their associated derat- ings. Embedded LPDDR2 SDRAM AC and DC Logic Input Measurement Levels for Single-Ended Signals PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 65: LPDDR2-466 to LPDDR2-1066 Input Signal 0.380V 0.000V 0.470V 0.576V 0.588V 0.600V 0.612V 0.624V 0.730V 0.820V VIL(AC) VIL(DC) VREF - AC noise VREF - DC error VREF + DC error VREF + AC noise VIH(DC) VIH(AC) 1.200V 1.550V –0.350V VDD VDD + 0.35V narrow pulse width VSS - 0.35V narrow pulse width VSS 0.380V 0.470V 0.576V 0.588V 0.600V 0.612V 0.624V 0.730V 0.820V Minimum VIL and VIH levels VIH(DC) VIH(AC) VIL(AC) VIL(DC) VIL and VIH levels with ringback Notes: 1. Numbers reflect typical values. 2. For CA[9:0], CK_t, CK_c, and CS_n V DD stands for VDD2. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ. 3. For CA[9:0], CK_t, CK_c, and CS_n are V SS . For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ. Embedded LPDDR2 SDRAM AC and DC Logic Input Measurement Levels for Single-Ended Signals PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 104 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 66: LPDDR2-200 to LPDDR2-400 Input Signal 0.300V 0.000V 0.400V 0.576V 0.588V 0.600V 0.612V 0.624V 0.800V 0.900V VIL(AC) VIL(DC) VREF - AC noise VREF - DC error VREF + DC error VREF + AC noise VIH(DC) VIH(AC) 1.200V 1.550V –0.350V VDD VDD + 0.35V narrow pulse width VSS - 0.35V narrow pulse width VSS 0.300V 0.400V 0.576V 0.588V 0.600V 0.612V 0.624V 0.800V 0.900V Minimum VIL and VIH levels VIH(DC) VIH(AC) VIL(AC) VIL(DC) VIL and VIH levels with ringback Notes: 1. Numbers reflect typical values. 2. For CA[9:0], CK_t, CK_c, and CS_n V DD stands for VDD2. For DQ, DM, DQS_t, and DQS_c, VDD stands for VDDQ. 3. For CA[9:0], CK_t, CK_c, and CS_n are V SS. For DQ, DM, DQS_t, and DQS_c, VSS stands for VSSQ. Embedded LPDDR2 SDRAM AC and DC Logic Input Measurement Levels for Single-Ended Signals PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 105 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

AC and DC Logic Input Measurement Levels for Differential Signals Figure 67: Differential AC Swing Time and tDVAC tDVAC tDVAC1/2 cycle Time VIH,diff(AC)min VIH,diff(DC)min 0.0 VIL,diff(DC)max VIL,diff(AC)max CK_t, CK_c DQS_t, DQS_c Differential Voltage Table 69: Differential AC and DC Input Levels For CK_t and CK_c, VREF = VREFCA(DC); For DQS_t and DQS_c VREF = VREFDQ(DC) Symbol Parameter LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Unit NotesMin Max Min Max VIH,diff(AC) Differential input HIGH AC 2 × (VIH(AC) - VREF) Note 1 2 × (V IH(AC) - VREF) Note 1 V 2 VIL,diff(AC) Differential input LOW AC Note 1 2 × (V IL(AC) - VREF) Note 1 2 × (V IL(AC) - VREF)V 2 VIH,diff(DC) Differential input HIGH 2 × (V IH(DC) - VREF) Note 1 2 × (V IH(DC) - VREF) Note 1 V 3 VIL,diff(DC) Differential input LOW Note 1 2 × (V IL(DC) - VREF) Note 1 2 × (V IL(DC) - VREF)V 3 Notes: 1. These values are not defined, however the single-ended signals CK_t, CK_c, DQS_t, and DQS_c must be within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals and must comply with the specified limitations for overshoot and undershoot (see Over- shoot and Undershoot Definitions). Embedded LPDDR2 SDRAM AC and DC Logic Input Measurement Levels for Differential Signals PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 106 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

For CK_t and CK_c, use V IH/VIL(AC) of CA and VREFCA; for DQS_t and DQS_c, use VIH/VIL(AC) of DQ and VREFDQ. If a reduced AC HIGH or AC LOW is used for a signal group, the re- duced voltage level also applies. 3. Used to define a differential signal slew rate. For CK_t - CK_c use VIH/VIL(dc) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(dc) of DQs and VREFDQ; if a reduced dc-high or dc-low level is used for a signal group,then the reduced level applies also here. Table 70: CK_t/CK_c and DQS_t/DQS_c Time Requirements Before Ringback (tDVAC) Slew Rate (V/ns) tDVAC (ps) at VIH/VILdiff(AC) = 440mV tDVAC (ps) at VIH/VILdiff(AC) = 600mV Min Min > 4.0 175 75 4.0 170 57 3.0 167 50 2.0 163 38 1.8 162 34 1.6 161 29 1.4 159 22 1.2 155 13 1.0 150 0 < 1.0 150 0 Single-Ended Requirements for Differential Signals Each individual component of a differential signal (CK_t, CK_c, DQS_t, and DQS_c) must also comply with certain requirements for single-ended signals. CK_t and CK_c must meet VSEH(AC)min/VSEL(AC)max in every half cycle. DQS_t, DQS_c must meet VSEH(AC)min/VSEL(AC)max in every half cycle preceding and following a valid transition. The applicable AC levels for CA and DQ differ by speed bin. Embedded LPDDR2 SDRAM AC and DC Logic Input Measurement Levels for Differential Signals PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 68: Single-Ended Requirements for Differential Signals Time VDD2 or VDDQ VSS or VSSQ VDD2/2 or VDDQ/2 VSEH(AC)min VSEH(AC) VSEL(AC)max VSEL(AC) CK or DQS Differential Voltage While CA and DQ signal requirements are referenced to VREF, the single-ended compo- nents of differential signals also have a requirement with respect to VDDQ/2 for DQS, and VDD2/2 for CK. The transition of single-ended signals through the AC levels is used to measure setup time. For single-ended components of differential signals, the requirement to reach V SEL(AC)max or VSEH(AC)min has no bearing on timing. This requirement does, however, add a restriction on the common mode characteristics of these signals (see Single- Ended AC and DC Input Levels for CA and CS_n Inputs for CK_t/CK_c single-ended re- quirements, and Single-Ended AC and DC Input Levels for DQ and DM for DQ and DQM single-ended requirements). Table 71: Single-Ended Levels for CK_t, CK_c, DQS_t, DQS_c Symbol Parameter LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Unit NotesMin Max Min Max VSEH(AC) Single-ended HIGH level for strobes (VDDQ/2) + 0.220 Note 1 (V DDQ/2) + 0.300 Note 1 V 2, 3 Single-ended HIGH level for CK_t, CK_c DD2/2) + 0.220 Note 1 (V DD2/2) + 0.300 Note 1 V 2, 3 VSEL(AC) Single-ended LOW level for strobes Note 1 (V DDQ/2) - 0.220 Note 1 (V DDQ/2) + 0.300 V 2, 3 Single-ended LOW level for CK_t, CK_c Note 1 (V DD2/2) - 0.220 Note 1 (V DD2/2) + 0.300 V 2, 3 Notes: 1. These values are not defined; however, the single-ended signals CK_t, CK_c, DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c must be within the respec- tive limits (VIH(DC)max/ VIL(DC)min) for single-ended signals, and must comply with the Embedded LPDDR2 SDRAM AC and DC Logic Input Measurement Levels for Differential Signals PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

specified limitations for overshoot and undershoot (see Overshoot and Undershoot Defi- nition). 2. For CK_t and CK_c, use V SEH/VSEL(AC) of CA; for strobes (DQS[3:0]_t and DQS[3:0]_c), use VIH/VIL(AC) of DQ. 3. V IH(AC) and VIL(AC) for DQ are based on VREFDQ; VSEH(AC) and VSEL(AC) for CA are based on VREFCA. If a reduced AC HIGH or AC LOW is used for a signal group, the reduced level applies. Differential Input Crosspoint Voltage To ensure tight setup and hold times as well as output skew parameters with respect to clock and strobe, each crosspoint voltage of differential input signals (CK_t, CK_c, DQS_t, and DQS_c) must meet the specifications listed in the Single-Ended Levels for CK_t, CK_c, DQS_t, DQS_c table. The differential input crosspoint voltage (V IX) is meas- ured from the actual crosspoint of the true signal and its and complement to the midle- vel between VDD and VSS. Figure 69: VIX Definition 9'' 9''4 966 9664 9'' 9''4 9'' 9''4 &.BF'46BF 9,; &.BW'46BW 9'' 9''4 966 9664 &.BF'46BF 9,; 9,; &.BW'46BW 9,; ; ; Table 72: Crosspoint Voltage for Differential Input Signals (CK_t, CK_c, DQS_t, DQS_c) Symbol Parameter LPDDR2-1066 to LPDDR2-200 Unit NotesMin Max VIXCA(AC) Differential input crosspoint voltage rela- tive to VDD2/2 for CK_t and CK_c –120 120 mV 1, 2 VIXDQ(AC) Differential input crosspoint voltage rela- tive to V DDQ/2 for DQS_t and DQS_c –120 120 mV 1, 2 Notes: 1. The typical value of V IX(AC) is expected to be about 0.5 × VDD of the transmitting device, and it is expected to track variations in VDD. VIX(AC) indicates the voltage at which differ- ential input signals must cross. 2. For CK_t and CK_c, V REF = VREFCA(DC). For DQS_t and DQS_c, VREF = VREFDQ(DC). Embedded LPDDR2 SDRAM AC and DC Logic Input Measurement Levels for Differential Signals PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 109 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 73: Differential Input Slew Rate Definition

Description

Differential input slew rate for rising edge (CK_t/CK_c and DQS_t/DQS_c) VIL,diff,max VIH,diff,min [VIH,diff,min - VIL,diff,maxΔTRdiff Differential input slew rate for falling edge (CK_t/CK_c and DQS_t/DQS_c) V IH,diff,min VIL,diff,max [VIH,diff,min - VIL,diff,maxΔTFdiff Note: 1. The differential signals (CK_t/CK_c and DQS_t/DQS_c) must be linear between these thresholds. Figure 70: Differential Input Slew Rate Definition for CK_t, CK_c, DQS_t, and DQS_c VIH,diff,min VIL,diff,max Time Differential Input Voltage ΔTFdiff ΔTRdiff Output Characteristics and Operating Conditions Table 74: Single-Ended AC and DC Output Levels Symbol Parameter Value Unit Notes VOH(AC) AC output HIGH measurement level (for output slew rate) VREF + 0.12 V VOL(AC) AC output LOW measurement level (for output slew rate) VREF - 0.12 V VOH(DC) DC output HIGH measurement level (for I-V curve linearity) 0.9 x VDDQ V1 VOL(DC) DC output LOW measurement level (for I-V curve linearity) 0.1 x VDDQ V2 IOZ Output leakage current (DQ, DM, DQS_t, DQS_c); DQ, DQS_t, DQS_c are disabled; 0V ≤ VOUT ≤ VDDQ MIN –5 μA MAX +5 μA Embedded LPDDR2 SDRAM Output Characteristics and Operating Conditions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 74: Single-Ended AC and DC Output Levels (Continued) Symbol Parameter Value Unit Notes MMpupd Delta output impedance between pull-up and pull- down for DQ/DM MIN –15 % MAX +15 % Notes: 1. I OH = –0.1mA. 2. I OL = 0.1mA. Table 75: Differential AC and DC Output Levels Symbol Parameter Value Unit VOHdiff(AC) AC differential output HIGH measurement level (for output SR) + 0.2 x VDDQ V VOLdiff(AC) AC differential output LOW measurement level (for output SR) - 0.2 x VDDQ V Single-Ended Output Slew Rate With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single-ended signals. Table 76: Single-Ended Output Slew Rate Definition Single-ended output slew rate for rising edge V OL(AC) VOH(AC) [VOH(AC) - VOL(AC)ΔTRSE Single-ended output slew rate for falling edge V OH(AC) VOL(AC) [VOH(AC) - VOL(AC)ΔTFSE Note: 1. Output slew rate is verified by design and characterization and may not be subject to production testing. Embedded LPDDR2 SDRAM Output Characteristics and Operating Conditions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 111 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 71: Single-Ended Output Slew Rate Definition VOH(AC) VREF VOL(AC) Time Single-Ended Output Voltage (DQ) ΔTFSE ΔTRSE Table 77: Single-Ended Output Slew Rate Notes 1–5 apply to all parameters conditions Parameter Symbol Value UnitMin Max Single-ended output slew rate (output impedance = 40Ω  SRQSE 1.5 3.5 V/ns Single-ended output slew rate (output impedance = 60Ω  SRQSE 1.0 2.5 V/ns Output slew-rate-matching ratio (pull-up to pull-down) 0.7 1.4 – Notes: 1. Definitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = single- ended signals. 2. Measured with output reference load. 3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage over the entire temperature and voltage range. For a given output, the ratio represents the maximum difference between pull-up and pull-down drivers due to proc- ess variation. 4. The output slew rate for falling and rising edges is defined and measured between V OL(AC) and VOH(AC). 5. Slew rates are measured under typical simultaneous switching output (SSO) conditions, with one-half of DQ signals per data byte driving HIGH and one-half of DQ signals per data byte driving LOW. Differential Output Slew Rate With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL,diff(AC) and VOH,diff(AC) for differential signals. Embedded LPDDR2 SDRAM Output Characteristics and Operating Conditions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 112 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 78: Differential Output Slew Rate Definition Differential output slew rate for rising edge V OL,diff(AC) VOH,diff(AC) [VOH,diff(AC) - VOL,diff(AC)ΔTRdiff Differential output slew rate for falling edge V OH,diff(AC) VOL,diff(AC) [VOH,diff(AC) - VOL,diff(AC)ΔTFdiff Note: 1. Output slew rate is verified by design and characterization and may not be subject to production testing. Figure 72: Differential Output Slew Rate Definition VOH,diff(AC) VOL,diff(AC) Time Differential Output Voltage (DQS_t, DQS_c) ∆TFdiff ∆TRdiff Table 79: Differential Output Slew Rate Parameter Symbol Value UnitMin Max Differential output slew rate (output impedance = 40Ω  SRQdiff 3.0 7.0 V/ns Differential output slew rate (output impedance = 60Ω  SRQdiff 2.0 5.0 V/ns Notes: 1. Definitions: SR = slew rate; Q = output (similar to DQ = data-in, data-out); SE = single- ended signals. 2. Measured with output reference load. 3. The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC). 4. Slew rates are measured under typical simultaneous switching output (SSO) conditions, with one-half of DQ signals per data byte driving HIGH and one-half of DQ signals per data byte driving LOW. Embedded LPDDR2 SDRAM Output Characteristics and Operating Conditions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 113 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 80: AC Overshoot/Undershoot Specification Applies for CA[9:0], CS_n, CKE, CK_t, CK_c, DQ, DQS_t, DQS_c, DM Parameter 1066 933 800 667 533 466 400 333 266 200 Unit Maximum peak amplitude provided for over- shoot area Maximum peak amplitude provided for under- shoot area Maximum area above V Notes: 1. V DD stands for VDD2 for CA[9:0], CK_t, CK_c, CS_n, and CKE. VDD stands for VDDQ for DQ, DM, DQS_t, and DQS_c. 2. V SS is for CA[9:0], CK_t, CK_c, CS_n, and CKE. VSS stands for VSSQ for DQ, DM, DQS_t, and DQS_c. Figure 73: Overshoot and Undershoot Definition Overshoot area VDD VSS Volts (V) Undershoot area Maximum amplitude Maximum amplitude Time (ns) Notes: 1. V DD stands for VDD2 for CA[9:0], CK_t, CK_c, CS_n, and CKE. VDD stands for VDDQ for DQ, DM, DQS_t, and DQS_c. 2. V SS is for CA[9:0], CK_t, CK_c, CS_n, and CKE. VSS stands for VSSQ for DQ, DM, DQS_t, and DQS_c. HSUL_12 Driver Output Timing Reference Load The timing reference loads are not intended as a precise representation of any particu- lar system environment or a depiction of the actual load presented by a production test- er. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally with one or more coaxial transmission lines terminated at the tester electronics. Embedded LPDDR2 SDRAM Output Characteristics and Operating Conditions PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 114 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 74: HSUL_12 Driver Output Reference Load for Timing and Slew Rate LPDDR2 VREF 0.5 × VDDQ Output CLOAD = 5pF VTT = 0.5 × VDDQ 50Ω Note: 1. All output timing parameter values ( tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc.) are reported with respect to this reference load. This reference load is also used to report slew rate. Output Driver Impedance Output driver impedance is selected by a mode register during initialization. To achieve tighter tolerances, ZQ calibration is required. Output specifications refer to the default output drive unless specifically stated otherwise. The output driver impedance R ON is defined by the value of the external reference resistor RZQ as follows: RONPU = VDDQ - VOUT ABS(IOUT) When RONPD is turned of f. RONPD = VOUT When RONPU is turned of f. ABS(IOUT) Embedded LPDDR2 SDRAM Output Driver Impedance PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 115 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 75: Output Driver To other circuitry (RCV, etc.) Output Driver Chip in Drive Mode IPU RONPU RONPD IPD IOUT VDDQ VOUT DQ VSSQ Output Driver Impedance Characteristics with ZQ Calibration Output driver impedance is defined by the value of the external reference resistor RZQ. Typical RZQ is 240 ohms. Table 81: Output Driver DC Electrical Characteristics with ZQ Calibration Notes 1–4 apply to all parameters and conditions RONnom Resistor VOUT Min Typ Max Unit Notes Ω RON34PD 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/7 RON34PU 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/7 Ω RON40PD 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/6 RON40PU 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/6 Ω RON48PD 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/5 RON48PU 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/5 Ω RON60PD 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/4 RON60PU 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/4 Ω RON80PD 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/3 RON80PU 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/3 (optional) RON120PD 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/2 RON120PU 0.5 × VDDQ 0.85 1.00 1.15 R ZQ/2 Mismatch between pull-up and pull-down MMPUPD –15.00 +15.00 % 5 Notes: 1. Applies across entire operating temperature range after calibration. 3. The tolerance limits are specified after calibration, with fixed voltage and temperature. For behavior of the tolerance limits if temperature or voltage changes after calibration, see Output Driver Temperature and Voltage Sensitivity. Embedded LPDDR2 SDRAM Output Driver Impedance PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 116 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Pull-down and pull-up output driver impedances should be calibrated at 0.5 x V DDQ. 5. Measurement definition for mismatch between pull-up and pull-down, MM PUPD: Measure RONPU and RONPD, both at 0.5 × VDDQ: MMPUPD = RONPU – RONPD × 100 R ON,nom For example, with MMPUPD (MAX) = 15% and RONPD = 0.85, RONPU must be less than 1.0. Output Driver Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen. Table 82: Output Driver Sensitivity Definition Resistor VOUT Min Max Unit RONPD 0.5 × VDDQ 85 – (dRONdT ΔT|) – (dRONdV ΔV|) 115 + (dR ONdT ΔT|) + (dRONdV ΔV|) % RONPU Notes: 1. ΔT = T - T (at calibration). ΔV = V - V (at calibration). 2. dR ONdT and dRONdV are not subject to production testing; they are verified by design and characterization. Table 83: Output Driver Temperature and Voltage Sensitivity Symbol Parameter Min Max Unit RONdT RON temperature sensitivity 0.00 0.75 %/˚C RONdV RON voltage sensitivity 0.00 0.20 %/mV Output Impedance Characteristics Without ZQ Calibration Output driver impedance is defined by design and characterization as the default set- ting. Table 84: Output Driver DC Electrical Characteristics Without ZQ Calibration RONnom Resistor VOUT Min Typ Max Unit Ω RON34PD 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/7 RON34PU 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/7 Ω RON40PD 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/6 RON40PU 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/6 Ω RON48PD 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/5 RON48PU 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/5 Ω RON60PD 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/4 RON60PU 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/4 Ω RON80PD 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/3 RON80PU 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/3 Embedded LPDDR2 SDRAM Output Driver Impedance PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 117 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 84: Output Driver DC Electrical Characteristics Without ZQ Calibration (Continued) RONnom Resistor VOUT Min Typ Max Unit (optional) RON120PD 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/2 RON120PU 0.5 × VDDQ 0.70 1.00 1.30 R ZQ/2 Notes: 1. Applies across entire operating temperature range without calibration. Table 85: I-V Curves Voltage (V) Pull-Down Pull-Up Current (mA) / RON (ohms) Current (mA) / RON (ohms) Default Value after ZQRESET With Calibration Default Value after ZQRESET With Calibration Min (mA) Max (mA) Min (mA) Max (mA) Min (mA) Max (mA) Min (mA) Max (mA) Embedded LPDDR2 SDRAM Output Driver Impedance PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 118 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 76: Output Impedance = 240 Ohms, I-V Curves After ZQRESET –6 mA Voltage PD (MAX) PD (MIN) PU (MIN) PU (MAX) Embedded LPDDR2 SDRAM Output Driver Impedance PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 119 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 77: Output Impedance = 240 Ohms, I-V Curves After Calibration mA Voltage PD (MAX) PD (MIN) PU (MIN) PU (MAX) Clock Specification The specified clock jitter is a random jitter with Gaussian distribution. Input clocks vio- lating minimum or maximum values may result in device malfunction. Embedded LPDDR2 SDRAM Clock Specification PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 120 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 86: Definitions and Calculations Symbol Description Calculation Notes tCK(avg) and nCK The average clock period across any consecutive 200-cycle window. Each clock period is calculated from rising clock edge to rising clock edge. Unit tCK(avg) represents the actual clock average tCK(avg)of the input clock under operation. Unit nCK represents one clock cycle of the input clock, counting from actual clock edge to actual clock edge. tCK(avg)can change no more than ±1% within a 100-clock-cycle window, provided that all jitter and timing specifications are met. tCK(avg) = Σ tCKj /N Where N = 200 N j = 1 tCK(abs) The absolute clock period, as measured from one rising clock edge to the next consecutive rising clock edge. tCH(avg) The average HIGH pulse width, as calculated across any 200 consecutive HIGH pulses. tCH(avg) = Σ tCHj /(N × tCK(avg)) Where N = 200 N j = 1 tCL(avg) The average LOW pulse width, as calculated across any 200 consecutive LOW pulses. tCL(avg) = Σ tCLj /(N × tCK(avg)) Where N = 200 N j = 1 tJIT(per) The single-period jitter defined as the largest de- viation of any signal tCK from tCK(avg). tJIT(per) = min/max of tCKi – tCK(avg) Where i = 1 to 200 tJIT(per),act The actual clock jitter for a given system. tJIT(per), allowed The specified clock period jitter allowance. tJIT(cc) The absolute difference in clock periods between two consecutive clock cycles. tJIT(cc) defines the cycle-to-cycle jitter. tJIT(cc) = max of tCKi + 1 – tCKi tERR(nper) The cumulative error across n multiple consecu- tive cycles from tCK(avg). tERR(nper) = Σ tCKj – (n × tCK(avg)) i + n – 1 j = i tERR(nper),act The actual cumulative error over n cycles for a given system. tERR(nper), allowed The specified cumulative error allowance over n cycles. tERR(nper),min The minimum tERR(nper). tERR(nper),min = (1 + 0.68LN(n)) × tJIT(per),min 2 tERR(nper),max The maximum tERR(nper). tERR(nper),max = (1 + 0.68LN(n)) × tJIT(per),max 2 Embedded LPDDR2 SDRAM Clock Specification PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 121 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 86: Definitions and Calculations (Continued) Symbol Description Calculation Notes tJIT(duty) Defined with absolute and average specifications for tCH and tCL, respectively. tJIT(duty),min = MIN((tCH(abs),min – tCH(avg),min), (tCL(abs),min – tCL(avg),min)) × tCK(avg) tJIT(duty),max = MAX((tCH(abs),max – tCH(avg),max), (tCL(abs),max – tCL(avg),max)) × tCK(avg) Notes: 1. Not subject to production testing. 2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value. tCK(abs), tCH(abs), and tCL(abs) These parameters are specified with their average values; however, the relationship be- tween the average timing and the absolute instantaneous timing (defined in the follow- ing table) is applicable at all times. Table 87: tCK(abs), tCH(abs), and tCL(abs) Definitions Parameter Symbol Minimum Unit Absolute clock period tCK(abs) tCK(avg),min + tJIT(per),min ps1 Absolute clock HIGH pulse width tCH(abs) tCH(avg),min + tJIT(duty),min2/tCK(avg)min tCK(avg) Absolute clock LOW pulse width tCL(abs) tCL(avg),min + tJIT(duty),min2/tCK(avg)min tCK(avg) Notes: 1. tCK(avg),min is expressed in ps for this table. 2. tJIT(duty),min is a negative value. Clock Period Jitter The LPDDR2 device can tolerate some clock period jitter without core timing parameter derating. This section describes device timing requirements with clock period jitter tJIT(per)) in excess of the values found in the AC Timing section. Calculating cycle time derating and clock cycle derating are also described. Clock Period Jitter Effects on Core Timing Parameters Core timing parameters (tRCD, tRP , tRTP , tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) ex- tend across multiple clock cycles. Clock period jitter impacts these parameters when measured in numbers of clock cycles. Within the specification limits, the device is char- acterized and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device op- eration where clock jitter is outside specification limits, the number of clocks or tCK(avg), may need to be increased based on the values for each core timing parameter. Embedded LPDDR2 SDRAM Clock Period Jitter PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 122 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Cycle Time Derating for Core Timing Parameters For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM),act exceed tERR(tnPARAM),allowed, cycle time derating may be required for core timing parame- ters. Cycle TimeDerating = max tPARAM + tERR(tnPARAM),act – tERR(tnPARAM),allowed – tCK(avg) , 0 tnPARAM Cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time derating required is the maximum of the cycle time deratings de- termined for each individual core timing parameter. Clock Cycle Derating for Core Timing Parameters For each core timing parameter and a given number of clocks (tnPARAM), clock cycle derating should be specified with tJIT(per). For a given number of clocks (tnPARAM), when tCK(avg) plus (tERR(tnPARAM),act) ex- ceed the supported cumulative tERR(tnPARAM),allowed, derating is required. If the equation below results in a positive value for a core timing parameter (tCORE), the re- quired clock cycle derating will be that positive value (in clocks). ClockCycle Derating = RU tPARAM + tERR(tnPARAM),act – tERR(tnPARAM),allowed – tnPARAM tCK(avg) Cycle-time derating analysis should be conducted for each core timing parameter. Clock Jitter Effects on Command/Address Timing Parameters Command/address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb, tIHCKEb) are measured from a command/address signal (CKE, CS_n, or CA[9:0]) transi- tion edge to its respective clock signal (CK_t/CK_c) crossing. The specification values are not affected by the tJIT(per) applied, because the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met. Clock Jitter Effects on READ Timing Parameters tRPRE When the device is operated with input clock jitter, tRPRE must be derated by the tJIT(per),act,max of the input clock that exceeds tJIT(per),allowed,max. Output derat- ings are relative to the input clock: tRPRE(min,derated) = 0.9 – tJIT(per),act,max – tJIT(per),allowed,max tCK(avg) For example, if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500ps, tJIT(per),act,min = –172ps, and tJIT(per),act,max = +193ps, then tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500 = 0.8628 tCK(avg). tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) Embedded LPDDR2 SDRAM Clock Period Jitter PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 123 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

These parameters are measured from a specific clock edge to a data signal transition (DMn or DQm, where: n = 0, 1, 2, or 3; and m = DQ[31:0]), and specified timings must be met with respect to that clock edge. Therefore, they are not affected by tJIT(per). tQSH, tQSL These parameters are affected by duty cycle jitter, represented by tCH(abs)min and tCL(abs)min. These parameters determine the absolute data valid window at the device pin. The absolute minimum data valid window at the device pin = min [(tQSH(abs)min × tCK(avg)min - tDQSQmax - tQHSmax), (tQSL(abs)min × tCK(avg)min - tDQSQmax - tQHSmax)]. This minimum data valid window must be met at the target frequency re- gardless of clock jitter. tRPST tRPST is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min. Clock Jitter Effects on WRITE Timing Parameters tDS, tDH These parameters are measured from a data signal (DMn or DQm, where n = 0, 1, 2, 3; and m = DQ[31:0]) transition edge to its respective data strobe signal (DQSn_t, DQSn_c: n = 0,1,2,3) crossing. The specification values are not affected by the amount of tJIT(per) applied, because the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met. tDSS, tDSH These parameters are measured from a data strobe signal crossing (DQSx_t, DQSx_c) to its clock signal crossing (CK_t/CK_c). The specification values are not affected by the amount of tJIT(per)) applied, because the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met. tDQSS tDQSS is measured from the clock signal crossing (CK_t/CK_c) to the first latching data strobe signal crossing (DQSx_t, DQSx_c). When the device is operated with input clock jitter, this parameter must be derated by the actual tJIT(per),act of the input clock in ex- cess of tJIT(per),allowed. tDQSS(min,derated) = 0.75 - tJIT(per),act,min – tJIT(per),allowed, min tCK(avg) tDQSS(max,derated) = 1.25 – tJIT(per),act,max – tJIT(per),allowed, max tCK(avg) For example, if the measured jitter into an LPDDR2-800 device has tCK(avg) = 2500ps, tJIT(per),act,min = -172ps, and tJIT(per),act,max = +193ps, then: tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = Embedded LPDDR2 SDRAM Clock Period Jitter PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 124 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Refresh Requirements Parameters Table 88: Refresh Requirement Parameters (Per Density) Parameter Symbol 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb Unit Number of banks 44448888 Refresh window: TCASE ≤ 85˚ tREFW 32 32 32 32 32 32 32 32 ms Refresh window: 85˚C < TCASE ≤ 105˚C tREFW 88888888 m s Required number of REFRESH commands (MIN) R 2048 2048 4096 4096 4096 8192 8192 8192 Average time be- tween REFRESH com- mands (for reference only) T CASE ≤ 85˚C REFpb tREFIpb (REFpb not supported below 1Gb) 0.975 0.4875 0.4875 0.4875 μs Refresh cycle time tRFCab 90 90 90 90 130 130 130 210 ns Per-bank REFRESH cycle time tRFCpb na 60 60 60 90 ns Burst REFRESH window = 4 × 8 × tRFCab AC Timing Table 89: AC Timing Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul- tiples of tCK) as well as the timing specifications when values for both are indicated. Parameter Symbol Min/ Max tCK Min Data Rate Unit Notes1066 933 800 667 533 400 333 Maximum frequency – – 533 466 400 333 266 200 166 MHz Clock Timing Average clock period tCK(avg) MIN – 1.875 2.15 2.5 3 3.75 5 6 ns MAX – 100 100 100 100 100 100 100 (avg) (avg) Absolute clock period tCK(abs) MIN – tCK(avg)min ± tJIT(per)min ps Absolute clock HIGH pulse width (with allowed jitter) tCH(abs), allowed (avg) Absolute clock LOW pulse width (with allowed jitter) tCL(abs), allowed (avg) Clock period jitter (with supported jitter) tJIT(per), allowed MIN – -90 -95 -100 -110 -120 -140 -150 ps MAX – 90 95 100 110 120 140 150 Embedded LPDDR2 SDRAM Refresh Requirements Parameters PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 125 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 89: AC Timing (Continued) Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul- tiples of tCK) as well as the timing specifications when values for both are indicated. Parameter Symbol Min/ Max tCK Min Data Rate Unit Notes1066 933 800 667 533 400 333 Maximum clock jitter between two consectuive clock cycles (with allowed jitter) tJIT(cc), allowed MAX – 180 190 200 220 240 280 300 ps Duty cycle jitter (with allowed jitter) tJIT(duty), allowed MIN – MIN (( tCH(abs),min - tCH(avg),min), (tCL(abs),min - tCL(avg),min)) × tCK(avg) ps MAX – MAX (( tCH(abs),max - tCH(avg),max), (tCL(abs),max - tCL(avg),max)) × tCK(avg) Cumulative errors across 2 cycles tERR(2per), allowed MIN – -132 -140 -147 -162 -177 -206 -221 ps MAX – 132 140 147 162 177 206 221 Cumulative errors across 3 cycles tERR(3per), allowed MIN – -157 -166 -175 -192 -210 -245 -262 ps MAX – 157 166 175 192 210 245 262 Cumulative errors across 4 cycles tERR(4per), allowed MIN – -175 -185 -194 -214 -233 -272 -291 ps MAX – 175 185 194 214 233 272 291 Cumulative errors across 5 cycles tERR(5per), allowed MIN – -188 -199 -209 -230 -251 -293 -314 ps MAX – 188 199 209 230 251 293 314 Cumulative errors across 6 cycles tERR(6per), allowed MIN – -200 -211 -222 -244 -266 -311 -333 ps MAX – 200 211 222 244 266 311 333 Cumulative errors across 7 cycles tERR(7per), allowed MIN – -209 -221 -232 -256 -279 -325 -348 ps MAX – 209 221 232 256 279 325 348 Cumulative errors across 8 cycles tERR(8per), allowed MIN – -217 -229 -241 -266 -290 -338 -362 ps MAX – 217 229 241 266 290 338 362 Cumulative errors across 9 cycles tERR(9per), allowed MIN – -224 -237 -249 -274 -299 -349 -374 ps MAX – 224 237 249 274 299 349 374 Cumulative errors across 10 cycles tERR(10per), allowed MIN – -231 -244 -257 -282 -308 -359 -385 ps MAX – 231 244 257 282 308 359 385 Cumulative errors across 11 cycles tERR(11per), allowed MIN – -237 -250 -263 -289 -316 -368 -395 ps MAX – 237 250 263 289 316 368 395 Cumulative errors across 12 cycles tERR(12per), allowed MIN – -242 -256 -269 -296 -323 -377 -403 ps MAX – 242 256 269 296 323 377 403 Cumulative errors across n = 13, 14, 15…, 49, 50 cycles tERR(nper), allowed MIN tERR(nper),allowed,min = (1 + 0.68ln(n)) × tJIT(per),allowed,min ps MAX tERR(nper), allowed,max = (1 + 0.68ln(n)) × tJIT(per),allowed,max ZQ Calibration Parameters Initialization calibration time tZQINIT MIN – 1 1 1 1 1 1 1 μs Long calibration time tZQCL MIN 6 360 360 360 360 360 360 360 ns Short calibration time tZQCS MIN 6 90 90 90 90 90 90 90 ns Embedded LPDDR2 SDRAM AC Timing PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 126 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 89: AC Timing (Continued) Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul- tiples of tCK) as well as the timing specifications when values for both are indicated. Parameter Symbol Min/ Max tCK Min Data Rate Unit Notes1066 933 800 667 533 400 333 tDQSCK derating tDQSCK (derated) MAX – 5620 6000 6000 6000 6000 6000 6000 ps Core timing temperature derating tRCD (derated) MIN – tRCD + 1.875 ns tRC (derated) MIN – tRC + 1.875 ns tRAS (derated) MIN – tRAS + 1.875 ns tRP (derated) MIN – tRP + 1.875 ns tRRD (derated) MIN – tRRD + 1.875 ns Notes: 1. Frequency values are for reference only. Clock cycle time ( tCK) is used to determine de- vice capabilities. 2. All AC timings assume an input slew rate of 1 V/ns. 3. READ, WRITE, and input setup and hold values are referenced to V REF. 4. tDQSCKDS is the absolute value of the difference between any two tDQSCK measure- ments (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include clock jitter. 5. tDQSCKDM is the absolute value of the difference between any two tDQSCK measure- ments (in a byte lane) within a 1.6μs rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include clock jitter. 6. tDQSCKDL is the absolute value of the difference between any two tDQSCK measure- ments (in a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include clock jitter. For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point when the signal crosses the transition threshold (V TT). tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ)). The figure below shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ) or begins driving tLZ(DQS) and tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and tRPST are determined from the differential signal DQS_t/DQS_c. Output Transition Timing Embedded LPDDR2 SDRAM AC Timing PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 130 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

X 2x Y VOH VOL Y T1 T2 VTT - Y mV VTT VTT VTT - 2x Y mV VTT + 2x Y mV VTT + Y mV tLZ(DQS), tLZ(DQ) tHZ(DQS), tHZ(DQ) T1 T2 Start driving point = 2 × T1 - T2 End driving point = 2 × T1 - T2 actual wave form 7. Measured from the point when DQS_t/DQS_c begins driving the signal, to the point when DQS_t/DQS_c begins driving the first rising strobe edge. 8. Measured from the last falling strobe edge of DQS_t/DQS_c to the point when DQS_t/ DQS_c finishes driving the signal. 9. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to CK_t/CK_c crossing. 10. CKE input hold time is measured from CK_t/CK_n crossing to CKE reaching a HIGH/LOW voltage level. 11. Input setup/hold time for signal (CA[9:0], CS_n). 12. To ensure device operation before the device is configured, a number of AC boot timing parameters are defined in this table. The letter b is appended to the boot parameter symbols (for example, tCK during boot is tCKb). 13. Mobile LPDDR2 devices set some mode register default values upon receiving a RESET (MRW) command, as specified in Mode Register Definition. 14. The output skew parameters are measured with default output impedance settings using the reference load. 15. The minimum tCK column applies only when tCK is greater than 6ns. 16. Timing derating applies for operation at 85˚C to 105˚C when the requirement to derate is indicated by mode register 4 op-code (see the MR4 Device Temperature (MA[7:0] = 04h) table). 17. DRAM devices should be evenly addressed when being accessed. Disproportionate ac- cesses to a particular row address may result in reduction of the product lifetime. CA and CS_n Setup, Hold, and Derating For all input signals (CA and CS_n), the total required setup time (tIS) and hold time (tIH) are calculated by adding the data sheet tIS (base) and tIH (base) values to the ΔtIS and ΔtIH derating values, respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS. (See the series of tables following this section.) The typical setup slew rate (tIS) for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. The typical setup slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is consistently earlier than the typical slew rate line between the shaded VREF(DC)-to-(AC) region, use the typical slew rate for the derating value (see Figure 78 (page 135)). If the actual signal is later than the typical slew rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a Embedded LPDDR2 SDRAM CA and CS_n Setup, Hold, and Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 131 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

tangent line to the actual signal from the AC level to the DC level is used for the derating value (see Figure 80 (page 137)). The hold (tIH) typical slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). The hold (tIH) typical slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is consistently later than the typical slew rate line between the shaded DC-to-VREF(DC) region, use the typical slew rate for the derating value (see Figure 79 (page 136)). If the actual signal is earlier than the typi- cal slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from the DC level to VREF(DC) level is used for the derat- ing value (see Figure 81 (page 138)). For a valid transition, the input signal must remain above or below VIH/VIL(AC) for a specified time, tVAC (see Table 94 (page 133)). For slow slew rates the total setup time could be a negative value; that is, a valid input signal will not have reached VIH/VIL(AC) at the time of the rising clock transition. A valid input signal is still required to complete the transition and reach VIH/VIL(AC). For slew rates between the values listed in Table 92, the derating values are obtained us- ing linear interpolation. Typically, slew rate values are not subject to production testing. They are verified by design and characterization. Table 90: CA and CS_n Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) Parameter Data Rate Reference1066 933 800 667 533 466 tIS (base) 0 30 70 150 240 300 V IH/VIL(AC) = VREF(DC) ±220mV tIH (base) 90 120 160 240 330 390 V IH/VIL(DC) = VREF(DC) ±130mV Note: 1. AC/DC referenced for 1 V/ns CA and CS_n slew rate, and 2 V/ns differential CK_t/CK_c slew rate. Table 91: CA and CS_n Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate) Parameter Data Rate Reference400 333 266 200 tIS (base) 300 440 600 850 VIH/VIL(AC) = VREF(DC) ±300mV tIH (base) 400 540 700 950 VIH/VIL(DC) = VREF(DC) ±200mV Note: 1. AC/DC referenced for 1 V/ns CA and CS_n slew rate, and 2 V/ns differential CK_t/CK_c slew rate. Embedded LPDDR2 SDRAM CA and CS_n Setup, Hold, and Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 92: Derating Values for AC/DC-Based tIS/tIH (AC220) ΔtIS, ΔtIH derating in ps AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV DC100 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV CK_t, CK_c Differential Slew Rate ΔΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH CA, CS_n slew rate V/ns 2.0 110 65 110 65 110 65 1.5 74 43 73 43 73 43 89 59 1.0 0 0 0 0 00 16 16 32 32 0.9 -3 -5 -3 -5 13 11 29 27 45 43 0.8 -8 -13 8 3 24 19 40 35 56 55 0.7 2 - 61 81 03 42 65 04 66 67 8 0.6 10 -3 26 13 42 33 58 65 0.5 4 - 42 01 63 64 8 0.4 -7 2 17 34 Note: 1. Shaded cells are not supported. Table 93: Derating Values for AC/DC-Based tIS/tIH (AC300) ΔtIS, ΔtIH derating in ps AC300 Threshold -> VIH(ac)=VREF(dc)+300mV, VIL(ac)=VREF(dc)-300mV DC200 Threshold -> VIH(dc)=VREF(dc)+200mV, VIL(dc)=VREF(dc)-200mV CK_t, CK_c Differential Slew Rate ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH CA, CS_n slew rate V/ns 2.0 150 100 150 100 150 100 1.5 100 67 100 67 100 67 116 83 1.0 0 0 0 0 00 16 16 32 32 0.9 -4 -8 -4 -8 12 8 28 24 44 40 0.8 - 1 2 - 2 04 - 42 01 23 62 85 24 8 0.7 -3 -18 13 -2 29 14 45 34 61 66 0.6 2 -21 18 -5 34 15 50 47 0.5 -12 -32 4 -12 20 20 0.4 -35 -40 -11 -8 Note: 1. Shaded cells are not supported. Table 94: Required Time for Valid Transition – tVAC > VIH(AC) and < VIL(AC) Slew Rate (V/ns) tVAC at 300mV (ps) tVAC at 220mV (ps) Min Max Min Max >2.0 75 – 175 – Embedded LPDDR2 SDRAM CA and CS_n Setup, Hold, and Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 133 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 94: Required Time for Valid Transition – tVAC > VIH(AC) and < VIL(AC) (Continued) Slew Rate (V/ns) tVAC at 300mV (ps) tVAC at 220mV (ps) Min Max Min Max 2.0 57 – 170 – 1.5 50 – 167 – 1.0 38 – 163 – 0.9 34 – 162 – 0.8 29 – 161 – 0.7 22 – 159 – 0.6 13 – 155 – 0.5 0 – 150 – <0.5 0 – 150 – Embedded LPDDR2 SDRAM CA and CS_n Setup, Hold, and Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 134 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 78: Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock VSS CK_t CK_c tVAC Setup slew rate rising signal Setup slew rate falling signal TF TR TF VIH(AC)min - VREF(DC) TR VDD2 Typical slew rate VREF to AC region VREF to AC region VREF(DC) - VIL(AC)max VIH(DC)min VREF(DC) VIL(AC)max VIL(DC)max VIH(AC)min Typical slew rate tIHtIS tIStIH tVAC Embedded LPDDR2 SDRAM CA and CS_n Setup, Hold, and Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 135 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 79: Typical Slew Rate – tIH for CA and CS_n Relative to Clock TR TF Typical slew rate DC to VREF region VSS CK_t CK_c VDD2 VIH(DC)min VREF(DC) VIL(AC)max VIL(DC)max VIH(AC)min DC to VREF region Typical slew rate Hold slew rate rising signal VREF(DC) - VIL(DC)max TR Hold slew rate falling signal V IH(DC)min - VREF(DC) TF tIHtIS tIStIH Embedded LPDDR2 SDRAM CA and CS_n Setup, Hold, and Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 136 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 80: Tangent Line – tIS for CA and CS_n Relative to Clock Setup slew rate rising signal TF TR tangent line [VIH(AC)min - VREF(DC)] TR Setup slew rate falling signal tangent line [V REF(DC) - VIL(AC)]max] TF Tangent line Tangent line VREF to AC region Typical line Typical line VSS CK_t CK_c VDD2 VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max VREF to AC region tVAC tIHtIS tIStIH tVAC Embedded LPDDR2 SDRAM CA and CS_n Setup, Hold, and Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 137 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 81: Tangent Line – tIH for CA and CS_n Relative to Clock Tangent line DC to VREF region tIHtIS tIS VSS VDD2 VIH(DC)min VREF(DC) VIL(AC)max VIL(DC)max VIH(AC)min DC to VREF region Tangent line tIH CK_c CK_t Hold slew rate falling signal TFTR tangent line [VIH(DC)min - VREF(DC)] TF Typical line Hold slew rate rising signal tangent line [V REF(DC) - VIL(DC)max] TR Typical line Embedded LPDDR2 SDRAM CA and CS_n Setup, Hold, and Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 138 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Data Setup, Hold, and Slew Rate Derating For all input signals (DQ, DM) the total required setup time (tDS) and hold time (tDH) are calculated by adding the data sheet tDS(base) and tDH(base) values (see the follow- ing table) to the ΔtDS and ΔtDH derating values, respectively (see the following derating tables). Example: tDS = tDS(base) + ΔtDS. The typical tDS slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. The typical tDS slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max (see the Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe figure). If the actual signal is consistently earlier than the typical slew rate line in the figure, "Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock (CA and CS_n Setup, Hold, and Derating), the area shaded gray between the VREF(DC) region and the AC re- gion, use the typical slew rate for the derating value. If the actual signal is later than the typical slew rate line anywhere between the shaded V REF(DC) region and the AC region, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the derating value (see figure "Tangent Line – tIS for CA and CS_n Relative to Clock" in CA and CS_n Setup, Hold, and Derating). The typical tDH slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). The typical tDH slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC) (see the Typical Slew Rate – DH for DQ Relative to Strobe fig- ure). If the actual signal is consistently later than the typical slew rate line between the shaded DC-level-to-V REF(DC) region, the typical slew rate should be used for the derating value. If the actual signal is earlier than the typical slew rate line anywhere between sha- ded DC-to-V REF(DC) region, the slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is used for the derating value (see the Tangent Line – tDH for DQ with Respect to Strobe figure). For a valid transition, the input signal must remain above or below VIH/VIL(AC) for the specified time, tVAC (see the Required Time for Valid Transition – tVAC > VIH(AC) or < VIL(AC) table). The total setup time for slow slew rates could be negative; that is, a valid input signal may not have reached VIH/VIL(AC) at the time of the rising clock transition. A valid input signal is still required to complete the transition and reach VIH/VIL(AC). For slew rates between the values listed in the following tables, the derating values can be obtained using linear interpolation. Typically, slew rate values are not subject to pro- duction testing. They are verified by design and characterization. Table 95: Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) Parameter Data Rate Reference1066 933 800 667 533 466 tDS (base) -10 15 50 130 210 230 V IH/VIL(AC) = VREF(DC) ±220mV Embedded LPDDR2 SDRAM Data Setup, Hold, and Slew Rate Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 139 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 95: Data Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate) (Continued) Parameter Data Rate Reference1066 933 800 667 533 466 tDH (base) 80 105 140 220 300 320 V IH/VIL(DC) = VREF(DC) ±130mV Note: 1. AC/DC referenced for 1 V/ns DQ, DM slew rate, and 2 V/ns differential DQS_t/DQS_c slew rate. Table 96: Data Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate) Parameter Data Rate Reference400 333 266 200 tDS (base) 180 300 450 700 VIH/VIL(AC) = VREF(DC) ±300mV tDH (base) 280 400 550 800 VIH/VIL(DC) = VREF(DC) ±200mV Note: 1. AC/DC referenced for 1 V/ns DQ, DM slew rate, and 2 V/ns differential DQS_t/DQS_c slew rate. Table 97: Derating Values for AC/DC-Based tDS/tDH (AC220) ΔtDS, ΔtDH derating in ps AC220 Threshold -> VIH(ac)=VREF(dc)+220mV, VIL(ac)=VREF(dc)-220mV DC130 Threshold -> VIH(dc)=VREF(dc)+130mV, VIL(dc)=VREF(dc)-130mV DQS_t, DQS_c Differential Slew Rate ΔΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH DQ, DM slew rate V/ns 2.0 110 65 110 65 110 65 1.5 74 43 73 43 73 43 89 59 1.0 0 0 0 0 00 16 16 32 32 0.9 -3 -5 -3 -5 13 11 29 27 45 43 0.8 -8 -13 8 3 24 19 40 35 56 55 0.7 2 - 61 81 03 42 65 04 66 67 8 0.6 10 -3 26 13 42 33 58 65 0.5 4 - 42 01 63 64 8 0.4 -7 2 17 34 Note: 1. Shaded cells are not supported. Embedded LPDDR2 SDRAM Data Setup, Hold, and Slew Rate Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 140 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 98: Derating Values for AC/DC-Based tDS/tDH (AC300) ΔtDS, ΔtDH derating in ps AC300 Threshold -> VIH(ac)=VREF(dc)+300mV, VIL(ac)=VREF(dc)-300mV DC200 Threshold -> VIH(dc)=VREF(dc)+200mV, VIL(dc)=VREF(dc)-200mV DQS_t, DQS_c Differential Slew Rate ΔΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH DQ, DM slew rate V/ns 2.0 150 100 150 100 150 100 1.5 100 67 100 67 100 67 116 83 1.0 0 0 0 0 00 16 16 32 32 0.9 -4 -8 -4 -8 12 8 28 24 44 40 0.8 -12 -20 4 -4 20 12 36 28 52 48 0.7 -3 -18 13 -2 29 14 45 34 61 66 0.6 2 -21 18 -5 34 15 50 47 0.5 -12 -32 4 -12 20 20 0.4 -35 -40 -11 -8 Note: 1. Shaded cells are not supported. Table 99: Required Time for Valid Transition – tVAC > VIH(AC) or < VIL(AC) Slew Rate (V/ns) tVAC at 300mV (ps) tVAC at 220mV (ps) Min Max Min Max >2.0 75 – 175 – 2.0 57 – 170 – 1.5 50 – 167 – 1.0 38 – 163 – 0.9 34 – 162 – 0.8 29 – 161 – 0.7 22 – 159 – 0.6 13 – 155 – 0.5 0 – 150 – <0.5 0 – 150 – Embedded LPDDR2 SDRAM Data Setup, Hold, and Slew Rate Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 141 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 82: Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe VREF to AC region VREF to AC region Setup slew rate rising signal Setup slew rate falling signal TF TR VREF(DC) - VIL(AC)max TF VIH(AC)min - VREF(DC) TR Typical slew rate VSSQ DQS_t DQS_c VDDQ VIH(DC)min VREF(DC) VIL(AC)max VIL(DC)max VIH(AC)min Typical slew rate tVAC tVAC tDHtDS tDStDH Embedded LPDDR2 SDRAM Data Setup, Hold, and Slew Rate Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 142 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 83: Typical Slew Rate – tDH for DQ Relative to Strobe Hold slew rate falling signal Hold slew rate rising signal V REF(DC) - VIL(DC)max TR= VIH(DC)min - VREF(DC) TF= TR TF Typical slew rate DC to V REF region VSSQ DQS_t DQS_c VDDQ VIH(DC)min VREF(DC) VIL(AC)max VIL(DC)max VIH(AC)min DC to VREF region Typical slew rate tDHtDS tDStDH Embedded LPDDR2 SDRAM Data Setup, Hold, and Slew Rate Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 143 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 84: Tangent Line – tDS for DQ with Respect to Strobe TF TR Setup slew rate rising signal Setup slew rate falling signal tangent line [V REF(DC) - VIL(AC)max] TF tangent line [VIH(AC)min - VREF(DC)] TR VSSQ DQS_t DQS_c VDDQ VIH(DC)min VREF(DC) VIL(AC)max VIL(DC)max VIH(AC)min Typical line Tangent line Typical line Tangent line VREF to AC region VREF to AC region tVAC tDHtDS tDStDH tVAC Embedded LPDDR2 SDRAM Data Setup, Hold, and Slew Rate Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 144 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 85: Tangent Line – tDH for DQ with Respect to Strobe Tangent line DC to VREF region VSSQ VDDQ VIH(DC)min VREF(DC) VIL(AC)max VIL(DC)max VIH(AC)min DC to VREF region Tangent line DQS_c DQS_t Hold slew rate falling signal ∆TF∆TR tangent line [VIH(DC)min - VREF(DC)] TF= Typical line Hold slew rate rising signal tangent line [VREF(DC) - VIL(DC)max] TR Nominal line tDHtDS tDStDH Embedded LPDDR2 SDRAM Data Setup, Hold, and Slew Rate Derating PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 145 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Revision History

Rev. C – 1/16

Converted from addendum to full datasheet
Updated Package Dimensions Rev. B – 7/14
Updated resistors in Package Block Diagram Rev. A – 4/14
Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. Embedded LPDDR2 SDRAM

PDF: 09005aef85a1f01d 168b_2e0e_embedded_lpddr2_sdram.pdf – Rev. C 1/16 EN 146 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Product Information

B8132B4PB-8D-F specifications and overview.

Summary

Embedded LPDDR2 SDRAM Rev. C 1/16 EN

Description

Embedded LPDDR2 SDRAM Rev. C 1/16 EN

Source title B8132B4PB-8D-F Datasheet(PDF) - Micron Technology

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