ATR2406_97 ATMEL | Alldatasheet
Document overview
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Technical content
Features
Fully Integrated Low IF Receiver Fully Integrated GFSK Modulator for 72, 144, 288, 576 and 1152 kBit/s High Sensitivity of Typically -93 dBm Due to Integrated LNA High Output Power of Typically +4 dBm Multi-channel Operation – 95 Channels – Support Frequency Hopping (ETSI) and Digital Modulation (FCC) Supply-voltage Range 2.9 V to 3.6 V (Unregulated) Auxiliary-voltage Regulator on Chip (3.2 V to 4.6 V) Low Current Consumption Few Low Cost External Components Integrated Ramp-signal Generator and Power Control for an Additional Power Amplifier Low Profile Lead-free Plastic Package QFN32 (5 × 5 × 0.9 mm)
Applications
Hightech Multi-user Toys Wireless Game Controllers Telemetry Wireless Audio/Video Electronic Point of Sales Wireless Head Set FCC CFR47, Part 15, ETSI EN 300 328 and ARIB STD-T-66 Compliant Radio Links Electrostatic sensitive device. Observe precautions for handling.
Description
The ATR2406 is a single chip RF-transceiver intended for applications in the 2.4 GHz ISM band. The QFN32 packaged IC is a complete transceiver including image rejec- tion mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, power-ramping generator for external power amplifier, integrated synthesizer, and a fully integrated VCO and TX filter. No mechanical adjustment is necessary in production. The RF-transceiver offers a clock recovery function on-chip. Low IF 2.4 GHz ISM Transceiver ATR2406 Preliminary
2 ATR2406 [Preliminary]
Figure 1. Block Diagram Figure 2. Pinning QFN32 - 5 × 5
ATR2406 [Preliminary] 4779F–ISM–09/04 Pin Description Pin Symbol Function
1 PU_REG Power-up input for auxiliary regulator
2 REF_CLK Reference frequency input
3 RSSI Received signal strength indicator output
4 VS_IFD Digital supply voltage
5 VS_IFA Analog supply voltage for IF circuits
6 RX-CLOCK RX-CLOCK, if RX mode with clock recovery is active
7 IC Internal connected, do not connect on PCB
8 IREF External resistor for band-gap reference
9 REG_CTRL Auxiliary voltage regulator control output
10 VREG Auxiliary voltage regulator output
11 VS_REG Auxiliary voltage regulator supply voltage
12 REG_DEC Decoupling pin for VCO_REG
13 VREG_VCO VCO voltage regulator
14 VTUNE VCO tuning voltage input
15 CP Charge-pump output
16 VS_SYN Synchronous supply voltage
17 VS_TRX Transmitter receiver supply voltage
18 RX_IN2 Differential receiver input 2
19 RX_IN1 Differential receiver input 1
20 TX_OUT TX driver amplifier output
21 RAMP_OUT Ramp generator output for PA power ramping
22 IC Internal connected, do not connect on PCB
23 IC Internal connected, do not connect on PCB
24 RX_ON RX control input
25 TX_ON TX control input
26 nOLE Open loop enable input
27 PU_TRX RX/TX/PLL/VCO power-up input
28 RX_DATA RX data output
29 TX_DATA TX data input
30 CLOCK 3-wire-bus: Clock input
31 DATA 3-wire-bus: Data input
32 ENABLE 3-wire-bus: Enable input
4 ATR2406 [Preliminary]
4779F–ISM–09/04 Functional Description Receiver The RF signal at RF_IN is differently fed through the LNA to the image rejection mixer IR_MIXER driving the integrated LowIF bandpass filter. The IF frequency is 864 kHz.The limiting IF_AMP with an integrated RSSI function feeds the signal to the digital demodulator DEMOD. No tuning is required. Datasling is handled internally. Clock Recovery For 1152 kBit/s data rate the receiver has a clock recovery function on-chip. The receiver includes a clock recovery circuit which regenerates the clock out of the received data. The advantage is that this recovered clock is synchronous to the clock of the transmitting device (and thus to the transmitted data) which allows to reduce the load of the processing microcontroller significantly. The falling edge of the clock gives the optimal sampling position for the RX_Data signal so at this event the data must be sampled by the microcontroller. The recovered clock is available at pin 6. Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed to the internal preamplifier PA. This preamplifier supplies typically +4 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled inter- nally so that spurious requirements are fulfilled. Synthesizer The IR_MIXER, the PA and the programmable counter PC are driven by the fully inte- grated VCO, using on-chip inductors and varactors. The output signal is frequency divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD PD = 1.728 MHz). Open loop modulation is supported. Power Supply An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided.
ATR2406 [Preliminary] 4779F–ISM–09/04 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage auxiliary regulator V S -0.3 +4.7 V Supply voltage V S -0.3 +3.6 V Control voltages V contr -0.3 V S V Storage temperature T stg -40 +125 °C Input RF level P RF +10 dBm ESD protection VESD_anal TBD V VESD_dig TBD V Operating Range Parameters Symbol Min. Max. Unit Supply voltage V S 2.9 3.6 V Auxiliary regulator supply voltage V S_BA TT 3.2 4.6 V Temperature ambient T amb -10 +60 °C Input frequency range f RX 2400 2483 MHz
Electrical Characteristics
VS = 3.6 V with AUX regulator, Tamb = 25°C, unless otherwise specified No. Parameters Test Conditions Symbol Min. Typ. Max. Unit
1 Supply
1.1 Supply voltage With AUX regulator V S 3.2 3.6 4.6 V 1.2 Supply voltage w/o AUX regulator V S 2.9 3.0 3.6 V
1.3 RX supply current CW-mode I S 31 mA
1.4 TX supply current CW-mode I S 16 mA
1.5 Synthesizer supply current I S 26 mA
1.6 Supply current in power-down
PU_TRX = 0; PU_REG = 0 IS < 1 µA
1.7 Supply current in power-down
PU_TRX = 0; PU_REG = 0 IS < 1 µA
2 Voltage Regulator
2.1 AUX regulator VREG 3.0 V 2.2 VCO regulator VREG_VCO 2.7 V 3T r a n s m i t t e r P a r t
3.1 TX data rate 72/144/288/576/1152 kBit/s
3.2 Output power Over full temperature range, from
2400 MHz to 2483 MHz
(1) PTX 0 4 dBm Notes: 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. F or further information refer to Application Note.
6 ATR2406 [Preliminary]
4779F–ISM–09/04 3.3 TX data filter clock 6 taps in filter f TXFCLK 6.912 MHz
3.4 Frequency deviation GFFM_nom ±400 kHz
3.5 Frequency deviation scaling GFFM = GFFM_nom × GFCS
(see bus protocol D9 to D11) GFCS 60 130 %
3.6 Frequency drift during a slot ∆fo (drift) ±10 kHz
3.7 Harmonics 2nd Harmonic 3rd Harmonic BW = 100 kHz(1) -40.5 -46 dBc dBc 3.8 Spurious Emission 30 - 1000 MHz 1 - 12.75 GHz 1.8 - 1.9 GHz 5.15 - 5.3 GHz BW = 100 kHz(1) -40.5 -48 -70 -70 dBm dBm dBm dBm
4 Receiver Part
4.1 Sensitivity At input for BER ≤ 10-3
at 1152 kBit/s(1) -93 dBm
4.2 Third order input intercept point IIP3 -15 dBm
4.3 Intermodulation rejection
BER < 10-3, wanted at -83 dBm, level of interferers in channels N + 2 and N + 4 (1) IM3 32 dBc
4.4 Co-channel rejection BER < 10 -3, wanted at -76 dBm(1) RCO -11 dBc
4.5 Adjacent channel rejection
BER < 10-3, wanted at -76 dBm, adjacent level referred to wanted channel level(1) ±1.728 MHz Ri (N-1) 4d B c
4.6 Bi-adjacent channel rejection
BER < 10-3, wanted at -76 dBm, bi- adjacent level referred to wanted channel level(1) ±3.456 MHz Ri (N - 2) 30 dBc
4.7 Rejection with ≥ 3 channels
BER < 10-3, wanted at -76 dBm, n ≥ 3 adjacent level referred to wanted channel level(1) ≥ ±5.128 MHz Ri (n ≥ 3) 40 dBc
4.8 Out of band rejection > 6 MHz BER < 10-3, wanted at -83 dBm at
2.45 GHz(1) Bldf>6MHz 38 dBc
4.9 Out of band rejection
2300 MHz to 2394 MHz
2506 MHz to 2600 GHz
BER < 10-3, wanted at -83 dBm at
2.45 GHz(1) Blnear 47 dBc
4.10 Out of band rejection
30 MHz to 2300 MHz
2600 MHz to 6 GHz
BER < 10-3, wanted at -83 dBm at
2.45 GHz(1) Blfar 57 dBc
5 RSSI Part
5.1 Maximum RSSI output voltage Under high RX input signal level V RSSImax 2.1 V Electrical Characteristics (Continued) VS = 3.6 V with AUX regulator, Tamb = 25°C, unless otherwise specified No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Notes: 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. F or further information refer to Application Note.
ATR2406 [Preliminary] 4779F–ISM–09/04
5.2 RSSI output voltage, monotonic
over range -96 dBm to -36 dBm with -33 dBm at RF input with -96 dBm at RF input VRSSI 1.9 0.3 V V
5.3 Wake-up time from power-up
signal to correct RSSI output Ton 40 µs 6V C O
6.1 Oscillator frequency Over full temperature range (1) 2400 2483 MHz
6.2 Frequency control voltage range V VTUNE 0.5 V CC - 0.5 V
6.3 VCO tuning input gain G VCO 150 MHz/V
7 Synthesizer
7.1 External reference input
D7 = 0 D7 = 1 REF_CLK 10.368 13.824 MHz MHz
7.2 Sinusoidal input signal level
(RMS value) AC coupled sinewave REF_CLK 250 500 mV RMS
7.3 Scaling factor prescaler S PSC 32/33
7.4 Scaling factor main counter S MC 86/87/88/89
7.5 Scaling factor swallow counter S SC 03 1
8 Phase Detector
8.1 Phase detector comparison
9 Charge-pump Output
9.1 Charge-pump output current V CP = 1/2 VCC ICP ±2 mA
9.2 Leakage current V CP = 1/2 VCC IL ±100 pA
10 Timing Conditions (1)(2)
10.1 Transmit to Receive time TX → RX-time 100 µs
10.2 Receive to Transmit time RX → TX-time 100 µs
10.3 Channel switch time CS-time 350 µs
10.4 Power down to Transmit PD → TR-time 450 µs
10.5 Power down to Receive PD → RX-time 400 µs
10.6 Programming register PRR-time 3 µs
10.7 PLL settling time PLL set-time 350 µs
11 Interface Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE
11.1 HIGH-level input voltage Logic 1 V
IH 1.4 3.4 V 11.2 LOW-level input voltage Logic 0 V IL -0.3 +0.4 V 11.3 HIGH-level output voltage Logic 1 V OH 3.4 V
11.4 LOW-level output voltage Logic 0 V OL 0V
11.5 Input bias current Logic 1 or logic 0 I bias -5 +5 µA
11.6 3-wire bus clock frequency f CLKmax 10 MHz Electrical Characteristics (Continued) VS = 3.6 V with AUX regulator, Tamb = 25°C, unless otherwise specified No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Notes: 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. F or further information refer to Application Note.
8 ATR2406 [Preliminary]
Figure 3. PLL Principle
13.824 MHz 1
010.368 MHz
The following table shows the LO frequencies for RX and TX in the 2.4 GHz ISM band. There are 95 channels available. TX Register Setting The following 16-bit word has to be programmed for TX. Table 1. LO Frequencies
01 P A G F C S 1 R C M C S C
Table 2. Output Power Settings with Bits D12 - D13
10 ATR2406 [Preliminary]
ery function is implemented. Must be used for data rates below 1.152 Mbit. Note: X values are not relevant and can be set to 0 or 1. Recommended for 1.152 Mbit data rate. signal samples the data signal. Note: X values are not relevant and can be set to 0 or 1. Table 3. PLL Settings with the Reference Counter Bit D7
bits are only relevant in TX mode. The VRAMP voltage is used to control the output power of an external power amplifier. The voltage ramp is started with the TX_ON signal. These bits are only relevant in TX mode. Table 4. PLL Settings with the Main Counter Bits D5 - D6 Table 5. PLL Settings with the Swallow Counter Bits D0 - D4 Table 6. GFCS Adjustment with Bits D9 - D11
12 ATR2406 [Preliminary]
Serial Programming Bus The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE). enable signal has returned to high condition, the programmed information is active. arrived during enable low condition. Figure 4. 3-wire Bus Protocol Timing Diagram Table 7. Control Signals – Functions Table 8. 3-wire Bus Protocol Table
Figure 5. Complete TX and RX Timing Diagram
14 ATR2406 [Preliminary]
Figure 6. Typical RSSI Value versus Input Power Table 9. Description of the Conditions/States ATR2406 is switched off and the supply current is lower than 1 µA. ATR2406 is powered up by toggling PU_REG and PU_RTX to high. Via the tree-wire-interface the internal register of ATR2406 is programmed. settling time of 350 µs so that the VCO-Frequency is stable. also derived, i.e., the gaussian filter circuitry and TX_DATA sampling. well as recovered clock are available.
application is shown in Figure 7. Figure 7. Application Circuit
12 C17
17 C14
19 C10
16 ATR2406 [Preliminary]
Figure 8. PCB-layout ATR2406-DEV-BOARD
Table 10. Bill of Material Table 11. Parts Count Bill of Material
18 ATR2406 [Preliminary]
4779F–ISM–09/04
Package Information
Ordering Information
Extended Type Number Package Remarks MOQ ATR2406-PNSG QFN32 - 5x5 Tube, Sampling; Pb-free 600 ATR2406-PNQG QFN32 - 5x5 Taped and reeled; Pb-free 6000 ATR2406-DEV-BOARD - RF-module 1 ATR2406-DEV-KIT - Complete Evaluation-kit 1
Figure 9. Recommenced Footprint/Landing Pattern Table 1. Recommended Footprint/Landing Pattern Signs
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