ATV750 ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • Third Generation Programmable Logic Structure – High-Density Replacement for Discrete Logic
  • High-Speed — Plus a New, Low-Power Version
  • Increased Logic Flexibility – 42 Inputs and 20 Sum Terms
  • Flexible Output Logic – 20 Flip-Flops - 10 Extra – All Can Be Individually Buried or 10 Output Directly – Each has Individual Asynchronous Reset and Clock Terms
  • Multiple Feedback Paths Provide for Buried State Machines and I/O Bus Compatibility
  • Proven and Reliable High-Speed CMOS EPROM Process – 2000V ESD Protection – 200 mA Latchup Immunity
  • Reprogrammable – Tested 100% for Programmability
  • 24-pin, 300-mil Dual-In-line and 28-Lead Surface Mount Packages Logic Diagram

Description

The ATV750(L) is 100% more powerful than most other programmable logic devices in 24-pin packages. Increased product terms, sum terms, and flip-flops translate into more usable gates. Each of the ATV750(L)’s twenty-two logic pins can be used as an input. Ten of these can be used as input, output, or bi-directional I/O pins. All twenty flip-flops can be fed back into the array independently. This flexibility allows burying all of the sum terms and flip-flops. There are 171 product terms available. A variable format is used to assign between four and eight product terms per sum term. There are two sum terms per output, pro- viding added flexibility. Rev. 0024E–05/98 Pin Configurations Pin Name Function IN Logic Inputs I/O Bidirectional Buffers * No Internal Connection VCC +5V Supply (continued) High Density UV Erasable Programmable Logic Device ATV750 ATV750L DIP/SOIC IN IN IN IN IN IN IN IN IN IN IN GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN PLCC/LCC (Top View) IN IN IN IN IN IN I/O I/O I/O I/O I/O I/O IN IN GND IN I/O I/O IN IN IN VCC I/O I/O

The ATV750(L) has more flip-flops available than other PLDs in this density range. Complex state machines are easily implemented. Product terms are available providing asynchronous resets, flip-flop clocks, and output enables. One reset and one clock term are provided per flip-flop, with one enable term per output. One product term provides a global syn- chronous preset. Register preload simplifies testing. The device has an internal power up clear function. Logic Options Output Options Absolute Maximum Ratings Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V DC, which may under- shoot to -2.0V for pulses of less than 20 ns. Max- imum output pin voltage is Vcc + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. Voltage on Any Pin with (1) Voltage on Input Pins with Respect to Ground Programming Voltage with (1) Combined Terms Separate Terms Combined Terms Separate Terms

Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. DC and AC Operating Conditions ATV750-20 ATV750/750L-25 Operating T emperature (Case) Com. 0°C - 70°C 0°C - 70°C V CC Power Supply 5V ± 10% 5V ± 10% DC Characteristics Symbol Parameter Condition Min Typ Max Units ILI Input Load Current VIN = -0.1V to VCC + 1V 10 µA ILO Output Leakage Current VOUT = -0.1V to VCC + 0.1V 10 µA ICC Power Supply Current VCC = MAX, VIN = GND, Outputs Open AT V 7 5 0 Com. 120 mA Ind.,Mil. 140 mA A TV750L Com. 1.0 12 mA Ind.,Mil. 1.0 15 mA IOS (1) Output Short Circuit Current VOUT = 0.5V -120 mA VIL Input Low Voltage -0.6 0.8 V VIH Input High Voltage 2.0 V CC + 0.75 V VOL Output Low Voltage VIN = VIH or VIL, VCC = MIN IOL = 12 mA Com.,Ind. 0.5 V IOL = 8 mA Mil. 0.5 V IOL = 24 mA, Com. 1.0 V VOH Output High Voltage VIN = VIH or VIL, VCC = MIN IOH = -100 µAV CC - 0.3 V IOH = -4.0 mA 2.4 V

AC Waveforms (1)

tR , tF < 5 ns (10% to 90%) Output Test Loads AC Characteristics Symbol Parameter ATV750-20 ATV750/750L-25 UnitsMin Max Min Max tPD Input or Feedback to Non-Registered Output 20 25 ns tEA Input to Output Enable 20 25 ns tER Input to Output Disable 20 25 ns tCO Clock to Output 20 22 ns tCF Clock to Feedback 5 10 5 10 ns tS Input Setup Time 10 12 ns tSF Feedback Setup Time 5 7 ns tH Hold Time 5 5 ns tP Clock Period 18 22 ns tW Clock Width 8 10 ns FMAX Maximum Frequency 55 45 MHz tAW Asynchronous Reset Width 15 20 ns tAR Asynchronous Reset Recovery Time 15 20 ns tAP Asynchronous Reset to Registered Output Reset 20 25 ns tSP Setup Time, Synchronous Preset 12 15 ns

Functional Logic Diagram ATV750, Upper Half

Functional Logic Diagram ATV750, Lower Half

Preload of Registered Outputs The ATV750's registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A V IH level on the I/O pin will force the register high; a VIL will force it low, independent of the output polarity. The pre- load state is entered by placing an 10.5V to 11.5V signal on pin 8 on DIPs, and pin 10 on SMPs. When the clock term is pulsed high, the data on the I/O pin is placed into the regis- ter chosen by the Select Pin. Power-Up Reset The registers in the ATV750(L) are designed to reset dur- ing power up. At a point delayed slightly from VCC crossing 3.8V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. How- ever, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the fol- lowing conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock term high, and 3. The signals from which the clock is derived must remain stable during tPR . Note: 1. T ypical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Level forced on registered output pin during PRELOAD cycle Select Pin State Register #1 state after cycle Register#2 State after cycle VIH Low High X VIL Low Low X VIH High X High VIL High X Low Parameter Description Min Typ Max Units tPR Power-Up Reset Time 600 1000 ns Pin Capacitance (f = 1 MHz, T = 25°C)(1) Typ Max Units Conditions C IN 58 p F VIN = 0V C OUT 68 p F VOUT = 0V

Using the ATV750's Many Advanced Features The ATV750's flexibility puts more usable gates in 24-pins than other PLDs. The ATV750(L) starts with an architecture similar to the popular AT22V10, and adds several features:

  • Asynchronous Clocks - Each of the flip-flops in the A TV750(L) has a dedicated product term driving the clock. The user is no longer constrained to using one clock for all the registers. Buried state machines, counters, and registers can all coexist in one device, while running on separate clocks. The A TV750(L) clock period matches that of similar synchronous devices.
  • A Full Bank of 10 More Registers - The A TV750(L) provides two flip-flops for each output macrocell - a total of 20. Each register has its own clock and reset product terms, as well as its own SUM term.
  • Independent I/O Pin and Feedback Paths - Each I/O pin on the A TV750(L) has a dedicated input path. Each of the 20 registers has individual feedback terms into the array. This feature, combined with individual product terms for each I/O's output enable, facilitates designs using bi-directional I/O buses.
  • Combinable Sum Terms - Each output macrocell’s two SUM terms can be combined in an OR gate before the output or the register. This provides up to 16 product terms per output or flip- flop. This architecture increases the number of usable gates available. Programming Software Support Software which is capable of transforming Boolean equa- tions, state machine descriptions and truth tables into JEDEC files for the ATV750(L) is available from several PLD software vendors. Please refer to the Software Sup- port Information table in the Programmable Logic Develop- ment Tools section for more information. Synchronous Preset and Asynchronous Reset One synchronous preset line is provided for all 20 registers in the ATV750(L). The appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching waveform diagram. An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and slave halves of the flip- flops are reset when the input signals received combine so as to force the internal resets high. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATV750(L) fuse patterns. Once programmed, the output buffers will remain in a high impedance state during verify. The security fuse should be programmed last, as its effect is immediate. Erasure Characteristics The entire memory array of an ATV750(L) is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 min- utes exposure using 12,000 µ W/cm 2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W
  • sec/cm2. To prevent unintentional erasure, an opaque label is recom- mended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. Atmel CMOS PLDs Atmel’s Programmable Logic Devices utilize an advanced 1.5-micron CMOS EPROM technology. This technology's state of the art features are the optimum combination for PLDs:
  • CMOS technology provides high speed, low power, and high noise immunity.
  • EPROM technology is the most cost effective method for producing PLDs - surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability.
  • EPROM reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible PLDs.
  • Atmel's EPROM process has proven extremely reliable in the volume production of a full line of advanced EPROM memory products, from 64K to one-megabit devices.

Ordering Information

(ns) tCO (ns) fMAX (MHz) Ordering Code Package Operation Range 20 20 55 A TV750-20JC A TV750-20PC A TV750-20SC 28J 24P3 24S Commercial (0°C to 70°C) A TV750-20JI A TV750-20PI A TV750-20SI 28J 24P3 24S Industrial (-40°C to 85°C) A TV750-20DM A TV750-20GM A TV750-20LM A TV750-20NM 24DW3 24D3 28LW 28L Military (-55°C to 125°C) A TV750-20DM/883 A TV750-20GM/883 A TV750-20LM/883 A TV750-20NM/883 24DW3 24D3 28LW 28L Military/883C (-55°C to 125°C) 25 22 45 A TV750-25JC A TV750-25PC A TV750-25SC 28J 24P3 24S Commercial (0°C to 70°C) A TV750-25JI A TV750-25PI A TV750-25SI 28J 24P3 24S Industrial (-40°C to 85°C) A TV750-25DM A TV750-25GM A TV750-25LM A TV750-25NM 24DW3 24D3 28LW 28L Military (-55°C to 125°C) A TV750-25DM/883 A TV750-25GM/883 A TV750-25LM/883 A TV750-25NM/883 24DW3 24D3 28LW 28L Military/883C (-55°C to 125°C) Class B, Fully Compliant 20 20 55 5962-88726 04 LA 5962-88726 04 3X 5962-94524 03 MLA 5962-94524 03 M3X 24DW3 28LW 24D3 28L Military/883C (-55°C to 125°C) Class B, Fully Compliant 25 22 45 5962-88726 03 LA 5962-88726 03 3X 5962-94524 02 MLA 5962-94524 02 M3X 24DW3 28LW 24D3 28L Military/883C (-55°C to 125°C) Class B, Fully Compliant

(0°C to 70°C) A TV750L-25JI A TV750L-25PI A TV750L-25SI 28J 24P3 24S Industrial (-40°C to 85°C) A TV750L-25DM A TV750L-25GM A TV750L-25LM A TV750L-25NM 24DW3 24D3 28LW 28L Military (-55°C to 125°C) A TV750L-25DM/883 A TV750L-25GM/883 A TV750L-25LM/883 A TV750L-25NM/883 24DW3 24D3 28LW 28L Military/883C (-55°C to 125°C) Class B, Fully Compliant 25 22 45 5962-88726 07 LX 5962-88726 07 3X 5962-94524 05 MLA 5962-94524 05 M3X 24DW3 28LW 24D3 28L Military/883C (-55°C to 125°C) Class B, Fully Compliant Ordering Information (Continued) tPD (ns) tCO (ns) fMAX (MHz) Ordering Code Package Operation Range Package Type 24DW3 24-Lead, 0.300" Wide, Windowed, Ceramic Dual In-line Package (Cerdip) 24D3 24-Lead, 0.300" Wide, Non-Windowed (OTP) Ceramic Dual In-line Package (Cerdip) 28J 28-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 28LW 28-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) 28L 28-Pad, Non-Windowed, Ceramic Leadless Chip Carrier OTP (LCC) 24P3 24-Lead, 0.300" Wide, Plastic Dual In-line Package OTP (PDIP) 24S 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC)

1.28(32.5) 1.24(31.5) PIN .310(7.87) .285(7.24) .098(2.49) MAX .005(.127) MIN .060(1.52) .015(.381) .023(.584) .045(1.14) .325(8.25) .300(7.62)

15 REF

.400(10.2) MAX .015(.381) .008(.203) .110(2.79) .090(2.29) .200(5.08) .125(3.18) SEATING PLANE .200(5.08) MAX 1.100(27.94) REF .045(1.14) X 45°PIN NO. 1 IDENTIFY .032(.813) .026(.660) .050(1.27) TYP .300(7.62) REF SQ .012(.305) .008(.203) .021(.533) .013(.330) .430(10.9) .390(9.91)SQ .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .456(11.6) .450(11.4) .495(12.6) .485(12.3) SQ SQ 24DW3, 24-Lead, 0.300" Wide, Windowed, Ceramic Dual In-line Package (Cerdip) Dimensions in Inches and (Millimeters) 24D3, 24-Lead, 0.300" Wide, Non-Windowed (OTP) Ceramic Dual In-line Package (Cerdip) Dimensions in Inches and (Millimeters) 28J, 28-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) Dimensions in Inches and (Millimeters) 28LW, 28-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters)

1.27(32.3) 1.25(31.7) PIN .266(6.76) .250(6.35) .090(2.29) MAX .005(.127) MIN .070(1.78) .020(.508) .023(.584) .014(.356) .065(1.65) .040(1.02) .325(8.26) .300(7.62) .400(10.2) MAX .012(.305) .008(.203) .110(2.79) .090(2.29) .151(3.84) .125(3.18) SEATING PLANE .200(5.06) MAX 1.100(27.94) REF .020(.508) .013(.330) .299(7.60) .291(7.39) .420(10.7) .393(9.98) .105(2.67) .092(2.34) .050(1.27) BSC .616(15.6) .598(15.2) .012(.305) .003(.076) .013(.330) .009(.229) .050(1.27) .015(.381)8

0 REF

28L, 28-Pad, Non-Windowed, Ceramic Leadless Chip Carrier OTP (LCC) Dimensions in Inches and (Millimeters) 24P3, 24-Lead, 0.300" Wide, Plastic Dual Inline Package OTP (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 AF 24S, 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC) Dimensions in Inches and (Millimeters)