ATV750B-10DM/883

ATV750B ATMEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

• Advanced, High-Speed Programmable Logic Device-Superset of 22V10 – Improved Performance - 7.5 ns tPD, 95 MHz External Operation – Enhanced Logic Flexibility – Backward Compatible with ATV750/L Software and Hardware
• New Flip-Flop Features – D- or T -Type – Product Term or Direct Input Pin Clocking
• High-Speed Erasable Programmable Logic Devices – 7.5 ns Maximum Pin-to-Pin Delay
• Highest Density Programmable Logic Available in a 24-Pin Package
• Increased Logic Flexibility – 42 Array Inputs, 20 Sum Terms and 20 Flip-Flops
• Enhanced Output Logic Flexibility – All 20 Flip-Flops Feed Back Internally – 10 Flip-Flops are Also Available as Outputs
• Full Military, Commercial and Industrial Temperature Ranges Logic Diagram

Description

The ATV750Bs are twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance. Device I CC , Stand-By A TV750B 125 mA A TV750BL 15 mA Rev. 0301D–05/98 High-Speed UV-Erasable Programmable Logic Device ATV750B Pin Configurations Pin Name Function CLK Clock IN Logic Inputs I/O Bidirectional Buffers * No Internal Connection V CC +5V Supply DIP/SOIC PLCC/LCC Top View (continued)

Each of the ATV750B’s 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bi- directional I/O pins. Each flip-flop is individually config- urable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. A variable for- mat is used to assign between four to eight product terms per sum term. There are two sum terms per output, provid- ing added flexibility. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individu- ally configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flip- flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power up. The ATV750BL is a low power device with speeds as fast as 15 ns. The ATV750BL provides the optimum low power PLD solution, with full CMOS output levels. This device sig- nificantly reduces total system power, thereby allowing bat- tery-powered operation. Logic Options Combinatorial Output Registered Output Abosute Maximum Rating* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V DC which may under- shoot to -2.0V for pulses of less than 20 ns.Maxi- mum output pin voltage is V CC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns. Voltage on Any Pin with (1) Voltage on Input Pins with Respect to Ground (1) Programming Voltage with Combined Terms Separate Terms Combined Terms Separate Terms

Note: 1. See ordering information for valid speed and temperature combination. DC and AC Operating Conditions(1) Commercial -7, -10, -15 Commercial -25 Industrial Military Operating T emperature (Case) 0°C - 70°C 0°C - 70°C -40°C - 85°C -55°C - 125°C V CC Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10% SELECT LOGIC TO CELLCLOCK PRODUCT TERM CLK CKi CKMUX PIN

Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. Input Test Waveforms and Measurement Levels tR , tF < 3 ns (10% to 90%) Output Test Load DC Characteristics Symbol Parameter Condition Min Typ Max Units ILI Input Load Current VIN = -0.1V to VCC + 1V 10 µA ILO Output Leakage Current VOUT = -0.1V to VCC + 0.1V 10 µA ICC Power Supply Current, Standby VCC = MAX, VIN = MAX, Outputs Open B-7, -10 Com. 125 180 mA Ind.,Mil. 125 190 mA B-15, -25 Com. 125 180 mA Ind.,Mil. 125 190 mA BL-15 Com. 15 30 mA Ind.,Mil. 15 30 mA IOS (1) Output Short Circuit Current VOUT = 0.5V -120 mA VIL Input Low Voltage 4.5 ≤ VCC ≤ 5.5V -0.6 0.8 V VIH Input High Voltage 2.0 V CC + 0.75 V VOL Output Low Voltage VIN = VIH or VIL, VCC = MIN IOL = 16 mA Com.,Ind. 0.5 V IOL = 12 mA Mil. 0.5 V IOL = 24 mA Com. 0.8 V VOH Output High Voltage VIN = VIH or VIL, VCC = MIN IOH = -100 µAV CC - 0.3 V IOH = -4.0 mA 2.4 V

AC Waveforms, Product Term Clock(1) Note: 1. See ordering information for valid part numbers. AC Characteristics, Product Term Clock(1) Symbol Parameter -7 -10 B/BL-15 B/BL-25 UnitsMin Max Min Max Min Max Min Max tPD Input or Feedback to Non-Registered Output 7.5 10 15 25 ns tEA Input to Output Enable 7.5 10 15 25 ns tER Input to Output Disable 7.5 10 15 25 ns tCO Clock to Output 3 7.5 4 10 5 12 6 20 ns tCF Clock to Feedback 1 5 4 7.5 5 9 5 10 ns tS Input Setup Time 3 4 8/12 14 ns tSF Feedback Setup Time 3 4 7 7 ns tH Hold Time 1 2 5/7 5/7 ns tP Clock Period 7 11 14 17 ns tW Clock Width 3.5 5.5 7 8.5 ns FMAX External Feedback 1/(tS+tCO ) 95 71 50/41 29 MHz Internal Feedback 1/(tSF +tCF ) 125 86 62 58 MHz No Feedback 1/(tP) 142 90 71 58 MHz tAW Asynchronous Reset Width 5 10 15 20 ns tAR Asynchronous Reset Recovery Time 31 0 1 5 2 0 n s tAP Asynchronous Reset to Registered Output Reset 81 2 1 52 5 n s tSP Setup Time, Synchronous Preset 4 7 8 15 ns

AC Waveforms, Input Pin Clock(1) AC Characteristics, Input Pin Clock Symbol Parameter -7 -10 B/BL -15 B/BL -25 UnitsMin Max Min Max Min Max Min Max tPD Input or Feedback to Non-Registered Output 7.5 10 15 25 ns tEA Input to Output Enable 7.5 10 15 25 ns tER Input to Output Disable 7.5 10 15 25 ns tCOS Clock to Output 0 6.5 0 7 0 6.5 0 12 ns tCFS Clock to Feedback 0 3.5 0 5 0 5.5 0 7 ns tSS Input Setup Time 4 5 8/12.5 9/15 ns tSFS Feedback Setup Time 4 5 7 9 ns tHS Hold Time 0 0 0 0 ns tPS Clock Period 7 10 12 16 ns tWS Clock Width 3.5 5 6 8 ns FMAXS External Feedback 1/(tSS +tCOS ) 95 83 69/52 48/37 MHz Internal Feedback 1/(tSFS +tCFS ) 133 100 80 62 MHz No Feedback 1/(tPS ) 142 100 83 62 MHz tAW Asynchronous Reset Width 5 10 15 20 ns tARS Asynchronous Reset Recovery Time 51 0 1 5 2 5 n s tAP Asynchronous Reset to Registered Output Reset 81 0 1 5 2 5 n s tSPS Setup Time, Synchronous Preset 5 5/9 11 15 ns

Functional Logic Diagram ATV750B, Upper Half

Functional Logic Diagram ATV750B, Lower Half

Preload of Registered Outputs The ATV750B’s registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A V IH level on the I/O pin will force the register high; a VIL will force it low, independent of the output polar- ity. The PRELOAD state is entered by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock term is pulsed high, the data on the I/O pins is placed into the register chosen by the Select Pin. Power Up Reset The registers in the ATV750Bs are designed to reset during power up. At a point delayed slightly from VCC crossing VRST , all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. How- ever, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the fol- lowing conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock terms or pin high, and 3. The clock pin, or signals from which clock terms are derived, must remain stable during t PR . Level forced on registered output pin during PRELOAD cycle Select Pin State Register #0 State after cycle Register #1 State after cycle VIH Low High X VIL Low Low X VIH High X High VIL High X Low Parameter Description Typ Max Units tPR Power-Up Reset Time 600 1000 ns VRST Power-Up Reset Voltage 3.8 4.5 V Pin Capacitance f = 1 MHz, T = 25°C(1) Typ Max Units Conditions C IN 58 p F V IN = 0V C OUT 68 p F V OUT = 0V

Using the ATV750B’s Many Advanced The ATV750B’s advanced flexibility packs more usable gates into 24-pins than any other logic device. The ATV750Bs start with the popular 22V10 architecture, and add several enhanced features:

• Selectable D- and T -Type Registers - Each A TV750B flip-flop can be individually configured as either D- or T -type. Using the T -type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage.
• Selectable Asynchronous Clocks - Each of the A TV750B’s flip-flops may be clocked by its own clock product term or directly from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design.
• A Full Bank of Ten More Registers - The A TV750B provides two flip-flops per output logic cell for a total of 20. Each register has its own sum term, its own reset term and its own clock term.
• Independent I/O Pin and Feedback Paths - Each I/O pin on the A TV750B has a dedicated input path. Each of the 20 registers has its own feedback terms into the array as well. This feature, combined with individual product terms for each I/O’s output enable, facilitates true bi-directional I/O design. Programming Software Support As with all other Atmel PLDs, several third party develop- ment software products support the ATV750Bs. Several third party programmers support the ATV750B as well. Additionally, the ATV750B may be programmed to perform the ATV750/L’s functional subset (no T-type flip-flops or pin clocking) using the ATV750/L JEDEC file. In this case, the ATV750B becomes a direct replacement or speed upgrade for the ATV750/L. The ATV750/L programming algorithm is different from the ATV750B algorithm. Choose the appro- priate device in your programmer menu to ensure proper programming. Please refer to the Programmable Logic Development Tools section for a complete PLD software and programmer listing. Synchronous Preset and Asynchronous Reset One synchronous preset line is provided for all 20 registers in the ATV750B. The appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching waveform diagram. An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and slave halves of the flip- flops are reset when the input signals received force the internal resets high. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATV750B fuse patterns. Once the security fuse is programmed, all fuses will appear programmed during ver- ify. The security fuse should be programmed last, as its effect is immediate. Erasure Characteristics The entire memory array of an ATV750B is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 min- utes exposure using 12,000 µ W/cm 2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W
• sec/cm2. To prevent unintentional erasure, an opaque label is recom- mended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. Atmel CMOS PLDs The ATV750B utilizes an advanced 0.65-micron CMOS EPROM technology. This technology’s state of the art fea- tures are the optimum combination for PLDs:
• CMOS technology provides high speed, low power, and high noise immunity.
• EPROM technology is the most cost effective method for producing PLDs - surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability.
• EPROM reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible PLDs.

Ordering Information

(ns) tCOS (ns) Ext. fMAXS (MHz) Ordering Code Package Operation Range 7.5 6.5 95 A TV750B-7JC A TV750B-7PC 28J 24P3 Commercial (0°C to 70°C) 10 7 83 A TV750B-10JC A TV750B-10PC A TV750B-10SC 28J 24P3 24S Commercial (0°C to 70°C) A TV750B-10JI A TV750B-10PI A TV750B-10SI 28J 24P3 24S Industrial (-40°C to 85°C) A TV750B-10DM/883 A TV750B-10LM/883 24DW3 28LW Military/883C (-55°C to 125°C) Class B, Fully Compliant 15 10 58 A TV750B-15JC A TV750B-15PC A TV750B-15SC 28J 24P3 24S Commercial (0°C to 70°C) A TV750B-15JI A TV750B-15PI A TV750B-15SI 28J 24P3 24S Industrial (-40°C to 85°C) A TV750B-15DM/883 A TV750B-15LM/883 24DW3 28LW Military/883C (-55°C to 125°C) Class B, Fully Compliant 25 15 41 A TV750B-25JC A TV750B-25PC A TV750B-25SC 28J 24P3 24S Commercial (0°C to 70°C) A TV750B-25JI A TV750B-25PI A TV750B-25SI 28J 24P3 24S Industrial (-40°C to 85°C) 10 7 83 5962-88726 08 LA 5962-88726 08 3X 24DW3 28LW Military/883C (-55°C to 125°C) Class B, Fully Compliant 15 9 58 5962-88726 09 LA 5962-88726 09 3X 24DW3 28LW Military/883C (-55°C to 125°C) Class B, Fully Compliant

(ns) tCOS (ns) Ext. fMAXS (MHz) Ordering Code Package Operation Range 15 9 92 A TV750BL-15JC A TV750BL-15PC A TV750BL-15SC 28J 24P3 24S Commercial (0°C to 70°C) A TV750BL-15JI A TV750BL-15PI A TV750BL-15SI 28J 24P3 24S Industrial (-40°C to 85°C) A TV750BL-15DM/883 A TV750BL-15LM/883 24DW3 28LW Military/883C (-55°C to 125°C) Class B, Fully Compliant 25 15 37 A TV750BL-25JC A TV750BL-25PC A TV750BL-25SC 28J 24P3 24S Commercial (0°C to 70°C) A TV750BL-25JI A TV750BL-25PI A TV750BL-25SI 28J 24P3 24S Industrial (-40°C to 85°C) 15 9 92 5962-88726 11 LX 5962-88726 11 3X 24DW3 28LW Military/883C (-55°C to 125°C) Class B, Fully Compliant Package Type 24DW3 24-Lead, 0.300" Wide, Windowed, Ceramic Dual Inline Package (Cerdip) 28J 28-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 28LW 28-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) 24P3 24-Lead, 0.300" Wide, Plastic Dual Inline Package OTP (PDIP) 24S 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC)

.045(1.14) X 45°PIN NO. 1 IDENTIFY .032(.813) .026(.660) .050(1.27) TYP .300(7.62) REF SQ .012(.305) .008(.203) .021(.533) .013(.330) .430(10.9) .390(9.91)SQ .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .456(11.6) .450(11.4) .495(12.6) .485(12.3) SQ SQ *Controlling dimension: millimeters 1.27(32.3) 1.25(31.7) PIN .266(6.76) .250(6.35) .090(2.29) MAX .005(.127) MIN .070(1.78) .020(.508) .023(.584) .014(.356) .065(1.65) .040(1.02) .325(8.26) .300(7.62)

15 REF

.400(10.2) MAX .012(.305) .008(.203) .110(2.79) .090(2.29) .151(3.84) .125(3.18) SEATING PLANE .200(5.06) MAX 1.100(27.94) REF 24DW3 , 24-Lead, 0.300" Wide, WIndowed, Ceramic Dual Inline Package (Cerdip) Dimensions in Inches and (Millimeters) MIL-STD-1835 D-9 CONFIG A 28J, 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AB 28LW , 28-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters)* MIL-STD-1835 C-4 24P3, 24-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 AF

.020(.508) .013(.330) .299(7.60) .291(7.39) .420(10.7) .393(9.98) .105(2.67) .092(2.34) .050(1.27) BSC .616(15.6) .598(15.2) .012(.305) .003(.076) .013(.330) .009(.229) .050(1.27) .015(.381)8

0 REF

24S, 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) © Atmel Corporation 1998. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s T erms and Conditions located on the Company’s website. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel Headquarters, 2325 Orchard Parkway, San Jose, CA 95131, TEL (408) 441-0311, FAX (408) 487-2600 Atmel Colorado Springs, 1150 E. Cheyenne Mtn. Blvd., Colorado Springs, CO 80906, TEL (719) 576-3300, FAX (719) 540-1759 Atmel Rousset, Zone Industrielle, 13106 Rousset Cedex, France, TEL (33) 4 42 53 60 00, FAX (33) 4 42 53 60 01 Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. T erms and product names in this document may be trademarks of others. Printed on recycled paper. 0301D–05/98/xM