ATV5962-9324803MXX

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Document overview

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Technical content

Features

• Advanced Programmable Logic Device - High Gate Utilization
• Flexible Interconnect Architecture - Universal Routing
• Flexible Logic Cells - 128 Flip-Flops and 52 Latches
• Multiple Flip-Flop Types - Synchronous or Asynchronous Registers
• High Speed - 50 MHz Operation
• Complete Third Party Software Support No Placement, Routing or Layout Software Required
• Proven and Reliable High Speed CMOS EPROM Process

2000 V ESD Protection

• Reprogrammable - Tested 100% for Programmability
• Commercial, Industrial and Military Temperature Grades UNIVERSAL AND REGIONAL INTERCONNECT

52 INPUT

52 LOGIC CELLS

(104 FLIP-FLOPS)

24 BURIED CELLS

(24 FLIP-FLOPS) INPUT PINS I/O PINS Block Diagram Chip Carrier Pin Configuration Pin Name Function IN Logic and Clock Inputs Pins 2,32,36,66 Input/Register Clocks 1-4 Pins 1,34,35,68 Input/Latch Clocks 1-4 I/O Bidirectional Buffers VCC +5 V Supply High Density UV Erasable Programmable Logic Device

Description

The Atmel V5000 is an easy to use, high density programmable logic device. Its simple, regu- lar architecture translates into increased utilization and high performance. The ATV5000 has one programmable combinatorial logic array. This guarantees easy inter- connection of and uniform performance from all nodes. "Sum terms", which are easy to use groupings of AND-OR gates, provide combinatorial logic blocks. Sum terms can be wire- OR’d together to integrate larger logic blocks. To expand the levels of logic, buried sum terms feed back into the logic array. The 52 I/O pins can each be driven by a register or a sum term. Each I/O pin has an individually enabled input latch. All 128 registers are configurable as D- or T-types without using extra logic gates. Individual sum terms, asynchronous presets, resets and clocks give each flip-flop added flexibility. A direct "clock from pin" option guarantees synchronization and fast clock to output perform- ance. Standard, off-the-shelf third-party software tools and programmers support the ATV5000. This minimizes start-up investment and improves product support. I/Os GND I/Os VCC I/Os I/Os VCC I/Os GND I/Os 18 52 I/Os I/Os VCC GND ININ GND VCC INI/Os I/OsIN JLCC 0065B ATV5000/L 1-193

UNIVERSALBUS REGIONALTO ALL BUSQUADRANTS PINS I/O REGISTERCLOCKS REGIONAL INPUTS REGIONAL INPUTS UNIVERSAL PRODUCT UNIVERSALINPUTS TERMS REGIONAL PRODUCT TERMS INPUT PINS REGISTERCLOCKS TERMS PRODUCT REGIONAL TERMS PRODUCT UNIVERSAL INPUT/OUTPUT LOGIC CELLS (13TOTAL PERQUADRANT) BURIED LOGIC CELLS (6TOTAL PERQUADRANT) Quadrant Functional Logic Diagram ATV5000 Figure 1 Functional Logic Diagram Description There are 52 identical input/ouput logic cells and 24 identical buried logic cells in the ATV5000. Each I/O cell has two flip- flops, up to three sum terms, individual clock, reset, and preset terms per flip-flop, and one output enable term. Independent of output configuration, all flip-flops are always usable, and have at least four product term inputs each. Each I/O pin (52 total) signal or its latched version drives the logic array. There is one latch clock per quadrant. The ATV5000 has four identical quadrants (see Figure 2). The universal bus routes true and false signals from each of the 52 I/O pins to all four quadrants. Regional buses route each quad- rant’s flip-flop Q and Q locally. The eight input-only pins are available in all four regional buses. Each logic cell has a number of "regional" and "universal" prod- uct terms (see Figure 1). The I/O logic cells contain three sum terms, two flip-flops, and an I/O buffer. The buried logic cells each contain one flip-flop. In addition, in each buried logic cell the sum term can drive the regional bus. This allows for logic expansion. Serial register preload and observability simplify testing. All registers automatically clear at power up. Voltage on Any Pin with Voltage on Input Pins with Respect to Ground Programming Voltage with *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect de- vice reliability. Note: 1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V for pulses of less than 20 ns. Maximum output pin voltage is V CC +0.75 V dc which may overshoot to +7.0 V for pulses of less than 20 ns. Absolute Maximum Ratings* D.C. and A.C. Operating Range ATV5000-25 ATV5000/L-30 ATV5000/L-35 Operating Temperature (Case) Commercial Industrial Military 0oC - 70oC0 oC - 70oC- 5 5 oC - 125oC VCC Power Supply 5 V ± 5% 5 V ± 10% 5 V ± 10% 1-194 ATV5000/L

The ATV5000 has: four identical quadrants, 52 identical input/ output logic cells, and 24 identical buried logic cells. The uni- versal bus routes true and false signals from each of the 52 I/O pins to all four quadrants. Regional buses route each quadrant’s flip-flop Q and Q locally. The eight input-only pins are available in every regional bus. Each logic cell has a number of "regional" and "universal" prod- uct terms (see Figure 3). The I/O logic cells (Figures 7, 8, 9) contain three sum terms, two flip-flops, and an I/O buffer. Sum term B has five product terms - two universal and three regional. Sum terms A and C each have four product terms - one universal and three regional. Flip-flop Q1 has global asynchronous preset, reset, and clock product terms. Flip-flop Q2 has universal asyn- chronous reset and clock terms and a regional asynchronous pre- set term. There is one universal product term for the I/O pin out- put enable. The buried logic cells (Figure 4) each contain one flip-flop. The sum term has one universal product term and four regional prod- uct terms for a total of five. The flip-flop has universal asynchro- nous preset, reset, and clock terms. In addition, in each buried logic cell the sum term can be fed back into the regional bus instead of the flip-flop. This allows for logic expansion. Regional product terms have as inputs all quadrant flip-flop out- puts (or buried flip-flop inputs) and the eight dedicated input pins. Universal product terms have the same inputs plus the 52 I/O pins and their complements. Quadrant Clock Pin Assignments Quadrant Number Register Clock Pin Latch Clock Pin 12 1 23 2 3 4 33 6 3 5 46 6 6 8

13 I/O

(13 TOTAL) REGISTER CLOCK REGIONAL BUS UNIVERSAL BUS TO ALL QUADRANTS Q1/D1 BURIED LOGIC CELLS (6 TOTAL) OE UNIVERSAL BUS INPUTS REGIONAL BUS INPUTS UNIVERSAL PRODUCT TERMS REGIONAL PRODUCT TERMS ALL 8 INPUT ONLY PINS Quadrant Structure Figure 3 UNIVERSAL BUS REGIONAL BUS REGIONAL BUS

13 I/O CELLS

6 BURIED

2 INPUT PINS

1,2,32,34,35, 36,66,68 REGISTER CLOCK PIN 32 LATCH CLOCK PIN 34

13 I/O PINS

18,19,21-31 REGISTER CLOCK PIN 2 LATCH CLOCK PIN 1 4-15,17 REGIONAL BUS REGIONAL BUS 38-49,51 REGISTER CLOCK PIN 66 LATCH CLOCK PIN 68 52,53,55-65 ATV5000 Block Diagram Figure 2 ATV5000/L 1-195

Register A.C. Characteristics, Input Pin Clock ATV5000-25 ATV5000/L-30 ATV5000/L-35 Symbol Parameter Min Max Min Max Min Max Units tCOS Clock to Output 15 20 25 ns tCFS Clock to Feedback 0 9 0 12 0 15 ns tSIS Input Setup Time(1) 16 17 20 ns tSFS Feedback Setup Time(1) 11 13 15 ns tHS Hold Time 0 0 0 ns tWS Clock Width 10 12 15 ns tPS Clock Period 20 25 30 ns FMAXS Maximum Frequency (1/tPS ) 50 40 33 MHz tARS Asynchronous Reset/Preset Recovery Time 20 25 30 ns Note: 1. Add 3 ns for Universal Product Terms. Register A.C. Characteristics, Product Term Clock ATV5000-25 ATV5000/L-30 ATV5000/L-35 Symbol Parameter Min Max Min Max Min Max Units tCOA Clock to Output 25 30 35 ns tCFA Clock to Feedback 7 20 10 25 12 27 ns tSIA Input Setup Time(1) 10 12 15 ns tSFA Feedback Setup Time(1) 5 81 3 n s tHA Hold Time 8 10 12 ns tWA Clock Width 12 15 15 ns tPA Clock Period 25 33 40 ns FMAXA Maximum Frequency (1/tPA ) 4 03 02 5 M H z tARA Asynchronous Reset/Preset Recovery Time 15 20 25 ns Note: 1. Add 3 ns for Universal Product Terms. tCOA ASYNCHRONOUS INPUTSAND REGISTER tPA tWA tSIA OUTPUTS VALID OUTPUT I/O PINS REGISTERED tHA tARA INTERNAL VALIDFEEDBACKS tCFA CLOCK RESET/PRESET tSFA tWA OUTPUT VALID VALID tAP tAPF TERM tAW A.C. Waveforms (1) Product Term Clock tCOS ASYNCHRONOUS INPUTSAND REGISTER tPS tWS tSIS OUTPUTS VALID OUTPUT I/O PINS REGISTERED tHS tARS INTERNAL VALIDFEEDBACKS tCFS CLOCKPIN RESET/PRESET tSFS tWS OUTPUT VALID VALID tAP tAPF tAW A.C. Waveforms (1) Input Pin Clock 1-198 ATV5000/L

A.C. Characteristics ATV5000-25 ATV5000/L-30 ATV5000/L-35 Symbol Parameter Min Max Min Max Min Max Units tPD1 Input to Non-Registered Output(1) 25 30 35 ns tPD2 Feedback to Non-Registered Output(1) 20 25 30 ns tPD3 Input to Non-Registered Feedback(1) 20 25 30 ns tPD4 Feedback to Non-Registered Feedback(1) 15 18 22 ns tEA1 Input to Output Enable 30 35 40 ns tER1 Input to Output Disable 30 35 40 ns tEA2 Feedback to Output Enable 25 30 35 ns tER2 Feedback to Output Disable 25 30 35 ns tS Input Latch Setup Time 5 6 7 ns tH Input Latch Hold Time 5 5 5 ns tW Clock Width 10 12 12 ns tP Clock Period 20 25 30 ns FMAX Maximum Frequency (1/tP)5 0 4 0 3 3 M H z tAW Asynchronous Reset/Preset Width 15 20 20 ns tAP Asynchronous Reset/ Preset to Registered Output 30 35 40 ns tAPF Asynchronous Reset/ Preset to Registered Feedback 25 30 35 ns Note: 1. Add 3 ns for Universal Product Terms. OUTPUT PIN 5.0V CL= 35pF R1= 450 R2= 250 (280 MIL.) (580 MIL.) Output Test Load AC MEASUREMENT LEVEL AC DRIVING LEVELS 0.0V 3.0V 1.5V tR , tF < 5 ns (10% to 90%) Input Test Waveforms and Measurement Levels HIGH Z OUTPUT VALID INPUTS AND I/O PINS INPUT LATCH CLOCK tP tW tS HIGH ZREGISTERED COMBINATORIAL OUTPUTS tH tPD1 tW tER1 tEA1 INTERNAL FEEDBACKS tEA2tER2 VALID tPD3 tPD2 tPD4 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID A.C. Waveforms (1) ATV5000/L 1-199

Preload and Observability of Registers The ATV5000’s registers include circuity to load and unload them serially. This feature simplifies testing. Any state can be forced into the registers to control test sequencing, and all regis- ters may be observed, independent of being buried. A VIH level on the Data In pin will force the appropriate register high; a VIL will force it low, independent of the polarity or other configura- tion bit settings. The preload/observe state is entered by placing an 11-V to 14-V signal on pin 68 on the JLCC. When the clock (pin 1) is pulsed high, data (pin 2) is clocked serially through all registers in the device, as in the following table. All register contents are also clocked out of the device on Pin 65 in FIFO fashion. If ob- servability only is required, data out should be connected back to data in. If preload only is required, OE (pin 66) can be held high and data out (pin 65) will remain high impedance. Any user contemplating the use of register preload/obervability is encouraged to contact Atmel’s PLD applications department. Note: All register clock terms or pins must be low prior to en- tering the preload/observe state, and low prior to leaving the pre- load/observe state. Pin 1 must be low prior to entering the pre- load/observe state. Preload / Observe Register Scan Order Quadrant Pin Quadrant 1 Pin 4 5 6 ••• 15 17 DIN Q2 Q1 B23 Q2 Q1 Q2 Q1 ••• B18 Q2 Q1 Q2 Q1 (Quadrant 2) Quadrant 2 Pin 18 19 21 22 ••• 31 (Quadrant 1)→ Q2 Q1 Q2 Q1 B17 Q2 Q1 Q2 Q1 ••• B12 Q2 Q1 (Quadrant 3) Quadrant 3 Pin 38 39 40 ••• 49 51 (Quadrant 2)→ Q2 Q1 B11 Q2 Q1 Q2 Q1 ••• B6 Q2 Q1 Q2 Q1 (Quadrant 4) Quadrant 4 Pin 52 53 55 56 ••• 65 (Quadrant 3)→ Q2 Q1 Q2 Q1 B5 Q2 Q1 Q2 Q1 ••• B0 Q2 Q1 D OUT CLOCK VH PRELOAD tD tHP tD tSP DATA IN tEAP tERP OE DATA OUT tCOP tPR Pin 65 New Q1 Pin 65 New Q2 Pin Clock Clock Clock #128 Pin Pin Pin tWPPtWPP tDMIN = 100 ns tSPMIN = 50 ns tHPMIN = 50 ns tWPP MIN = 100 ns tPRMIN = 1000 ns tERPMAX = 100 ns tEAPMAX = 100 ns tCOP MAX = 100 ns 1-200 ATV5000/L

The ATV5000’s simple, regular architecture means that only simple logic compilers are required to configure the device. No layout or route and place are required. These software tools are readily available from companies such as Data I/O Corporation (ABEL  ), Logical Devices (CUPL ), MINC Inc. (PLDes- igner-XL ), and ISDATA (LOGiC ). The first step in designing a device as complex as the ATV5000 is to partition your design into manageable blocks. These blocks are then allocated proportionally to each of the four quadrants of the ATV5000. Random gates can be described either with boolean equations (a behavioral description) or with a schematic editor. Truth table logic and state machines are best described behaviorially and entered with a text editor. The design is then combined into one ASCII file, which is then submitted to the logic compiler. Compilation, logic reduction, simulation, JEDEC file creation and documentation are then completed by all of the popular compilers. Assignment of signals to pins or buried nodes as well as select- ing the various options of the ATV5000 (such as register clocks and input latches) can be done manually in the design data base file, or an automatic fitter may be used. A logic fitter assigns pins and nodes to make best use of the features in the ATV5000, and frees the designer from being re- quired to learn all of the features of a complex device such as the ATV5000. For further information on fitters for the ATV5000, contact Atmel’s PLD applications department. After correcting any syntax and logic errors discovered by the compiler, the JEDEC file is ready to download to an PLD pro- grammer. These are available from a number of manufacturers. Programmed devices are usually first tested in the programmer with your supplied test vectors. The next step is check out your "custom chip" in the target system. When this hardware debug step is complete, your system is ready to go— all in a matter of hours. ABEL  , CUPL , PLDesigner-XL and LOGiC may be trademarks of others. RANDOM GATES PARTITION DESIGN INTO MANAGABLE PIECES STATE MACHINES TRUTH TABLES SCHEMATIC EDITOR TEXT EDITOR DESIGN DATA BASE (ASCII FILE) TRANSFER JEDEC FILE AND PROGRAM COMPILE AND SIMULATE HARDWARE TEST SHIP IT! ERRORS? ERRORS? ERRORS? ERRORS? CORRECT Design Flow Diagram Power Up Reset The registers in the ATV5000 are designed to reset during power up. At a point delayed slightly from VCC crossing 3.8 V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the following conditions are required: 1) The VCC rise must be monotonic, 2) After reset occurs, all input and feedback setup times must be met before driving the clock term high, and 3) The signals from which the clock is derived must remain sta- ble during tPR . Parameter Description Min Typ Max Units tPR Power-Up Reset Time 600 1000 ns ATV5000/L 1-201

A single fuse is provided to prevent unauthorized copying of the ATV5000 fuse patterns. Once programmed, all outputs appear programmed during verify. The security fuse should be pro- grammed last (after verifying all other programmed bits), as its effect is immediate. The security fuse also inhibits preload and observability. Erasure Characteristics The entire memory array of an ATV5000 is erased after expo- sure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 minutes exposure using 12,000 µW/cm 2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W

• sec/cm2. To prevent unintentional erasure, an opaque la- bel is recommended to cover the clear window on any UV eras- able PLD which will be subjected to continuous fluorescent in- door lighting or sunlight. ATV5000 PLCC/PGA Pin Assignments PLCC Pin PGA Pin Name PLCC Pin PGA Pin Name PLCC Pin PGA Pin Name PLCC Pin PGA Pin Name

1 B6 IN 18 F2 I/O 35 K6 IN 52 F10 I/O

2 A6 IN 19 F1 I/O 36 L6 IN 53 F11 I/O

3 B5 VCC 20 G2 VCC 37 K7 VCC 54 E10 VCC

4 A5 I/O 21 G1 I/O 38 L7 I/O 55 E11 I/O

5 B4 I/O 22 H2 I/O 39 K8 I/O 56 D10 I/O

6 A4 I/O 23 H1 I/O 40 L8 I/O 57 D11 I/O

7 B3 I/O 24 J2 I/O 41 K9 I/O 58 C10 I/O

8 A3 I/O 25 J1 I/O 42 L9 I/O 59 C11 I/O

9 A2 I/O 26 K1 I/O 43 L10 I/O 60 B11 I/O

10 B2 I/O 27 K2 I/O 44 K10 I/O 61 B10 I/O

11 B1 I/O 28 L2 I/O 45 K11 I/O 62 A10 I/O

12 C2 I/O 29 K3 I/O 46 J10 I/O 63 B9 I/O

13 C1 I/O 30 L3 I/O 47 J11 I/O 64 A9 I/O

14 D2 I/O 31 K4 I/O 48 H10 I/O 65 B8 I/O

15 D1 I/O 32 L4 IN 49 H11 I/O 66 A8 IN

16 E2 GND 33 K5 GND 50 G10 GND 67 B7 GND

17 E1 I/O 34 L5 IN 51 G11 I/O 68 A7 IN

Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ Max Units Conditions C IN 68 p F V IN = 0 V C OUT 81 2 p F V OUT = 0 V Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 1-202 ATV5000/L

SUPPLY CURRENT vs. INPUT FREQUENCY ATV5000 (TA = 25C, VCC = 5V) 100 150 200 S U P P L Y C U R R E N T m A 0 3 6 9 1 21 51 82 1 INPUT FREQUENCY (MHz) SUPPLY CURRENT vs. INPUT FREQUENCY ATV5000L (TA = 25C, VCC = 5V) 100 150 200 S U P P L Y C U R R E N T m A 0 3 6 9 12 15 18 21 INPUT FREQUENCY (MHz) ATV5000/L 1-203

Ordering Information

(ns) tCOS (ns) fMAX (MHz) Ordering Code Package Operation Range 25 15 50 ATV5000-25JC 68J Commercial ATV5000-25KC 68KW (0 °C to 70°C) ATV5000-25UC 68UW 30 20 40 ATV5000-30JC 68J Commercial ATV5000-30KC 68KW (0 °C to 70°C) ATV5000-30UC 68UW ATV5000-30KI 68KW Industrial ATV5000-30UI 68UW (-40 °C to 85°C) ATV5000-30KM 68KW Military ATV5000-30UM 68UW (-55 °C to 125°C) ATV5000-30KM/883 68KW Military/883C ATV5000-30UM/883 68UW Class B, Fully Compliant (-55°C to 125°C) 35 25 33 ATV5000-35JC 68J Commercial ATV5000-35KC 68KW (0 °C to 70°C) ATV5000-35UC 68UW ATV5000-35KI 68KW Industrial ATV5000-35UI 68UW (-40 °C to 85°C) ATV5000-35KM 68KW Military ATV5000-35UM 68UW (-55 °C to 125°C) ATV5000-35KM/883 68KW Military/883C ATV5000-35UM/883 68UW Class B, Fully Compliant (-55°C to 125°C) 35 25 33 ATV5962-93248 02M XX 68KW Military/883C ATV5962-93248 02M YX 68UW Class B, Fully Compliant (-55°C to 125°C) tPD (ns) tCOS (ns) fMAX (MHz) Ordering Code Package Operation Range 30 20 40 ATV5000L-30JC 68J Commercial ATV5000L-30KC 68KW (0 °C to 70°C) ATV5000L-30UC 68UW 35 25 33 ATV5000L-35JC 68J Commercial ATV5000L-35KC 68KW (0 °C to 70°C) ATV5000L-35UC 68UW ATV5000L-35KI 68KW Industrial ATV5000L-35UI 68UW (-40 °C to 85°C) ATV5000L-35KM 68KW Military ATV5000L-35UM 68UW (-55 °C to 125°C) ATV5000L-35KM/883 68KW Military/883C ATV5000L-35UM/883 68UW Class B, Fully Compliant (-55°C to 125°C) 35 25 33 ATV5962-93248 03M XX 68KW Military/883C ATV5962-93248 08M YX 68UK Class B, Fully Compliant (-55°C to 125°C) 1-204 ATV5000/L

68J 68 Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 68KW 68 Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) 68UW 68 Pin, Windowed, Ceramic Pin Grid Array (PGA)