ATV2500B-15LM/883

ATV2500B ATMEL | Alldatasheet

Document overview

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Technical content

Features

• High Performance, High Density Programmable Logic Device – Typical 7 ns Pin-to-Pin Delay – Fully Connected Logic Array With 416 Product Terms
• Flexible Output Macrocell – 48 Flip-Flops - Two per Macrocell – 72 Sum Terms – All Flip-Flops, I/O Pins Feed In Independently – Achieves Over 80% Gate Utilization
• Enhanced Macrocell Configuration Selections – D- or T -Type Flip-Flops – Product Term or Direct Input Pin Clocking – Registered or Combinatorial Internal Feedback
• Several Power Saving Options
• Backward Compatible With ATV2500H/L Software
• Proven and Reliable High Speed UV EPROM Process
• Reprogrammable - Tested 100% for Programmability
• 40-Pin Dual-In-Line and 44-Pin Lead Surface Mount Packages Block Diagram Device I CC , Stand-By A TV2500B 110 mA A TV2500BQ 30 mA A TV2500BL 2 mA A TV2500BQL 2 mA Rev. 0249F–06/98 High-Speed High-Density UV Erasable Programmable Logic Device ATV2500B DIP LCC/PLCC CLK/IN IN IN I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 VCC I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 IN IN IN IN IN IN IN IN I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 GND I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 IN IN IN

Functional Logic Diagram ATV2500B Note: 1. Not required for PLCC versions of A TV2500BQ or A TV2500BQL, making them compatible with A TV2500H and A TV2500L pinout.

Description

The ATV2500Bs are the highest density PLDs available in a 40- or 44-pin package. With their fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATV2500Bs are organized around a single universal and-or array. All pin and feedback terms are always avail- able to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop. In the ATV2500Bs, four product terms are input to each sum term. Furthermore, each macrocell's three sum terms can be combined to provide up to 12 product terms per sum term with no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array. Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops may also be individu- ally configured to have direct input pin clocking. Each out- put has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power up. Several low power device options allow selection of the optimum solution for many power-sensitive applications. Each of the options significantly reduces total system power and enhances system reliability. Functional Logic Diagram Description The ATV2500B functional logic diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the sin- gle global bus. The ATV2500Bs are straightforward and uniform PLDs. The 24 macrocells are numbered 0 through 23. Each mac- rocell contains 17 AND gates. All AND gates have 172 inputs. The five lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous reset and clock per flip-flop, and an output enable. The top 12 product terms are grouped into three sum terms, which are used as shown in the macrocell diagrams. Eight synchronous preset terms are distributed in a 2/4 pat- tern. The first four macrocells share Preset 0, the next two share Preset 1, and so on, ending with the last two macro- cells sharing Preset 7. The 14 dedicated inputs and their complements use the numbered positions in the global bus as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2 (1) true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by these signals in the global bus are the six numbers in the bus diagram next to each macrocell. Note: 1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATV2500Bs.

*NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V dc which may undershoot to -2.0V for pulses of less than 20ns. Maximum out- put pin volt- age is V CC +0.75V dc which may over- shoot to +7.0V for pulses of less than 20ns. Absolute Maximum Ratings* Voltage on Any Pin with (1) Voltage on Input Pins with Respect to Ground Programming Voltage with (1) Note: 1. T ypical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. DC and AC Operating Conditions Commercial Industrial Military Operating T emperature (Case) 0°C - 70°C -40°C - 85°C -55°C - 125°C VCC Power Supply 5V ± 5% 5V ± 10% 5V ± 10% Pin Capacitance (f = 1 MHz, T = 25°C)(1) Typ Max Units Conditions C IN 46 p F V IN = 0V C OUT 81 2 p F V OUT = 0V

Output Logic, Registered(1) Output Logic, Combinatiorial(1) Note: 1. These diagrams show equivalent logic functions, not necessarily the actual circuit implementation. Note: 1. These four terms are shared with D/T1. Clock Option S2 = 0 Terms in Output ConfigurationS1 S0 D/T1 D/T2

0084 Registered (Q1); Q2 FB

10 1 2 4 (1) Registered (Q1); Q2 FB

1184 Registered (Q1); D/T2 FB

S3 Ouput Configuration S6 Q1 CLOCK

0 Active Low 0 CK1

1 Active High 1 CK1 • PIN1

S4 Register 1 Type S7 Q2 CLOCK 0D 0C K 2 1T 1C K 2 • P I N 1 S5 Register 2 Type S2 = 1 Terms in Output ConfigurationS5 S1 S0 D/T1 D/T2 X00 4 (1) 4 Combinatorial (8 Terms); Q2 FB X0144 Combinatorial (4 Terms); Q2 FB X10 4 (1) 4(1) Combinatorial (12 Terms); Q2 FB 111 4 (1) 4 Combinatorial (8 Terms); D/T2 FB

01144 Combinatorial (4 Terms);

Note: 1. See ICC versus frequency characterization curves. DC Characteristics Symbol Parameter Condition Min Typ Max Units IIL Input Load Current VIN = -0.1V to VCC + 1V 10 µA ILO Output Leakage Current VOUT = -0.1V to VCC + 0.1V 10 µA ICC Power Supply Current, Standby V CC = MAX, VIN = GND or VCC f = 0 MHz, Outputs Open A TV2500B Com. 110 190 mA Ind., Mil. 110 210 mA A TV2500BQ Com. 30 70 mA Ind., Mil. 30 85 mA A TV2500BL Com. 2 5 mA Ind., Mil. 2 10 mA A TV2500BQL Com. 2 4 mA Ind., Mil. 2 5 mA IOS Output Short Circuit Current VOUT = 0.5V -120 mA VIL Input Low Voltage MIN ≤ VCC ≤ MAX -0.6 0.8 V VIH Input High Voltage 2.0 V CC + 0.75 V VOL Output Low VoltageVIN = VIH or VIL, VCC = 4.5V IOL = 8 mA Com., Ind. 0.5 V IOL = 6 mA Mil. 0.5 V VOH Output High Voltage VCC = MIN IOH = -4.0 mA V CC - 0.3 V IOH = -4.0 mA 2.4

AC Waveforms (1) Input Pin Clock AC Waveforms (1) Product Term Clock Register AC Characteristics, Input Pin Clock Symbol Parameter UnitsMin Max Min Max Min Max Min Max Min Max tCOS C l o c k t o O u t p u t 7 . 5 1 01 11 21 5 n s tCFS C l o c k t o F e e d b a c k 0405060708 n s tSIS Input Setup Time 7 9 14 20 23 ns tSFS Feedback Setup Time 7 9 14 20 23 ns tHS H o l d T i m e 00000 n s tWS C l o c k W i d t h 56789 n s tPS Clock Period 10 12 14 16 18 ns FMAXS External Feedback 1/(tSIS + tCOS ) 6 95 24 03 12 6 M H z Internal Feedback 1/(tSFS + tCFS )9 07 15 03 73 2 M H z No Feedback 1/(tPS ) 100 83 71 62 55 MHz tARS Asynchronous Reset/Preset Recovery Time 7 1 21 52 02 5 n s

AC Waveforms (1) Combinatorial Outputs and Feedback Register AC Characteristics, Product Term Clock Symbol Parameter UnitsMin Max Min Max Min Max Min Max Min Max tCOA Clock to Output 12 15 20 22 25 ns tCFA Clock to Feedback 3 7 5 12 10 16 12 18 13 20 ns tSIA Input Setup Time 4 5 10 15 19 ns tSFA Feedback Setup Time 4 5 8 10 10 ns tHA Hold Time 3 5 10 12 13 ns tWA Clock Width 5.5 7.5 11 14 15 ns tPA Clock Period 11 15 22 28 30 ns FMAXA External Feedback 1/(tSIA + tCOA ) 6 2 . 5 5 03 32 72 3 M H z Internal Feedback 1/(tSFA + tCFA )9 05 83 83 62 4 M H z No Feedback 1/(tPS ) 9 06 64 53 63 3 M H z tARA Asynchronous Reset/Preset Recovery Time 3 8 12 15 18 ns

n Ma x Min Ma x Min Ma x Min Ma x tPD1 Input to Non-Registered Output 12 15 20 25 30 ns tPD2 Feedback to Non-Registered Output 12 15 20 25 30 ns tPD3 Input to Non-Registered Feedback 8 1 11 51 82 0 n s tPD4 Feedback to Non-Registered Feedback 8 1 11 51 82 0 n s tEA1 Input to Output Enable 12 15 20 25 30 ns tER1 Input to Output Disable 12 15 20 25 30 ns tEA2 Feedback to Output Enable 12 15 20 25 30 ns tER2 Feedback to Output Disable 12 15 20 25 30 ns tAW Asynchronous Reset Width 6 8 12 15 18 ns tAP Asynchronous Reset to Registered Output 15 18 22 28 30 ns tAPF Asynchronous Reset to Registered Feedback 12 15 19 25 30 ns Input Test Waveforms and Measurement Levels Output Test Load Preload and Observability of Registered Outputs The ATV2500Bs registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A V IH level on the odd I/O pins will force the appropriate register high; a VIL will force it low, independent of the polarity or other configuration bit settings. The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12 registers chosen by the Q select and even/odd select pins. Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2. In this mode, the contents of the buried register bank will appear on the associated outputs when the OE control signals are active.

The registers in the ATV2500Bs are designed to reset dur- ing power up. At a point delayed slightly from VCC crossing VRST , all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises in the system, the fol- lowing conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin or terms high, and 3. The clock pin, and any signals from which clock terms are derived, must remain stable during t PR . Level forced on Odd I/O pin during PRELOAD cycle Q Select Pin State Even/Odd Select Even Q1 state after cycle Even Q2 state after cycle Odd Q1 state after cycle Odd Q2 state after cycle VIH/VIL Low Low High/Low X X X VIH/VIL High Low X High/Low X X VIH/VIL Low High X X High/Low X VIH/VIL High High X X X High/Low Parameter Description Typ Max Units tPR Power-Up Reset Time 600 1000 ns VRST Power-Up Reset Voltage 3.8 4.5 V

A single fuse is provided to prevent unauthorized copying of ATV2500B fuse patterns. Once programmed, the out- puts will read programmed during verify. The security fuse should be programmed last, as its effect is immediate. The security fuse also inhibits Preload and Q2 observabil- ity. Atmel CMOS PLDs The ATV2500Bs utilize an advanced 0.65-micron CMOS EPROM technology. This technology's state of the art fea- tures are the optimum combination for PLDs:

• CMOS technology provides high speed, low power, and high noise immunity.
• EPROM technology is the most cost effective method for producing PLDs - surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability.
• EPROM reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible PLDs. Using the ATV2500Bs Many Advanced

The ATV2500Bs advanced flexibility packs more usable gates into 44 leads than other PLDs. Some of the ATV2500Bs key features are:

• Fully Connected Logic Array - Each array input is always available to every product term. This makes logic placement a breeze.
• Selectable D- and T -Type Registers - Each ATV2500B flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage.
• Buried Combinatorial Feedback - Each macrocell's Q2 register may be bypassed to feed its input (D/T2) directly back to the logic array. This provides further logic expansion capability without using precious pin resources.
• Selectable Synchronous/Asynchronous Clocking - Each of the ATV2500Bs flip-flops has a dedicated clock product term. This removes the constraint that all registers use the same clock. Buried state machines, counters and registers can all coexist in one device while running on sep- arate clocks. Individual flip-flop clock source selection fur- ther allows mixing higher performance pin clocking and flexible product term clocking within one design.
• A T otal of 48 Registers - The ATV2500B provides two flip-flops per macrocell - a total of 48. Each register has its own clock and reset terms, as well as its own sum term.
• Independent I/O Pin and Feedback Paths - Each I/O pin on the ATV2500B has a dedicated input path. Each of the 48 registers has its own feedback term into the array as well. These features, combined with individual product terms for each I/O's output enable, facilitate true bi- directional I/O design.
• Combinable Sum T erms - Each output macrocell's three sum terms may be combined into a single term. This provides a fan in of up to 12 product terms per sum term with no speed penalty. Programming Software Support As with all other Atmel PLDs, several third party PLD devel- opment software products and programmers will support the ATV2500Bs. Several third party programmers will support the ATV2500B as well. Additionally, the ATV2500B may be programmed to perform the ATV2500H/Ls functional sub- set (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H/L JEDEC file. In this case, the ATV2500B becomes a direct replacement or speed upgrade for the ATV2500H/L (additional GND connections are required). Please refer to the Programmable Logic Development Tools section for a complete PLD software and programmer listing. Erasure Characteristics The entire memory array of an ATV2500B is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 min- utes exposure using 12,000 µ W/cm 2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W
• sec/cm2. To prevent unintentional erasure, an opaque label is recom- mended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight.

Note: 1. All normalized values referenced to maximum specification in AC Characteristics of data sheet.

vs. OUTPUT VOLTAGE (VCC=5V,T A=25°C) OUTPUT VOLT AGE (V) I O H m A OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE (VCC=5V,T A=25°C) -80 -60 -40 -20 OUTPUT VOLT AGE (V) I O H m A NORMALIZED TCO vs. SUPPLYVOL T AGE (TA=25°C ) 0.8 0.9 1.0 1.1 1.2 1.3 SUPPLYVOL T AGE (V) N O R M T C O A TV2500BQ(L) A TV2500B(L) NORMALIZED TPD vs. AMBIENT TEMPERATURE (VCC = 5V) 0.8 0.9 1.0 1.1 1.2 1.3 - 5 5 - 2 55 3 56 59 51 2 5 AMBIENT TEMPERATURE (C) N O R M T P D ATV2500B(L) ATV2500BQ (L) NORMALIZED TCO vs. AMBIENT TEMPERATURE (VCC = 5V) 0.8 0.9 1.0 1.1 1.2 1.3 -55 -25 5 35 65 95 125 AMBIENT TEMPERATURE (C) N O R M T C O ATV2500B(L) ATV2500BQ (L) Note: 1. All normalized values referenced to maximum specification in AC Characteristics of data sheet.

Note: 1. All normalized values referenced to maximum specification in AC Characteristics of data sheet.

Ordering Information

(ns) tCOS (ns) Ext. fMAXS (MHz) Ordering Code Package Operation Range 12 7.5 69 A TV2500B-12JC 44J Commercial A TV2500B-12KC 44KW (0 °C to 70°C) 15 10 52 A TV2500B-15JC 44J Commercial A TV2500B-15KC 44KW (0 °C to 70°C) A TV2500B-15JI 44J Industrial A TV2500B-15KI 44KW (-40 °C to 85°C) A TV2500B-15KM 44KW Military A TV2500B-15LM 44LW (-55 °C to 125°C) A TV2500B-15KM/883 44KW Military/883C A TV2500B-15LM/883 44LW (-55 °C to 125°C) Class B, Fully Compliant 20 11 40 A TV2500BL-20JC 44J Commercial A TV2500BL-20KC 44KW (0 °C to 70°C) A TV2500BL-20JI 44J Industrial A TV2500BL-20KI 44KW (-40 °C to 85°C) A TV2500BL-20KM 44KW Military A TV2500BL-20LM 44LW (-55 °C to 125°C) A TV2500BL-20KM/883 44KW Military/883C A TV2500BL-20LM/883 44LW (-55 °C to 125°C) Class B, Fully Compliant 20 11 40 A TV2500BQ-20DC 40DW6 Commercial A TV2500BQ-20JC 44J (0 °C to 70°C) A TV2500BQ-20KC 44KW A TV2500BQ-20PC 40P6 25 12 31 A TV2500BQ-25DC 40DW6 Commercial A TV2500BQ-25JC 44J (0 °C to 70°C) A TV2500BQ-25KC 44KW A TV2500BQ-25PC 40P6 A TV2500BQ-25DI 40DW6 Industrial A TV2500BQ-25JI 44J (-40 °C to 85°C) A TV2500BQ-25KI 44KW A TV2500BQ-25PI 40P6 A TV2500BQ-25DM 40DW6 Military/883C A TV2500BQ-25KM 44KW (-55 °C to 125°C) A TV2500BQ-25LM 44LW A TV2500BQ-25DM/883 40DW6 Military/883C A TV2500BQ-25KM/883 44KW (-55 °C to 125°C) A TV2500BQ-25LM/883 44LW Class B, Fully Compliant

25 12 31 A TV2500BQL-25DC 40DW6 Commercial A TV2500BQL-25JC 44J (0 °C to 70°C) A TV2500BQL-25KC 44KW A TV2500BQL-25PC 40P6 25 12 31 A TV2500BQL-25DI 40DW6 Industrial A TV2500BQL-25JI 44J (-40 °C to 85°C) A TV2500BQL-25KI 44KW A TV2500BQL-25PI 40P6 30 15 26 A TV2500BQL-30DM 40DW6 Military/883C A TV2500BQL-30KM 44KW (-55 °C to 125°C) A TV2500BQL-30LM 44LW 15 26 A TV2500BQL-30DM/883 40DW6 Military/883C A TV2500BQL-30KM/883 44KW (-55 °C to 125°C) A TV2500BQL-30LM/883 44LW Class B, Fully Compliant 15 10 52 5962 - 9154504MXX 44LW Military/883C 5962 - 9154504MYX 44KW (-55 °C to 125°C) Class B, Fully Compliant 20 11 40 5962 - 9154505MXX 44LW Military/883C 5962 - 9154505MYX 44KW (-55 °C to 125°C) Class B, Fully Compliant 25 12 31 5962 - 9154506MXX 44LW Military/883C 5962 - 9154506MYX 44KW (-55 °C to 125°C) 5962 - 9154506MQA 40DW6 Class B, Fully Compliant 30 15 26 5962 - 9154507MXX 44LW Military/883C 5962 - 9154507MYX 44KW (-55 °C to 125°C) 5962 - 9154507MQA 40DW6 Class B, Fully Compliant Ordering Information (Continued) tPD (ns) tCOS (ns) Ext. fMAXS (MHz) Ordering Code Package Operation Range Package Type 40DW6 40-Lead, 0.600" Wide, Ceramic, Dual Inline Package (Cerdip) 44J 44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 44KW 44-Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) 40P6 40-Lead, 0.600" Wide, Plastic, Dual Inline Package OTP (PDIP) 44LW 44-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC)

.045(1.14) X 45° PIN NO. 1 IDENTIFY .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) REF SQ .032(.813) .026(.660) .050(1.27) TYP .656(16.7) .650(16.5) .695(17.7) .685(17.4)SQ SQ .045(1.14) X 45° .032(.813) .026(.660) .050(1.27) TYP .500(12.7) REF SQ .035(.889) X 45° .010(.254) .006(.152) .021(.533) .017(.432) .630(16.0) .590(15.0) .045(1.14) .035(.889) .120(3.05) .090(2.29) .180(4.57) .156(3.96) .665(16.9) .645(16.4) .695(17.7) .685(17.4) SQ SQ .025(.635) RADIUS MAX (3X) 2.07(52.6) 2.04(51.8) PIN .566(14.4) .530(13.5) .090(2.29) MAX .005(.127) MIN .065(1.65) .015(.381) .022(.559) .041(1.04)

15 REF

.690(17.5) .610(15.5) .630(16.0) .590(15.0) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) SEATING PLANE .220(5.59) MAX 1.900(48.26) REF 40DW6 , 40-Lead, 0.600” Wide, Windowed, Ceramic Dual Inline Package (Cerdip) Dimensions in Inches and (Millimeters) MIL-STD-1835 D-5 CONFIG A 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensiosn in Inches and (Millimeters) JEDEC STANDARD MS-018 AC 44KW , 44-Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) Dimensions in Inches and (Millimeters) MIL-STD-1835 CJ1 40P6, 40-Lead, 0.600” Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDED STANDARD MS-011 AC

*Controlling dimension: millimeters 44LW , 44-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters)* MIL-STD-1835 C-5