ATU18 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion Very effective associated Physical synthesis/optimization Flow From 45K Gates up to 1000K Gates Supported From 55Kbit to 847Kbit DPRAM Compatible with Xilinx and Altera Latest FPGA’s Pin-count: Over 700 pins Any Pin–out Matched Full Range of Packages: PQFP/TQFP/VQFP , BGA/FLBGA, PGA/PPGA, QFN, CS Available in Commercial, Industrial and Military Grades 0.18 um Drawn CMOS, 5 Metal Layers Library Optimised for best Synthesis, Place & route and Testability Generation (ATPG) High system clock Skew Control 250Mhz system clock, up to 400Mhz for local clock Power on Reset, PLL, Multiplier Standard 3, 6, 12, 24 mA I/Os LVCMOS, LVTTL, GTL, HSTL, LVPECL, PCI & LVDS Interfaces High Noise & EMC Immunity Thick Oxide periphery Allowing Interface with 2.5V and 3.3V Environments
Description
The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs. It supports within one ULC 55Kbits to 847Kbits DPRAM and 45Kgates to 1000 Kgates. Typically, ULC die size is 50% smaller than the equivalent FPGA. Metal level customisation allows a DPRAM blocks compatibility with Xilinx ® or Altera® blocks. Devices are implemented in high–performance 0.18 um CMOS technology to improve the design frequency and reach 250Mhz typical application and local clock up to 400Mhz. The architecture of the ATU18 series is dedicated for efficient conversion of latest CPLD and FPGA device types with higher IO count. A compact RAM cell and a large number of available gates allow t he implementation of memories compatible with FPGA RAM, as well as JTAG boundary–scan and scan–path testing. Conversion to the ATU18 series of ULC provides a significant reduction of the operat- ing power when compared to the original PLD or FPGA. The ATU18 series has a very low standby consumption, less than 0.145 nA/gate typically at commercial tempera- ture. Operating consumption is a strict function of clock frequency, which typically results in a significant power reduction depending on the device being compared. For a NAND2 cell the dynamic power consumption is 0.124uW/MHz at 1.8V. 0.18 um ULC Series with Embedded DPRAM ATU18 4318C–ULC–08/05
supply buses and internal decoupling for isolation. improving drastically the application frequency and power consumption. Table 1. Matrices
Table 2. Dual Port Mode Configurations
I/O Flexibility All I/O buffers at the periphery may be configured as input, output, bi-directional and oscillator. pull down resistor or bus keeper. The Standard IO supported are given in table 3. drive is achievable using two adjacent pads). Table 3. Standard IO Supported
Table 4. Pin Description
to reduce and even remove the clock tree delay. Figure 3. PLL Frequency Synthesis outx0, it is necessary to set the input clock divider M to 1 and the feed-back clock divider N to 10.
4318C–ULC–08/05 ATU18 Atmel Flow With 0.18um technology , ATMEL has introduced Physical synthesis to optimize design speed. Physical synthesis takes into account the placement and the routing of the cells, and the optimization in incremental mode can be done on the full design or only partially. The result is that ATMEL has faster chips, using the same RTL code. Less iterations are necessary and the timings target is quickly reached. Code SYNTHESIS Placement Clock Tree synthesis Route PHYSICAL SYNTHESIS ATMEL Bonding diagram Customer Timing constraints Post layout Simulations, Timing & power Analysis Timing , Power OPT Customer RTL DRC - LVS TAPE OUT SCAN, JTAG, BIST NETLIST for Layout ATMEL NETLIST Formal Proof Customer Pinout
4318C–ULC–08/05 ATU18 ATU18 Packages The following packages are supported: gray cells : supported package configuration Remark: Other package and package/matrix configurations can be supported upon request ATU18_680 ATU18_600 ATU18_484 ATU18_432 ATU18_352 ATU18_304 ATU18_256 ATU18_160
100 TQFP
144 TQFP
100 PQFP
160 PQFP
208 PQFP
240 PQFP
304 PQFP
100 FLBGA
144 FLBGA
256 FLBGA
324 FLBGA
456 FLBGA
484 FLBGA
556 FLBGA
672 FLBGA
676 FLBGA
680 FLBGA
780 FLBGA
860 FLBGA
900 FLBGA
1020 FLBGA
1156 FLBGA
1508 FLBGA
225 BGA
256 BGA
313 BGA
329 BGA
352 BGA
356 BGA
432 BGA
560 SBGA
600 SBGA
652 SBGA
4318C–ULC–08/05 ATU18
Electrical Characteristics
Absolute Maximum Ratings* PLL Specifications Operating Temperature *NOTICE: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. This value is based on the maximum allowable die temperature and the thermal resistance of the package. Operating Modes - Clock tree reduction - Zero delay buffer - Phase shift - Frequency synthesis
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