ATTINY13-24SSJ

ATTINY13 ATMEL | Alldatasheet

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Technical content

Features

 High Performance, Low Power AVR® 8-Bit Microcontroller  Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation  Non-volatile Program and Data Memories – 1K Byte of In-System Programmable Program Memory Flash Endurance: 10,000 Write/Erase Cycles – 64 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – 64 Bytes Internal SRAM – Programming Lock for Self-Programming Flash Program and EEPROM Data Security  Peripheral Features – One 8-bit Timer/Counter with Prescaler and Two PWM Channels – 4-channel, 10-bit ADC with Internal Voltage Reference – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator  Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator  I/O and Packages – 8-pin PDIP/SOIC: Six Programmable I/O Lines  Operating Voltage: – 1.8 - 5.5V for ATtiny13V – 2.7 - 5.5V for ATtiny13  Speed Grade – ATtiny13V: 0 - 6 MHz @ 1.8 - 5.5V, 0 - 12 MHz @ 2.7 - 5.5V – ATtiny13: 0 - 12 MHz @ 2.7 - 5.5V, 0 - 24 MHz @ 4.5 - 5.5V  Industrial Temperature Range  Low Power Consumption – Active Mode: 1 MHz, 1.8V: 240µA – Power-down Mode: < 0.1µA at 1.8V Pin Configurations Figure 1. Pinout ATtiny13

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2535B–AVR–01/04 Overview The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2. Block Diagram PROGRAM COUNTER INTERNAL OSCILLA TOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH SRAM MCU CONTROL REGISTER GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER/ COUNTER0 INSTRUCTION DECODER DATA DIR. REG.PORT B DATA REGISTER PORT B PROGRAMMING LOGIC TIMING AND CONTROL MCU STATUS REGISTER STATUS REGISTER ALU PORT B DRIVERS PB0-PB5 VCC GND CONTROL LINES 8-BIT DATABUS Z ADC / ANALOG COMPARATOR INTERRUPT UNIT CALIBRATED Y X RESET CLKI WATCHDOG OSCILLATOR DATA EEPROM

2535B–AVR–01/04 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny13 provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general pur- pose working registers, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register con- tents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny13 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir- cuit Emulators, and Evaluation kits. Pin Descriptions VCC Digital supply voltage. GND Ground. Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13 as listed on page 49. RESET Reset input. A low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running. The minimum pulse length is given in Table 12 on page 30. Shorter pulses are not guaranteed to generate a reset. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit defini- tions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

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2535B–AVR–01/04 AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being exe- cuted, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In- System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Direct AddressingIndirect Addressing Interrupt Unit Watchdog Timer Analog Comparator I/O Module 2 I/O Module1 I/O Module n

2535B–AVR–01/04 the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Pro- gram memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a con- stant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruc- tion Set” section for a detailed description.

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2535B–AVR–01/04 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as:  Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ- ual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I- bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.  Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.  Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.  Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple- ment Overflow Flag V. See the “Instruction Set Description” for detailed information.  Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.  Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.  Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.  Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc- tion Set Description” for detailed information. B i t 76543210 I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

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The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5. The X-, Y -, and Z-registers PUSH command decreases the Stack Pointer. address in SRAM during on reset. The Stack Pointer must be set to point above 0x60. case, the SPH Register will not be present.

15 XH XL 0

15 YH YL 0

15 ZH ZL 0

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2535B–AVR–01/04 There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remem- bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the cor- responding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disap- pears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and exe- cute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt rou- tine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simulta- neously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. Assembly Code Example inr16, SREG; store SREG value cli ; disable interrupts during timed sequence sbiEECR, EEMWE; start EEPROM write sbiEECR, EEWE outSREG, r16; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG;/* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */

2535B–AVR–01/04 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. Assembly Code Example sei; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */

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spaces are linear and regular. on Flash data serial downloading using the SPI pins. the LPM – Load Program memory instruction description). Figure 8. Program Memory Map

SRAM Data Memory Figure 9 shows how the ATtiny13 SRAM Memory is organized. the Register File, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. address given by the Y- or Z-register. increment, the address registers X, Y, and Z are decremented or incremented. Register File is described in “General Purpose Register File” on page 7. Figure 9. Data Memory Map Data Memory Access Times This section describes the general access timing concepts for internal memory access. Figure 10. On-chip Data SRAM Access Cycles

32 Registers

64 I/O Registers

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2535B–AVR–01/04 EEPROM Data Memory The ATtiny13 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endur- ance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see page 103. EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 18 for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be fol- lowed. Refer to “Atomic Byte Programming” on page 16 and “Split Byte Programming” on page 16 for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. EEPROM Address Register – EEARL  Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.  Bits 5..0 – EEAR5..0: EEPROM Address The EEPROM Address Register – EEARL – specifies the EEPROM address in the 64 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63. The initial value of EEARL is undefined. A proper value must be written before the EEPROM may be accessed. EEPROM Data Register – EEDR  Bits 7..0 – EEDR7..0: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEARL Register. For the EEPROM read oper- ation, the EEDR contains the data read out from the EEPROM at the address given by EEARL. B i t 76543210 – – EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X X X X X B i t 76543210 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X

with future AVR devices, always write this bit to zero. After reading, mask out this bit. This bit is reserved in the ATtiny13 and will always read as zero. reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. constant interrupt when Non-volatile memory is ready for programming. The EEMPE bit determines whether writing EEPE to one will have effect or not. halted for two cycles before the next instruction is executed. Table 1. EEPROM Mode Bits

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2535B–AVR–01/04 one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is nei- ther possible to read the EEPROM, nor to change the EEARL Register. Atomic Byte Programming Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEARL Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 1. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations. Split Byte Programming It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations (typically after Power-up). Erase To erase a byte, the address must be written to EEARL. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase opera- tion only (programming time is given in Table 1). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations. Write To write a location, the user must write the address into EEARL and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in Table 1). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations. The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscilla- tor frequency is within the requirements described in “Oscillator Calibration Register – OSCCAL” on page 22.

2535B–AVR–01/04 The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode ldir16, (0<<EEPM1)|(0<<EEPM0) outEECR, r16 ; Set up address (r17) in address register out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write(unsigned char ucAddress, unsigned char ucData) /* Wait for completion of previous write */ while(EECR & (1<<EEPE)) /* Set Programming mode */ EECR = (0<<EEPM1)|(0>>EEPM0) /* Set up address and data registers */ EEARL = ucAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE);

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2535B–AVR–01/04 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Preventing EEPROM Corruption During periods of low VCC , the EEPROM data can be corrupted because the supply volt- age is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V CC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r17) in address register out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned char ucAddress) /* Wait for completion of previous write */ while(EECR & (1<<EEPE)) /* Set up address register */ EEARL = ucAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR;

2535B–AVR–01/04 I/O Memory The I/O space definition of the ATtiny13 is shown in “Register Summary” on page 153. All ATtiny13 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instruc- tions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and Peripherals Control Registers are explained in later sections.

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Figure 11. Clock Distribution core from performing general operations and calculations. active simultaneously with the CPU clock. rate ADC conversion results.

and routed to the appropriate modules.Note: 1. For all fuses “1” means unprogrammed while “0” means programmed. time the start-up, ensuring stable Oscillator operation before instruction execution starts. used for each time-out is shown in Table 3. Table 2. Device Clocking Options Select Table 3. Number of Watchdog Oscillator Cycles

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grammed calibration value, see the section “Calibration Byte” on page 102. Note: 1. The device is shipped with this option selected. Note: 1. The device is shipped with this option selected. This bit is reserved bit in the ATtiny13 and will always read as zero. Table 4. Internal Calibrated RC Oscillator Operating Modes Table 5. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

11 Reserved

write may fail. Note that the Oscillator is intended for calibration to 9.6 MHz or 4.8 MHz. Tuning to other values is not guaranteed, as indicated in Table 6. OSCCAL should not exceed 0x20 for each calibration. Figure 12. To run the device on an external clock, the CKSEL Fuses must be pro- Figure 12. External Clock Drive Configuration Prescaler” on page 24 for details. Table 6. Internal RC Oscillator Frequency Range Table 7. Start-up Times for the External Clock Selection

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The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. by programming the CKSEL Fuses to “11”. clkCPU , and clkFLASH are divided by a factor as shown in Table 9. extend the time-out period, nor clear the CLKPCE bit. These bits are reserved bits in the ATtiny13 and will always read as zero. sion factors are given in Table 9.

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits
2. Within four cycles, write the desired value to CLKPS while writing a zero to

Table 8. Start-up Times for the 128 kHz Internal Oscillator

tions. The device is shipped with the CKDIV8 Fuse programmed. quency corresponding to the new setting. takes to switch from one clock division to another cannot be exactly predicted. Table 9. Clock Prescaler Select

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trollers an ideal choice for low power applications. power consumption to the application’s requirements. during sleep mode, the MCU wakes up and executes from the Reset Vector. tribution. The figure is helpful in selecting an appropriate sleep mode. The MCU Control Register contains control bits for power management. These bits select between the three available sleep modes as shown in Table 10. This bit is a reserved bit in the ATtiny13 and will always read as zero. Table 10. Sleep Mode Select

00 I d l e

10 P o w e r - d o w n

11 R e s e r v e d

CPU and clkFLASH , while allowing the other clocks to run. clkCPU , and clkFLASH , while allowing the other clocks to run. rupts” on page 52 for details. Note: 1. For INT0, only level interrupt. Table 11. Active Clock Domains and Wake-up Sources in the Different Sleep Modes

28 ATtiny13

2535B–AVR–01/04 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possi- ble, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “Analog to Digital Con- verter” on page 77 for details on ADC operation. Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Ref- erence will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 74 for details on how to configure the Analog Comparator. Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detec- tion” on page 32 for details on how to configure the Brown-out Detector. Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detec- tion, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be con- suming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Voltage Reference” on page 34 for details on the start-up time. Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Interrupts” on page 40 for details on how to con- figure the Watchdog Timer. Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk I/O) and the ADC clock (clkADC ) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 45 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an analog signal level close to V CC /2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC /2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Regis- ter (DIDR0). Refer to “Digital Input Disable Register 0 – DIDR0” on page 76 for details.

2535B–AVR–01/04 System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 13 shows the reset logic. Table 12 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 21. Reset Sources The ATtiny13 has four sources of reset:  Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V POT ).  External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length.  Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.  Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT ) and the Brown-out Detector is enabled.

30 ATtiny13

Figure 13. Reset Logic Notes: 1. Values are guidelines only. Actual values are TBD.

1. The Power-on Reset will not work unless the supply voltage has been below VPOT

Table 12. Reset Characteristics(1)

32 ATtiny13

the delay counter starts the MCU after the Time-out period – tTOUT – has expired. Figure 16. External Reset During Operation BOT+ = VBOT + VHYST /2 and VBOT- = VBOT - VHYST /2. to a voltage where correct operation of the microcontroller is no longer guaranteed. out period tTOUT has expired. for longer than tBOD given in Table 12. Table 13. BODLEVEL Fuse Coding (1)

11 BOD Disabled

Table 14. Brown-out Characteristics

34 ATtiny13

writing a logic zero to the flag. Detection, and it can be used as an input to the Analog Comparator or the ADC. The voltage reference has a start-up time that may influence the way it should be used.

1. When the BOD is enabled (by programming the BODLEVEL [1..0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting

Note: 1. Values are guidelines only. Actual values are TBD. Table 15. Internal Voltage Reference Characteristics(1)

Figure 19. Watchdog Timer

1. In the same operation, write a logic one to the Watchdog change enable bit
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits

36 ATtiny13

2535B–AVR–01/04 The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. Note: 1. The example code assumes that the part specific header file is included. Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Assembly Code Example (1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<<WDRF)) out MCUSR, r16 ; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out in r16, WDTCR ori r16, (1<<WDCE) | (1<<WDE) out WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ; Turn on global interrupt sei ret C Code Example(1) void WDT_off(void) __disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; __enable_interrupt();

2535B–AVR–01/04 Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation rou- tine, even if the Watchdog is not in use. The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Note: 1. The example code assumes that the part specific header file is included. Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. Watchdog Timer Control Register - WDTCR Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence in r16, WDTCR ori r16, (1<<WDCE) | (1<<WDE) out WDTCR, r16 ; -- Got four cycles to set the new values from here - ; Set new prescaler(time-out) value = 64K cycles (~0.5 s) ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0) out WDTCR, r16 ; -- Finished setting new values, used 2 cycles - ; Turn on global interrupt sei ret C Code Example(1) void WDT_Prescaler_Change(void) __disable_interrupt(); __watchdog_reset(); /* Start timed sequence */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */ WDTCR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); B i t 76543210 WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0

38 ATtiny13

interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. interrupt is not executed before the next time-out, a System Reset will be applied. WDE bit, and/or change the prescaler bits, WDCE must be set. Once written to one, hardware will clear WDCE after four clock cycles. resets during conditions causing failure, and a safe start-up after the failure. shown in Table 17 on page 39. Table 16. Watchdog Timer Configuration

011 Interrupt and System

Table 17. Watchdog Timer Prescale Select

40 ATtiny13

Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny13. Table 18. Reset and Interrupt Vectors

115 for a complete list of parameters. Figure 20. I/O Pin Equivalent Schematic tion for I/O-Ports” on page 51. full description of the alternate functions.

42 ATtiny13

of the other pins in the port as general digital I/O. functional description of one I/O-port pin, here generically called Pxn. Figure 21. General Digital I/O(1) Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP , and PUD are common to all ports. reset condition becomes active, even if no clocks are running. put pin, the port pin is driven low (zero).

DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. the MCUCR Register can be set to disable all pull-ups in all ports. ({DDxn, PORTxn} = 0b10) as an intermediate step. Table 19 summarizes the control signals for the pin value. Figure 22. Synchronization when Reading an Externally Applied Pin value Table 19. Port Pin Configurations

44 ATtiny13

Consider the clock period starting shortly after the first falling edge of the system clock. period depending upon the time of assertion. Figure 23. Synchronization when Reading a Software Assigned Pin Value

2535B–AVR–01/04 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The result- ing pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defin- ing bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Digital Input Enable and Sleep Modes As shown in Figure 21, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to V CC /2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external inter- rupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Func- tions” on page 46. If a logic high level (“one”) is present on an asynchronous external interrupt pin config- ured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set Assembly Code Example (1) ... ; Define pull-ups and set outputs high ; Define directions for port pins outPORTB,r16 outDDRB,r17 ; Insert nop for synchronization nop ; Read port pins in r16,PINB ... C Code Example unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ /* Insert nop for synchronization*/ _NOP(); /* Read port pins */ i = PINB; ...

46 ATtiny13

2535B–AVR–01/04 when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. Alternate Port FunctionsMost port pins have alternate functions in addition to being general digital I/Os. Figure 24 shows how the port pin control signals from the simplified Figure 21 can be overrid- den by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR micro- controller family.

Figure 24. Alternate Port Functions(1) Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.

48 ATtiny13

erated internally in the modules having the alternate function. description for further details. Table 20. Generic Description of Overriding Signals for Alternate Functions enabled when {DDxn, PORTxn, PUD} = 0b010. DDxn, PORTxn, and PUD Register bits. driver is enabled by the DDxn Register bit. is controlled by the PORTxn Register bit. of the setting of the PORTxn Register bit. If PTOE is set, the PORTxn Register bit is inverted. the alternate function will use its own synchronizer. can be used bi-directionally.

These bits are reserved bits in the ATtiny13 and will always read as zero. and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 42 for more details about this feature. Alternate Functions of Port BThe Port B pins with alternate function are shown in Table 21. Notes: 1. Reset pin, debugWire I/O, ADC Input channel, or Pin Change Interrupt.

1. ADC Input channel or Pin Change Interrupt.
2. ADC Input channel, Clock Input, or Pin Change Interrupt.
3. Serial Clock Input, Timer/Counter Clock Input, ADC Input Channel 0, or Pin Change
4. Serial Data Input, Analog Comparator Negative Input, Output Compare and PWM

Output B for Timer/Counter, External Interrupt 0 or Pin Change Interrupt.

1. Serial Data Output, Analog Comparator Positive Input, Output Compare and PWM

Output A for Timer/Counter, or Pin Change Interrupt. ing signals shown in Figure 24 on page 47. Table 21. Port B Pins Alternate Functions

50 ATtiny13

Note: 1. 1 when the Fuse is “0” (Programmed). Table 22. Overriding Signals for Alternate Functions in PB5..PB3 Table 23. Overriding Signals for Alternate Functions in PB2..PB0

2535B–AVR–01/04 Register Description for I/O-Ports Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB B i t 76543210 – – PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 76543210 –– DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 B i t 76543210 –– PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 N/A N/A N/A N/A N/A N/A

52 ATtiny13

External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. configured as outputs. This feature provides a way of generating a software interrupt. used for waking the part also from sleep modes other than Idle mode. mode. The I/O clock is halted in all sleep modes except Idle mode. SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 20. the completion of the currently executing instruction to generate an interrupt. Table 24. Interrupt 0 Sense Control 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.

2535B–AVR–01/04 General Interrupt Mask Register – GIMSK  Bits 7, 4..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.  Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Inter- rupt Vector.  Bit 5 – PCIE: Pin Change Interrupt Enable When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt is enabled. Any change on any enabled PCINT5..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt Vector. PCINT5..0 pins are enabled individually by the PCMSK0 Register. General Interrupt Flag Register – GIFR  Bits 7, 4..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.  Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter- rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt.  Bit 5 – PCIF: Pin Change Interrupt Flag When a logic change on any PCINT5..0 pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. B i t 76543210 R e a d / W r i t e R R / W R / W RRRRR I n i t i a l V a l u e 00000000 B i t 76543210 – I N T F 0 P C I F ––––– G I F R R e a d / W r i t e R R / W R / W RRRRR I n i t i a l V a l u e 00000000

54 ATtiny13

2535B–AVR–01/04 Pin Change Mask Register – PCMSK  Bits 7, 6 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. Each PCINT5..0 bit selects whether pin change interrupt is enabled on the correspond- ing I/O pin. If PCINT5..0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT5..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. B i t 76543210 – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK Read/Write R R R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00111111

Figure 25. 8-bit Timer/Counter Block Diagram

56 ATtiny13

Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 57. for details. can be used to generate an Output Compare interrupt request. TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in Table 25 are also used extensively throughout the document. clock sources and prescaler, see “Timer/Counter Prescaler” on page 72. Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 26 shows a block diagram of the counter and its surroundings. Figure 26. Counter Unit Block Diagram count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). Tn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Table 25. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). assignment is dependent on the mode of operation.

58 ATtiny13

2535B–AVR–01/04 The OCR0x Registers are double buffered when using any of the Pulse Width Modula- tion (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly. Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled). Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately.

Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to “0”. Figure 28. Compare Match Output Unit, Schematic dent of the Waveform Generation mode. modes of operation. See “8-bit Timer/Counter Register Description” on page 66. effect by using the FOC0x strobe bits.

60 ATtiny13

“Timer/Counter Timing Diagrams” on page 64. TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. consider in the Normal mode, a new counter value can be written anytime. since this will occupy too much of the CPU time. Match output frequency. It also simplifies the operation of counting external events. then counter (TCNT0) is cleared. Figure 29. CTC Mode, Timing Diagram

2535B–AVR–01/04 to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maxi- mum frequency of f OC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope opera- tion. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized exter- nal components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 30. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. f OCnx fclk_I/O

62 ATtiny13

Figure 30. Fast PWM Mode, Timing Diagram The N variable represents the prescale factor (1, 8, 64, 256, or 1024). buffer feature of the Output Compare unit is enabled in the fast PWM mode.

PWM modes, these modes are preferred for motor control applications. sent Compare Matches between OCR0x and TCNT0. Figure 31. Phase Correct PWM Mode, Timing Diagram

64 ATtiny13

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). around BOTTOM. There are two cases that give a transition without Compare Match. correspond to the result of an up-counting Compare Match. other than phase correct PWM mode. Figure 32. Timer/Counter Timing Diagram, no Prescaling Figure 33 shows the same timing data, but with the prescaler enabled.

66 ATtiny13

responding to the OC0A pin must be set in order to enable the output driver. WGM02:0 bits are set to a normal or CTC mode (non-PWM). Mode” on page 61 for more details. Table 26. Compare Output Mode, non-PWM Mode 0 0 Normal port operation, OC0A disconnected. Table 27. Compare Output Mode, Fast PWM Mode(1) 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: T oggle OC0A on Compare Match.

rect PWM Mode” on page 63 for more details. responding to the OC0B pin must be set in order to enable the output driver. WGM02:0 bits are set to a normal or CTC mode (non-PWM). Mode” on page 61 for more details. Table 28. Compare Output Mode, Phase Correct PWM Mode(1) 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: T oggle OC0A on Compare Match. Compare Match when down-counting. Compare Match when down-counting. Table 29. Compare Output Mode, non-PWM Mode 0 0 Normal port operation, OC0B disconnected. Table 30. Compare Output Mode, Fast PWM Mode(1) 0 0 Normal port operation, OC0B disconnected.

01 R e s e r v e d

68 ATtiny13

rect PWM Mode” on page 63 for more details. These bits are reserved bits in the ATtiny13 and will always read as zero. “Modes of Operation” on page 60). Table 31. Compare Output Mode, Phase Correct PWM Mode(1) 0 0 Normal port operation, OC0B disconnected. Compare Match when down-counting. Compare Match when down-counting. Table 32. Waveform Generation Mode Bit Description

The FOC0A bit is only active when the WGM bits specify a non-PWM mode. FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit. COM0A1:0 bits that determines the effect of the forced compare. The FOC0A bit is always read as zero. The FOC0B bit is only active when the WGM bits specify a non-PWM mode. FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit. COM0B1:0 bits that determines the effect of the forced compare. The FOC0B bit is always read as zero. These bits are reserved bits in the ATtiny13 and will always read as zero. See the description in the “Timer/Counter Control Register A – TCCR0A” on page 66. The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 33. Clock Select Bit Description

70 ATtiny13

interrupt, or to generate a waveform output on the OC0A pin. interrupt, or to generate a waveform output on the OC0B pin. These bits are reserved bits in the ATtiny13 and will always read as zero. 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. Table 33. Clock Select Bit Description (Continued)

2535B–AVR–01/04 executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.  Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.  Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. Timer/Counter 0 Interrupt Flag Register – TIFR0  Bits 7..4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero.  Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.  Bit 2 – OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.  Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 32, “Waveform Generation Mode Bit Description” on page 68. B i t 76543210 –––– O C F 0 B O C F 0 A TOV0 –T I F R 0 Read/Write R R R R R/W R/W R/W R I n i t i a l V a l u e 00000000

72 ATtiny13

either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). clkI/O). The latch is transparent in the high period of the internal system clock. (CSn2:0 = 6) edge it detects. Figure 36. T0 Pin Sampling clock cycles from an edge has been applied to the T0 pin to the counter is updated. An external clock source can not be prescaled.

Figure 37. Prescaler for Timer/Counter0 Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 36. zero, the PSR10 bit is cleared by hardware, and the Timer/Counter start counting. cleared immediately by hardware, except if the TSM bit is set.

74 ATtiny13

parator and its surrounding logic is shown in Figure 38. Figure 38. Analog Comparator Block Diagram Notes: 1. See Table 35 on page 76.

1. Refer to Figure 1 on page 1 and Table 23 on page 50 for Analog Comparator pin

When this bit is written logic one, the power to the Analog Comparator is switched off. can occur when the bit is changed.

ACO. The synchronization introduces a delay of 1 - 2 clock cycles. log Comparator interrupt is activated. When written logic zero, the interrupt is disabled. This bit is a reserved bit in the ATtiny13 and will always read as zero. rupt. The different settings are shown in Table 34. can occur when the bits are changed. Table 34. ACIS1/ACIS0 Settings 0 0 Comparator Interrupt on Output T oggle. 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge.

76 ATtiny13

applied to the negative input to the Analog Comparator. When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. Table 35. Analog Comparator Multiplexed Input

2535B–AVR–01/04 Analog to Digital Converter Features  10-bit Resolution  0.5 LSB Integral Non-linearity  ± 2 LSB Absolute Accuracy  13 - 260 µs Conversion Time  Up to 15 kSPS at Maximum Resolution  Four Multiplexed Single Ended Input Channels  Optional Left Adjustment for ADC Result Readout  0 - VCC ADC Input Voltage Range  Selectable 1.1V ADC Reference Voltage  Free Running or Single Conversion Mode  ADC Start Conversion by Auto Triggering on Interrupt Sources  Interrupt on ADC Conversion Complete  Sleep Mode Noise Canceler The ATtiny13 features a 10-bit successive approximation ADC. The ADC is connected to a 4-channel Analog Multiplexer which allows four single-ended voltage inputs con- structed from the pins of Port B. The single-ended voltage inputs refer to 0V (GND). The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 39. Internal reference voltages of nominally 1.1V or VCC are provided On-chip.

78 ATtiny13

Figure 39. Analog to Digital Converter Block Schematic the voltage on VCC or an internal 1.1V reference voltage. ADC input pins, can be selected as single ended inputs to the ADC. ADC before entering power saving sleep modes. be presented left adjusted by setting the ADLAR bit in ADMUX.

The ADC has its own interrupt which can be triggered when a conversion completes. ADCL, the interrupt will trigger even if the result is lost. ger a new conversion at the next interrupt event. Figure 40. ADC Auto Trigger Logic Interrupt Flag, ADIF is cleared or not. ADCSRA to one. ADSC can also be used to determine if a conversion is in progress.

80 ATtiny13

Figure 41. ADC Prescaler bit is set, and is continuously reset when ADEN is low. version starts at the following rising edge of the ADC clock cycle. ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. source signal. Three additional CPU clock cycles are used for synchronization logic.

82 ATtiny13

Figure 45. ADC Timing Diagram, Free Running Conversion Table 36. ADC Conversion Time

2535B–AVR–01/04 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem- porary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: 1. When ADATE or ADEN is cleared. 2. During conversion, minimum one ADC clock cycle after the trigger event. 3. After a conversion, before the Interrupt Flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automati- cally, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection.

84 ATtiny13

2535B–AVR–01/04 ADC Voltage Reference The reference voltage for the ADC (VREF ) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either VCC , or internal 1.1V reference, or external AREF pin. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting. Single Con- version mode must be selected and the ADC conversion complete interrupt must be enabled. 2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a con- version once the CPU has been halted. 3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC con- version is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption.

(combined resistance in the input path). minimizes the required charge transfer to the S/H capacitor. Figure 46. Analog Input Circuitry

86 ATtiny13

1. Keep analog signal paths as short as possible. Make sure analog tracks run
2. Use the ADC noise canceler function to reduce induced noise from the CPU.
3. If any port pins are used as digital outputs, it is essential that these do not

switch while a conversion is in progress. steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 47. Offset Error

88 ATtiny13

Figure 50. Differential Non-linearity (DNL) the ADC Result Registers (ADCL, ADCH). ground, and 0x3FF represents the selected reference voltage minus one LSB. This bit is reserved bit in the ATtiny13 and will always read as zero.

0 VREF Input Voltage

1 LSB

complete (ADIF in ADCSRA is set). ADC Data Register – ADCL and ADCH” on page 90. These bits are reserved bits in the ATtiny13 and will always read as zero. ADC. See Table 38 for details. change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). ing the ADC off while a conversion is in progress, will terminate this conversion.

1. This first conversion performs initialization of the ADC.

complete, it returns to zero. Writing zero to this bit has no effect. Table 37. Voltage Reference Selections for ADC 0V CC used as analog reference. 1 Internal Voltage Reference. Table 38. Input Channel Selections

00 ADC0 (PB5)

01 ADC1 (PB2)

10 ADC2 (PB4)

11 ADC3 (PB3)

90 ATtiny13

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. This bit is set when an ADC conversion completes and the data registers are updated. handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. abled. This also applies if the SBI and CBI instructions are used. plete Interrupt is activated. Table 39. ADC Prescaler Selections

When an ADC conversion is complete, the result is found in these two registers. sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. (default), the result is right adjusted. These bits are reserved bits in the ATtiny13 and will always read as zero. effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Table 40. ADC Auto Trigger Source Selections

92 ATtiny13

2535B–AVR–01/04 When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the dig- ital input buffer.

94 ATtiny13

2535B–AVR–01/04  Capacitors inserted on the RESET pin must be disconnected when using debugWire.  All external reset sources must be disconnected. Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction. Set- ting a Break Point in AVR Studio® will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK instruction will be stored. When pro- gram execution is continued, the stored instruction will be executed before continuing from the Program memory. A break can be inserted manually by putting the BREAK instruction in the program. The Flash must be re-programmed each time a Break Point is changed. This is auto- matically handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore reduce the Flash Data retention. Devices used for debugging pur- poses should not be shipped to end customers. Limitations of debugWIRE The debugWIRE communication pin (dW) is physically located on the same pin as External Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is enabled. The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e., when the program in the CPU is running. When the CPU is stopped, care must be taken while accessing some of the I/O Registers via the debugger (AVR Stu- dio). See the debugWIRE documentation for detailed description of the limitations. A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire is not used. debugWIRE Related Register in I/O Memory The following section describes the registers used with the debugWire. debugWire Data Register – DWDR The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. B i t 76543210 DWDR[7:0] DWDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

2535B–AVR–01/04 Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation: Alternative 1, fill the buffer before a Page Erase  Fill temporary page buffer  Perform a Page Erase  Perform a Page Write Alternative 2, fill the buffer after Page Erase  Perform a Page Erase  Fill temporary page buffer  Perform a Page Write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be re-written. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.  The CPU is halted during the Page Erase operation. Filling the Temporary Buffer (Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation.  The CPU is halted during the Page Write operation.

96 ATtiny13

The Z-pointer is used to address the SPM commands. addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 52. Addressing the Flash During SPM Note: 1. The different variables used in Figure 52 are listed in Table 46 on page 102.

2535B–AVR–01/04 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations.  Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and always read as zero.  Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost.  Bit 3 – RFLB: Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SELFPRGEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “EEPROM Write Prevents Writing to SPMCSR” on page 98 for details.  Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.  Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.  Bit 0 – SELFPRGEN: Self Programming Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SELFPRGEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is exe- cuted within four clock cycles. During Page Erase and Page Write, the SELFPRGEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect. B i t 7654321 0 – – – CTPB RFLB PGWRT PGERS SELFPRGEN SPMCSR Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

98 ATtiny13

2535B–AVR–01/04 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the RFLB and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the RFLB and SELFPRGEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The RFLB and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When RFLB and SELFPRGEN are cleared, LPM will work as described in the Instruction set Manual. The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the RFLB and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 45 on page 101 for a detailed description and mapping of the Fuse Low byte. Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruction is executed within three cycles after the RFLB and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to Table XXX on page XXX for detailed description and mapping of the Fuse High byte. Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. B i t 76543210 B i t 76543210 Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 B i t 76543210 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

A Flash program corruption can be caused by two situations when the voltage is too low. for executing instructions is too low.

1. Keep the AVR RESET active (low) during periods of insufficient power supply
2. Keep the AVR core in Power-down sleep mode during periods of low VCC . This

programming time for Flash accesses from the CPU. Table 41. SPM Programming Time

100 ATtiny13

This section describes the different methods for Programming the ATtiny13 memories. only be erased to “1” with the Chip Erase command. should always debugWIRE be disabled by clearing the DWEN fuse. Notes: 1. Program the Fuse bits before programming the LB1 and LB2.

1. “1” means unprogrammed, “0” means programmed

Table 42. Lock Bit Byte(1) Table 43. Lock Bit Protection Modes(1)(2) 1 1 1 No memory lock features enabled. disabled in High-voltage and Serial Programming mode. Serial and High-voltage Programming mode.

read as logical zero, “0”, if they are programmed. Notes: 1. See Table 13 on page 32 for BODLEVEL Fuse decoding.

1. See “Alternate Functions of Port B” on page 49 for description of RSTDISBL and
2. DWEN must be unprogrammed when Lock Bit security is required. See “Program

And Data Memory Lock Bits” on page 100.

1. When programming the RSTDISBL Fuse, High-voltage Serial programming has to be

used to change fuses to perform further programming. Notes: 1. The SPIEN Fuse is not accessible in SPI Programming mode.

1. See “Watchdog Timer Control Register - WDTCR” on page 37 for details.
2. The default value of SUT1..0 results in maximum start-up time for the default clock

source. See Table 5 on page 22 for details. Table 4 on page 22 for details.

1. See “System Clock Prescaler” on page 24 for details.

Table 44. Fuse High Byte Table 45. Fuse Low Byte

102 ATtiny13

are also latched on Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. the device is locked. The three bytes reside in a separate address space.

1. 0x000: 0x1E (indicates manufactured by Atmel).
2. 0x001: 0x90 (indicates 1 KB Flash memory).
3. 0x002: 0x07 (indicates ATtiny13 device when 0x001 is 0x90).

Table 46. No. of Words in a Page and No. of Pages in the Flash Table 47. No. of Words in a Page and No. of Pages in the EEPROM

the SPI pins dedicated for the internal SPI interface. Figure 53. Serial Programming and Verify location in both the Program and EEPROM arrays into 0xFF. Table 48. Pin Mapping Serial Programming

104 ATtiny13

2535B–AVR–01/04 Serial Programming Algorithm When writing serial data to the ATtiny13, data is clocked on the rising edge of SCK. When reading data from the ATtiny13, data is clocked on the falling edge of SCK. See Figure 54 and Figure 55 for timing details. To program and verify the ATtiny13 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 50): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Program- ming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 3 MSB of the address. If polling is not used, the user must wait at least t WD_FLASH before issuing the next page. (See Table 49.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least t WD_EEPROM before issuing the next byte. (See Table 49.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Mem- ory Page is stored by loading the Write EEPROM Memory Page Instruction with the 4 MSB of the address. When using EEPROM page access only byte loca- tions loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling is not used, the used must wait at least t WD_EEPROM before issuing the next page (See Table 47). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Tur n VCC power off.

skipped. See Table 49 for tWD_FLASH value. locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re-programmed without chip erasing the device. Figure 54. Serial Programming Waveforms Table 49. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

106 ATtiny13

Table 50. Serial Programming Instruction Set Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxxChip Erase EEPROM and Flash. Program memory at word address a:b. Write EEPROM page at address b. Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo ooooRead Signature Byte o at address b. Table 36 on page 82 for details. “0” before applying another command.

Figure 55. Serial Programming Timing Data memory, Lock bits and Fuse bits in the ATtiny13. Table 51. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 - 5.5V

108 ATtiny13

Figure 56. High-voltage Serial Programming Table 52. Pin Name Mapping Table 53. Pin Values Used to Enter Programming Mode

1. Apply 4.5 - 5.5V between VCC and GND.
2. Set RESET pin to “0” and toggle SCI at least six times.
3. Set the Prog_enable pins listed in Table 53 to “000” and wait at least 100 ns.
4. Shortly after latching the Prog_enable signature, the device will actively output
5. Wait at least 50 µs before giving any serial instructions on SDI/SII.

efficient programming, the following should be considered. the EESAVE Fuse is programmed) and Flash after a Chip Erase.

1. Load command “Chip Erase” (see Table 55).
2. Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish.
3. Load Command “No Operation”.

Table 54. High-voltage Reset Characteristics

110 ATtiny13

1. Load Command “Write Flash” (see Table 55).
2. Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes

high for the “Page Programming” cycle to finish.

1. Repeat 2 through 3 until the entire Flash is programmed or until all data has
2. End Page Programming by Loading Command “No Operation”.

the serial clock, see Figure 58, Figure 59 and Table 56 for details. Figure 57. Addressing the Flash which is Organized in Pages Figure 58. High-voltage Serial Programming Waveforms

2535B–AVR–01/04 Programming the EEPROM The EEPROM is organized in pages, see Table 51 on page 107. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data mem- ory is as follows (refer to Table 55): 1. Load Command “Write EEPROM”. 2. Load EEPROM Page Buffer. 3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Programming” cycle to finish. 4. Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. Reading the Flash The algorithm for reading the Flash memory is as follows (refer to Table 55): 1. Load Command "Read Flash". 2. Read Flash Low and High Bytes. The contents at the selected address are avail- able at serial output SDO. Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to Table 55): 1. Load Command “Read EEPROM”. 2. Read EEPROM Byte. The contents at the selected address are available at serial output SDO. Programming and Reading the Fuse and Lock Bits The algorithms for programming and reading the Fuse Low/High bits and Lock bits are shown in Table 55. Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in Table 55. Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn VCC power off.

112 ATtiny13

Table 55. High-voltage Serial Programming Instruction Set for ATtiny13 Enter Flash Programming code. Flash or all data is programmed.

Notes: 1. For page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address.

1. For page sizes less than 256 bytes, parts of the address (bbbb_bbbb) will be parts of the page address.
2. The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM.

of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming. Table 55. High-voltage Serial Programming Instruction Set for ATtiny13 (Continued)

114 ATtiny13

Figure 59. High-voltage Serial Programming Timing Table 56. High-voltage Serial Programming Characteristics VCC = 5.0V ± 10% (Unless

2535B–AVR–01/04

Electrical Characteristics

Absolute Maximum Ratings* DC Characteristics Notes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrol- lers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon. 2. “Max” means the highest value where the pin is guaranteed to be read as low. Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on any Pin except RESET TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) Symbol Parameter Condition Min. Typ. Max. Units VIL Input Low Voltage -0.5 0.2V CC V VIH Input High-voltage Except RESET pin 0.6V CC (3) VCC +0.5 V VIH2 Input High-voltage RESET pin 0.9V CC (3) VCC +0.5 V VOL Output Low Voltage(4) (Port B) IOL = 10 mA, VCC = 5V IOL = 5 mA, VCC = 3V 0.7 0.5 V V VOH Output High-voltage(5) (Port B) IOH = -10 mA, VCC = 5V IOH = -5 mA, VCC = 3V 4.2 2.5 V V IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low (absolute value) 1µ A IIH Input Leakage Current I/O Pin Vcc = 5.5V, pin high (absolute value) 1µ A R RST Reset Pull-up Resistor 30 80 k Ω R pu I/O Pin Pull-up Resistor 20 50 k Ω ICC Power Supply Current Active 1MHz, VCC = 2V 0.55 mA Active 4MHz, VCC = 3V 3.5 mA Active 8MHz, VCC = 5V 12 mA Idle 1MHz, VCC = 2V 0.08 0.25 mA Idle 4MHz, VCC = 3V 0.41 1.5 mA Idle 8MHz, VCC = 5V 1.6 5.5 mA Power-down mode WDT enabled, VCC = 3V < 5 16 µA WDT disabled, VCC = 3V < 0.5 8 µA

116 ATtiny13

1. “Min” means the lowest value where the pin is guaranteed to be read as high.
2. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state

1] The sum of all IOL, for all ports, should not exceed 60 mA. than the listed test condition.

1. Although each I/O port can source more than the test conditions (10 mA at V

1] The sum of all IOH, for all ports, should not exceed 60 mA. greater than the listed test condition. Figure 60. External Clock Drive Waveforms CC = 3V, maximum frequency will be 14 MHz. Table 57. External Clock Drive

Thus, a maximum frequency of 19 MHz requires VCC = 3.75 V. Figure 61. Maximum Frequency vs. VCC , ATtiny13V Figure 62. Maximum Frequency vs. VCC , ATtiny13

12 MHz

6 MHz

24 MHz

118 ATtiny13

Notes: 1. Values are preliminary. Table 58. ADC Characteristics, Single Ended Channels. -40°C - 85°C

1.5 LSB

2.5 LSB

0.5 LSB

2535B–AVR–01/04 ATtiny13 Typical Characteristics – Preliminary Data The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail- to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as C L*VCC *f where CL = load capacitance, VCC = operating voltage and f = average switch- ing frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaran- teed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif- ferential current drawn by the Watchdog Timer. Active Supply Current Figure 63. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0.2 0.4 0.6 0.8 1.2 Frequency (MHz) ICC (mA)

120 ATtiny13

Figure 64. Active Supply Current vs. Frequency (1 - 24 MHz) Figure 65. Active Supply Current vs. VCC (Internal RC Oscillator, 9.6 MHz)

122 ATtiny13

Figure 68. Active Supply Current vs. VCC (32 kHz External Clock)

124 ATtiny13

Figure 72. Idle Supply Current vs. VCC (Internal RC Oscillator, 4.8 MHz) Figure 73. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)

126 ATtiny13

Figure 76. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)

128 ATtiny13

Figure 80. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)

130 ATtiny13

Figure 84. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 5V) Figure 85. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 2.7V)

132 ATtiny13

Figure 88. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) Figure 89. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V)

134 ATtiny13

Figure 92. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) Figure 93. Reset Pin as I/O - Source Current vs. Output Voltage (VCC = 5V)

136 ATtiny13

Figure 96. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 5V) Figure 97. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 2.7V)

138 ATtiny13

Figure 100. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as '0') Figure 101. I/O Pin Input Hysteresis vs. VCC

140 ATtiny13

Figure 104. Reset Pin as I/O - Pin Hysteresis vs. VCC Figure 105. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as '1')

142 ATtiny13

Figure 108. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) Figure 109. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)

144 ATtiny13

Figure 112. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) Figure 113. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V)

Figure 115. Calibrated 9.6 MHz RC Oscillator Frequency vs. VCC

146 ATtiny13

Figure 116. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value Figure 117. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature

148 ATtiny13

Figure 120. 128 kHz Watchdog Oscillator Frequency vs. VCC Figure 121. 128 kHz Watchdog Oscillator Frequency vs. Temperature

150 ATtiny13

Figure 124. Analog Comparator Current vs. VCC Figure 125. Programming Current vs. VCC

152 ATtiny13

Figure 128. Reset Pulse Width vs. VCC

2535B–AVR–01/04 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F SREG I T H S V N Z C page 6 0x3D SPL SP[7:0] page 8 0x3C Reserved – 0x3B GIMSK – INT0 PCIE – – – – – page 53 0x3A GIFR –I N T F 0 P C I F – – – – – page 53 0x39 TIMSK0 – – – – OCIE0B OCIE0A TOIE0 – page 70 0x38 TIFR0 – – – – OCF0B OCF0A TOV0 – page 71 0x37 SPMCSR – – – CTPB RFLB PGWRT PGERS SELFPRGEN page 97 0x36 OCR0A Timer/Counter – Output Compare Register A page 70 0x35 MCUCR – PUD SE SM1 SM0 – ISC01 ISC00 page 49 0x34 MCUSR – – – – WDRF BORF EXTRF PORF page 33 0x33 TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 page 66 0x32 TCNT0 Timer/Counter (8-bit) page 70 0x31 OSCCAL Oscillator Calibration Register page 22 0x30 Reserved 0x2F TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 page 69 0x2E DWDR DWDR[7:0] page 94 0x2D Reserved – 0x2C Reserved – 0x2B Reserved – 0x2A Reserved – 0x29 OCR0B Timer/Counter – Output Compare Register B page 70 0x28 GTCCR TSM 0x27 Reserved – 0x26 CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 24 0x25 Reserved – 0x24 Reserved – 0x23 Reserved – 0x22 Reserved – 0x21 WDTCR WDTIF WDTIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 37 0x20 Reserved 0x1F Reserved – 0x1E EEARL – – EEPROM Address Register page 14 0x1D EEDR EEPROM Data Register page 14 0x1C EECR – – EEPM1 EEPM0 EERIE EEMWE EEWE EERE page 15 0x1B Reserved – 0x1A Reserved – 0x19 Reserved – 0x18 PORTB – – PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 51 0x17 DDRB – – DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 51 0x16 PINB – – PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 51 0x15 PCMSK – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 page 54 0x14 DIDR0 – – ADC0D ADC2D ADC3D ADC1D EIN1D AIN0D page 76, page 91 0x13 Reserved – 0x12 Reserved – 0x11 Reserved – 0x10 Reserved – 0x0F Reserved – 0x0E Reserved – 0x0D Reserved – 0x0C Reserved – 0x0B Reserved – 0x0A Reserved – 0x09 Reserved – 0x08 ACSR ACD ACBG ACO ACI ACIE – ACIS1 ACIS0 page 74 0x07 ADMUX – REFS0 ADLAR – – – MUX1 MUX0 page 88 0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 89 0x05 ADCH ADC Data Register High Byte page 90 0x04 ADCL ADC Data Register Low Byte page 90 0x03 ADCSRB –A C M E – – – ADTS2 ADTS1 ADTS0 page 91 0x02 Reserved – 0x01 Reserved – 0x00 Reserved –

154 ATtiny13

2535B–AVR–01/04 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

2535B–AVR–01/04 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • KZ , N , V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← ZN o n e 3 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1N o n e 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0N o n e 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0) ← C,Rd(n+1)← Rd(n),C← Rd(7) Z,C,N,V 1

156 ATtiny13

2535B–AVR–01/04 ROR Rd Rotate Right Through Carry Rd(7) ← C,Rd(n)← Rd(n+1),C← Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 BSET s Flag Set SREG(s) ← 1S R E G ( s ) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← TN o n e 1 SEC Set Carry C ← 1C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1Z 1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1S 1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Twos Complement Overflow. V ← 1V 1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← KN o n e 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 SPM Store Program Memory (z) ← R1:R0 None IN Rd, P In Port Rd ← PN o n e 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1 BREAK Break For On-chip Debug Only None N/A Mnemonics Operands Description Operation Flags #Clocks

2535B–AVR–01/04

Ordering Information

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative. 3. For Speed vs. V CC , see “Maximum Speed vs. VCC” on page 116. Power Supply Speed (MHz) Ordering Code Package (1) Operation Range 12(3) 1.8 - 5.5 ATtiny13-12PI ATtiny13-12PJ(2) ATtiny13-12SI ATtiny13-12SJ (2) ATtiny13-12SSI ATtiny13-12SSJ (2) 8P3 8P3 8S2 8S2 S8S1 S8S1 Industrial (-40°C to 85°C) (3) 2.7 - 5.5 ATtiny13-24PI ATtiny13-24PJ(2) ATtiny13-24SI ATtiny13-24SJ(2) ATtiny13-24SSI ATtiny13-24SSJ(2) 8P3 8P3 8S2 8S2 S8S1 S8S1 Industrial (-40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) S8S1 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)

158 ATtiny13

2535B–AVR–01/04 Packaging Information 8P3

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B D E e Lb2 b A2 A N eA c

4 PLCS

(Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. A 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2

2535B–AVR–01/04 8S2 San Jose, CA 95131 TITLE DRAWING NO. R REV. 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) 10/7/03 8S2 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs are not included. 3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. 4. Determines the true geometric position. A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 2, 3 E 7.70 8.26 L 0.51 0.85 ∅ 0˚ 8˚ e 1.27 BSC 4 End View Side View e b A D E N C L Top View

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2535B–AVR–01/04 S8S1 San Jose, CA 95131 TITLE DRAWING NO. R REV. S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline (JEDEC SOIC) 7/28/03 S8S1 A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. E 5.79 6.20 E1 3.81 3.99 A 1.35 1.75 A1 0.1 0.25 D 4.80 4.98 C 0.17 0.25 b 0.31 0.51 L 0.4 1.27 e 1.27 BSC o 8 o Top View Side View End View N C A b L e D E1 E

2535B–AVR–01/04 Errata The revision letter in this section refers to the revision of the ATtiny13 device. ATtiny13 Rev. C There are no known errata for this revision. ATtiny13 Rev. B  Wrong values read after Erase Only operation  High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail  Device may lock for further programming  debugWIRE communication not blocked by lock-bits  Watchdog Timer Interrupt disabled 1. Wrong values read after Erase Only operation At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00). Problem Fix/Workaround If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed. 2. High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail Writing to any of these locations and bits may in some occasions fail. Problem Fix/Workaround After a writing has been initiated, always observe the RDY/BSY signal. If the writing should fail, rewrite until the RDY/BSY verifies a correct writing. This will be fixed in revision C. 3. Device may lock for further programming Special combinations of fuse bits will lock the device for further programming effec- tively turning it into an OTP device. The following combinations of settings/fuse bits will cause this effect: – 128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. – 9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. – 4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. Problem fix/ Workaround Avoid the above fuse combinations. Selecting longer start-up time will eliminate the problem. 4. debugWIRE communication not blocked by lock-bits When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program memory and EEPROM data memory can be read even if the lock-bits are set to block further reading of the device.

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2535B–AVR–01/04 Problem fix/ Workaround Do not ship products with on-chip debug of the tiny13 enabled. 5. Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-out following an interrupt, the device works correctly. Problem fix / Workaround Make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. This is done by selecting a long enough time-out period. ATtiny13 Rev. A Revision A has not been sampled.

2535B–AVR–01/04 Datasheet Change Log for ATtiny13 Please note that the referring page numbers in this section are referring to this docu- ment. The referring revision in this section are referring to the document revision. Changes from Rev. 2535A-06/03 to Rev. 2535B-01/04 1. Updated Figure 2 on page 2. 2. Updated Table 12 on page 30, Table 17 on page 39, Table 37 on page 89 and Table 57 on page 116. 3. Updated “Calibrated Internal RC Oscillator” on page 22. 4. Updated the whole “Watchdog Timer” on page 35. 5. Updated Figure 53 on page 103 and Figure 56 on page 108. 6. Updated registers “MCU Control Register – MCUCR” on page 49, “Timer/Counter Control Register B – TCCR0B” on page 69 and “Digital Input Disable Register 0 – DIDR0” on page 76. 7. Updated Absolute Maximum Ratings and DC Characteristics in “Electrical Characteristics” on page 115. 8. Added “Maximum Speed vs. VCC” on page 116 9. Updated “ADC Characteristics – Preliminary Data” on page 118. 10. Updated “ATtiny13 Typical Characteristics – Preliminary Data” on page 119. 11. Updated “Ordering Information” on page 157. 12. Updated “Packaging Information” on page 158. 13. Updated “Errata” on page 161. 14. Changed instances of EEAR to EEARL.

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2535B–AVR–01/04 Maximum Speed vs. V

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