ATSAM3S ATMEL | Alldatasheet
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Technical content
Features
- Core – ARM ® Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit (MPU) –T h u m b®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, single plane – From 16 to 48 Kbytes embedded SRAM – 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines – 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support – Memory Protection Unit (MPU) System – Embedded voltage regulator for single supply operation – Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation – Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low power 32.768 kHz for RTC or device clock – High precision 8/12 MHz factory trimmed inte rnal RC oscillator with 4 MHz default frequency for device startup. In-application trimming access for frequency adjustment – Slow Clock Internal RC oscillator as permanent low-power mode device clock – Two PLLs up to 130 MHz for device clock and for USB – Temperature Sensor – Up to 22 peripheral DMA (PDC) channels Low Power Modes – Sleep and Backup modes, down to 3 µA in Backup mode – Ultra low power RTC Peripherals – USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip Transceiver – Up to 2 USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode – Two 2-wire UARTs – Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller (I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC) – Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor – 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control – 32-bit Real-time Timer and RTC with calendar and alarm features – Up to 15-channel, 1Msps ADC with differential input mode and programmable gain stage – One 2-channel 12-bit 1Msps DAC – One Analog Comparator with flexible input selection, window mode, Selectable input hysteresis – 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU) I/O – Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination – Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel Capture Mode Packages – 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm / 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm – 64-lead LQFP, 12 x 12 mm, pitch 0.5 mm / 64-pad QFN 9x9 mm, pitch 0.45 mm – 48-lead LQFP, 9 x 9 mm, pitch 0.5 mm / 48-pad QFN 7x7 mm, pitch 0.45 mm AT91 ARM Cortex M3-based Processor ATSAM3S Series Preliminary Summary 6500AS–ATARM–11-Dec-09
6500AS–ATARM–11-Dec-09 SAM3S Summary 1. SAM3S Description Atmel's SAM3S series is a member of a family of Flash microcontrollers based on the high per- formance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 64 MHz and features up to 256 Kbytes of Flash and up to 48 Kbytes of SRAM. The peripheral set includes a Full Speed USB Device port with embedded transceiver, a High Speed MCI for SDIO/SD/MMC, an External Bus Interface featur ing a Static Memory Controller providing con- nection to SRAM, PSRAM, NOR Flash, LCD Modu le and NAND Flash, 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, an I2S, as well as 1 PWM timer, 6x general-purpose 16-bit timers, an RTC, a ADC, a 12-bit DAC and an analog comparator. The SAM3S series is ready for capacitive touch thanks to the QTouch library, offering an easy way to implement buttons, wheels and sliders The SAM3S device is a medium range general purpose microcontroller with the best ratio in terms of reduced power consumption, processing power and peripheral set. This enables the SAM3S able to sustain a wide range of applications including consumer, industrial control, and PC peripherals. It operates from 1.62V to 3.6V and is available in 48-, 64- and 100-pin QFP, 48- and 64-pin QFN, and 100-pin BGA packages. The SAM3S series is the ideal migration path from the SAM7S series for applications that require more performance. The SAM3S series is pin-to-pin compatible with the SAM7Sseries.
1.1 Configuration Summary
The SAM3S series devices differ in memory size, package and features list. Table 1-1 below summarizes the configurations of the device family Note: 1. Full Modem support on USART1. Table 1-1. Configuration Summary Device Flash SRAM Timer Counter Channels GPIOs UART/ USARTs ADC 12-bit DAC Output External Bus Interface HSMCI Package SAM3S4C 256 Kbytes single plane 48 Kbytes 6 79 2/2 (1) 16 ch. 2 8-bit data, 4 chip selects, 24-bit address 1 port 4 bits LQFP100 BGA100 SAM3S4B 256 Kbytes single plane 48 Kbytes 3 47 2/2 10 ch. 2 - 1 port 4 bits LQFP64 QFN 64 SAM3S4A 256 Kbytes single plane 48 Kbytes 3 34 2/1 8 ch. - - - LQFP48 QFN 48 SAM3S2C 128 Kbytes single plane 32 Kbytes 6 79 2/2 (1) 16 ch. 2 8-bit data, 4 chip selects, 24-bit address 1 port 4 bits LQFP100 BGA100 SAM3S2B 128 Kbytes single plane 32 Kbytes 3 47 2/2 10 ch. 2 - 1 port 4 bits LQFP64 QFN 64 SAM3S2A 128 Kbytes single plane 32 Kbytes 3 34 2/1 8 ch. - - - LQFP48 QFN 48 SAM3S1C 64 Kbytes single plane 16 Kbytes 6 79 2/2 (1) 16 ch. 2 8-bit data, 4 chip selects, 24-bit address 1 port 4 bits LQFP100 BGA100 SAM3S1B 64 Kbytes single plane 16 Kbytes 3 47 2/2 10 ch. 2 - 1 port 4 bits LQFP64 QFN 64 SAM3S1A 64 Kbytes single plane 16 Kbytes 3 34 2/1 8 ch. - - - LQFP48 QFN 48
6500AS–ATARM–11-Dec-09 SAM3S Summary 2. SAM3S Block Diagram Figure 2-1. SAM3S 100-pin Version Block Diagram PLLA TST PCK0-PCK2 System C ontroller XIN NRST VDDCORE X OUT WDT RTT OSC 32kXIN32 X OUT32 SUPC RSTC
8 GPBREG
Osc. POR RT C RC 32k SM RC 12/8/4 M ERASE TDITDOTM S/SWDIO TCK/ SWCLK JTAGSEL I/D S Vo l tage Regulator VDDIN VDDOUT SPI T C[0..2] DAC ADVREF PDC NPCS0 PIODCCLK PIODCEN1 PIODCEN2 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK MCDA[0..3] MCCDA MCCK TCLK[0:2] Temp. Sensor PDC TWI0 PDCTWD0 PWM PDC TF TK TD RD RK RF DDP DDM MPU N V I C 24-Bit SysTick Counter 4-layer AHB Bus Matrix Fmax 64 MHz TWI1 PDCTWCK1 TWD1 PWMH[0:3] PWML[0:3] PWMFI0 PDC UART0 UART1 URXD0 UTXD0 UR XD1 UTXD1 SSC P eripheral Bridge PDC PIO PDC PDC 2668 Bytes FIFO USB 2.0 Full Speed VDDPLL VDDIO PDC RXD0 TXD0 USART0SCK0 RTS0 CTS0 Analog Comparator CRC Unit ADC Transceiver PLLB In-Circuit Emulator JTAG & Serial Wire Flash Unique Identifier PMC PIOA / PIOB / PIOC ADTRG Cortex-M3 Processor Fmax 64 MHz Timer Counter A Timer Counter B TWCK0 FLASH
256 KBytes
128 KBytes
64 KBytes
48 KBytes
32 KBytes
16 KBytes
D[7:0] PIODC[7:0] A[0:23] A21/NANDALE A22/NANDCLE NCS0 NCS1 NCS2 NCS3 NRD NWE NANDOE NANDWE NWAIT High Speed MCI PDC DATRG PDC DAC0 DAC1 TC [3..5] TIOA[3:5] TIOB[3:5] TIOA[0:2] TIOB[0:2] TCLK[3:5] AD[0..14] PDC RXD1 TXD1 USART1 SCK1 RTS1 CTS1 DSR1 DTR1 RI1 DCD1 NAND Flash Logic Static Memory Controller ADC DAC Temp Sensor ADVREF
6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 2-2. SAM3S 64-pin Version Block Diagram TDI TDOTM S/SWDIO TCK/ SWCLK JTA GSEL I/D S Vo l tage Regulator VDDIN VDDOU T SPI T C[0..2] ADVREF TIOB[0:2] TIOA[0:2] TCLK[0:2] PDC TWI0 PDC TWCK0 PWM PDC TF TK TD RD RK RF DDP DDM Transceiver MPU N V I C TWI1 PDCTWD1 PWMH[0:3] PWMFI0 PDC UART0 UART1 URXD0 UTXD0 URXD1 UTXD1 SSC Peripheral Bridge PDC PDC 2668 Bytes FIFO USB 2.0 Full Speed PDC RXD0 TXD0 USART0SCK0 RTS0 CTS0 PLLA TST PCK0-PCK2 System C ontroller XIN NRST VDDCORE XOUT WDT RTT OSC 32KXIN32 XOUT32 SUPC RSTC Osc. POR RTC RC 32k SM RC 12/8/4 M ERASE VDDPLL VDDIO PLLB PMC PIOA / PIOB JTAG & Serial Wire Flash Unique Identifier PIODCCLK PIODCEN1 PIODCEN2PIO PDC PIODC[7:0] Analog Comparator CRC Unit ADC DAC Temp Sensor ADVREF NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK MCCK MCCDA MCDA[0..3] High Speed MCI Cortex-M3 Processor Fmax 64 MHz In-Circuit Emulator Timer Counter A ROM PWML[0:3] 24-Bit SysTick Counter FLASH AD[0..8] ADTRG DATRG PDC RXD1 TXD1 USART1 SCK1 RTS1 CTS1 DSR1 DTR1 RI1 DCD1 4-layer AHB Bus Matrix Fmax 64 MHz DAC PDC Temp. Sensor ADC PDC
6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 2-3. SAM3S 48-pin Version Block Diagram TDI TDOTM S/SWDIO T CK/ SWCLK JTAGSEL I/D S V oltage Regulator VDDIN VDDOUT SPI T C[0..2] ADVREF TIOA[0:2] TIOB[0:2] TCLK[0:2] PDC TWI0 PDC TWCK0 TWD0 PWM PDC TF TK TD RD RK RF DDP DDM Transceiver MPU N V I C TWI1 PDC TWCK1 TWD1 PWMH[0:3] PWML[0:3] PWMFI0 PDC UART0 UART1 URXD0 UTXD0 URXD1 UTXD1 SSC Peripheral Bridge PDC PDC 2668 Bytes FIFO USB 2.0 Full Speed PDC RXD0 TXD0 USART0SCK0 RTS0 CTS0 PLLA System C ontroller WDT RTT OSC32K SUPC RSTC Osc. POR RTC RC 32k SM RC 12/8/4 M PLLB PMC PIOA / PIOB JTAG & Serial Wire Flash Unique Identifier Analog Comparator CRC Unit ADC Temp Sensor ADVREF NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK Cortex-M3 Processor Fmax 64 MHz Timer Counter A ROM AD[0..7] ADTRG 4-layer AHB Bus Matrix Fmax 64 MHz PDC Temp. Sensor ADC
6500AS–ATARM–11-Dec-09 SAM3S Summary 3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Description List Signal Name Function Type Active Level Voltage reference Comments Power Supplies VDDIO Peripherals I/O Lines and USB transceiver Power Supply Power 1.62V to 3.6V VDDIN Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply Power 1.8V to 3.6V (4) VDDOUT Voltage Regulator Output Power 1.8V Output VDDPLL Oscillator and PLL Power Supply Power 1.62 V to 1.95V VDDCORE Power the core, the embedded memories and the peripherals Power 1.62V to 1.95V GND Ground Ground Clocks, Oscillators and PLLs XIN Main Oscillator Input Input VDDIO Reset State: - PIO Input - Internal Pull-up disabled - Schmitt Trigger enabled(1) XOUT Main Oscillator Output Output XIN32 Slow Clock Oscillator Input Input XOUT32 Slow Clock Oscillator Output Output PCK0 - PCK2 Programmable Clock Output Output Reset State: - PIO Input - Internal Pull-up enabled - Schmitt Trigger enabled (1) Serial Wire/JTAG Debug Port - SWJ-DP TCK/SWCLK Test Clock/Se rial Wire Clock Input VDDIO Reset State: - SWJ-DP Mode - Internal pull-up disabled - Schmitt Trigger enabled(1) TDI Test Data In Input TDO/TRACESWO Test Data Out / Trace Asynchronous Data Out Output TMS/SWDIO Test Mode Select /Seria l Wire Input/Output Input / I/O JTAGSEL JTAG Selection Input High Permanent Internal pull-down Flash Memory ERASE Flash and NVM Configuration Bits Erase Command Input High VDDIO Reset State: - Erase Input - Internal pull-down enabled - Schmitt Trigger enabled (1) Reset/Test NRST Synchronous Microcontroller Reset I/O Low VDDIO Permanent Internal pull-up TST Test Select Input Permanent Internal pull-down
6500AS–ATARM–11-Dec-09 SAM3S Summary Universal Asynchronous Receiver Transmitter - UARTx URXDx UART Receive Data Input UTXDx UART Transmit Data Output PIO Controller - PIOA - PIOB - PIOC PA0 - PA31 Parallel IO Controller A I/O VDDIO Reset State: - PIO or System IOs (2) - Internal pull-up enabled - Schmitt Trigger enabled (1) PB0 - PB14 Parallel IO Controller B I/O PC0 - PC31 Parallel IO Controller C I/O PIO Controller - Parallel Capture Mode (PIOA Only) PIODC0-PIODC7 Parallel Capture Mode Data Input VDDIOPIODCCLK Parallel Capture Mode Clock Input PIODCEN1-2 Parallel Capture Mode Enable Input External Bus Interface D0 - D7 Data Bus I/O A0 - A23 Address Bus Output NWAIT External Wait Signal Input Low Static Memory Controller - SMC NCS0 - NCS3 Chip Select Lines Output Low NRD Read Signal Output Low NWE Write Enable Output Low NAND Flash Logic NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low High Speed Multimedia Card Interface - HSMCI MCCK Multimedia Card Clock I/O MCCDA Multimedia Card Slot A Command I/O MCDA0 - MCDA3 Multimedia Card Slot A Data I/O Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx USARTx Serial Clock I/O TXDx USARTx Transmit Data I/O RXDx USARTx Receive Data Input RTSx USARTx Request To Send Output CTSx USARTx Clear To Send Input DTR1 USART1 Data Terminal Ready I/O DSR1 USART1 Data Set Ready Input DCD1 USART1 Data Carrier Detect Input RI1 USART1 Ring Indicator Input Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage reference Comments
6500AS–ATARM–11-Dec-09 SAM3S Summary Synchronous Serial Controller - SSC TD SSC Transmit Data Output RD SSC Receive Data Input TK SSC Transmit Clock I/O RK SSC Receive Clock I/O TF SSC Transmit Frame Sync I/O RF SSC Receive Frame Sync I/O Timer/Counter - TC TCLKx TC Channel x External Clock Input Input TIOAx TC Channel x I/O Line A I/O TIOBx TC Channel x I/O Line B I/O Pulse Width Modulation Controller- PWMC PWMHx PWM Waveform Output High for channel x Output PWMLx PWM Waveform Output Low for channel x Output only output in complementary mode when dead time insertion is enabled PWMFI0 PWM Fault Input Input Serial Peripheral Interface - SPI MISO Master In Slave Out I/O MOSI Master Out Slave In I/O SPCK SPI Serial Clock I/O SPI_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPI_NPCS1 - SPI_NPCS3 SPI Peripheral Chip Select Output Low Two-Wire Interface- TWI TWDx TWIx Two-wire Serial Data I/O TWCKx TWIx Two-wire Serial Clock I/O Analog ADVREF ADC, DAC and Analog Comparator Reference Analog Analog-to-Digital Converter - ADC AD0 - AD14 Analog Inputs Analog, Digital ADTRG ADC Trigger Input VDDIO 12-bit Digital-to-Analog Converter - DAC DAC0 - DAC1 Analog output Analog, Digital DACTRG DAC Trigger Input VDDIO Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage reference Comments
6500AS–ATARM–11-Dec-09 SAM3S Summary Notes: 1. Schmitt Triggers can be disabled through PIO registers. 2. Some PIO lines are shared with System IOs. 3. Refer to the USB sub section in the product Electrical Characteristics Section for Pull-down value in USB Mode. 4. See Section 5.3 “Typical Powering Schematics” for restriction on voltage range of Analog Cells. Fast Flash Programming Interface - FFPI PGMEN0-PGMEN2 Programming Enabling Input VDDIO PGMM0-PGMM3 Programming Mode Input VDDIO PGMD0-PGMD15 Programming Data I/O PGMRDY Programming Ready Output High PGMNVALID Data Direction Output Low PGMNOE Programming Read Input Low PGMCK Programming Clock Input PGMNCMD Programming Command Input Low USB Full Speed Device DDM USB Full Speed Data - Analog, Digital VDDIO Reset State: - USB Mode - Internal Pull-down (3)DDP USB Full Speed Data + Table 3-1. Signal Description List (Continued) Signal Name Function Type Active Level Voltage reference Comments
6500AS–ATARM–11-Dec-09 SAM3S Summary 4. Package and Pinout
4.1 SAM3S4/2/1C Package and Pinout
Figure 4-2 shows the orientation of the 100-ball LFBGA Package The 100-ball LFBGA pinout will be specified as soon as the first layout of the device is completed. 4.1.1 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 4.1.2 100-ball LFBGA Package Outline The 100-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimen- sions are 9 x 9 x 1.1 mm. Figure 4-2. Orientation of the 100-BALL LFBGA Package 12 5 5175 100 ABCDEFGHJK TOP VIEW BALL A1
6500AS–ATARM–11-Dec-09 SAM3S Summary 4.1.3 100-Lead LQFP Pinout Table 4-1. 100-lead LQFP SAM3S4/2/1C Pinout
1 ADVREF 26 GND 51 TDI/PB4 76 TDO/TRACESWO/
2 GND 27 VDDIO 52 PA6/PGMNOE 77 JTAGSEL
3 PB0/AD4 28 PA16/PGMD4 53 PA5/PGMRDY 78 PC18
4 PC29/AD13 29 PC7 54 PC28 79 TMS/SWDIO/PB6
5 PB1/AD5 30 PA15/PGMD3 55 PA4/PGMNCMD 80 PC19
6 PC30/AD14 31 PA14/PGMD2 56 VDDCORE 81 PA31
7 PB2/AD6 32 PC6 57 PA27 82 PC20
8 PC31 33 PA13/PGMD1 58 PC8 83 TCK/SWCLK/PB7
9 PB3/AD7 34 PA24 59 PA28 84 PC21
10 VDDIN 35 PC5 60 NRST 85 VDDCORE
11 VDDOUT 36 VDDCORE 61 TST 86 PC22
12 PA17/PGMD5/
AD0 37 PC4 62 PC9 87 ERASE/PB12
13 PC26 38 PA25 63 PA29 88 DDM/PB10
14 PA18/PGMD6/
AD1 39 PA26 64 PA30 89 DDP/PB11
15 PA21/AD8 40 PC3 65 PC10 90 PC23
16 VDDCORE 41 PA12/PGMD0 66 PA3 91 VDDIO
17 PC27 42 PA11/PGMM3 67 PA2/PGMEN2 92 PC24
18 PA19/PGMD7/
AD2 43 PC2 68 PC11 93 PB13/DAC0
19 PC15/AD11 44 PA10/PGMM2 69 VDDIO 94 PC25
20 PA22/AD9 45 GND 70 GND 95 GND
21 PC13/AD10 46 PA9/PGMM1 71 PC14 96 PB8/XOUT
22 PA23 47 PC1 72 PA1/PGMEN1 97 PB9 /PGMCK/XIN
23 PC12/AD12 48 PA8/XOUT32/
24 PA20/AD3 49 PA7/XIN32/
PGMNVALID 74 PA0/PGMEN0 99 PB14/DAC1
25 PC0 50 VDDIO 75 PC17 100 VDDPLL
6500AS–ATARM–11-Dec-09 SAM3S Summary 4.1.4 100-ball LFBGA Pinout Table 4-2. 100-ball LFBGA SAM3S4/2/1C Pinout (To be Provided) A10 B10
6500AS–ATARM–11-Dec-09 SAM3S Summary
4.2 SAM3S4/2/1B Package and Pinout
Figure 4-3. Orientation of the 64-pad QFN Package Figure 4-4. Orientation of the 64-lead LQFP Package 17 32 4964 TOP VIEW 161
6500AS–ATARM–11-Dec-09 SAM3S Summary 4.2.1 64-Lead LQFP and QFN Pinout 64-pin version SAM3S devices are pin-to-pin compatible with AT91SAM7S legacy products. Furthermore, SAM3S products have new functionalities shown in italic in Table 4-3. Note: The bottom pad of the QFN pac kage must be connected to ground. Table 4-3. 64-pin SAM3S4/2/1B Pinout
1 ADVREF 17 GND 33 TDI/PB4 49 TDO/TRACESWO/PB5
2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL
3 PB0/AD4 19 PA16/PGMD4 35 PA 5/PGMRDY 51 TMS/SWDIO/PB6
4 PB1/AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31
5 PB2/AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK/SWCLK/PB7
6 PB3/AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE
7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE/PB12
8 VDDOUT 24 VDDCORE 40 TST 56 DDM/PB10
9 PA17/PGMD5/
AD0 25 PA25/PGMD13 41 PA29 57 DDP/PB11
10 PA18/PGMD6/
AD1 26 PA26/PGMD14 42 PA30 58 VDDIO
11 PA21/PGMD9/
AD8 27 PA12/PGMD0 43 PA3 59 PB13/DAC0
12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND
13 PA19/PGMD7/
AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT/PB8
14 PA22/PGMD10/
AD9 30 PA9/PGMM1 46 GND 62 XIN/PGMCK/PB9
15 PA23/PGMD11 31 PA8/XOUT32/
PGMM0 47 PA1/PGMEN1 63 PB14/DAC1
16 PA20/PGMD8/
PGMNVALID 48 PA0/PGMEN0 64 VDDPLL
6500AS–ATARM–11-Dec-09 SAM3S Summary
4.3 SAM3S4/2/1A Package and Pinout
Figure 4-5. Orientation of the 48-pad QFN Package Figure 4-6. Orientation of the 48-lead LQFP Package 13 24 3748 TOP VIEW 121
6500AS–ATARM–11-Dec-09 SAM3S Summary 4.3.1 48-Lead LQFP and QFN Pinout Note: The bottom pad of the QFN pac kage must be connected to ground. Table 4-4. 48-pin SAM3S4/2/1A Pinout
1 ADVREF 13 VDDIO 25 TDI/PB4 37 TDO/TRACESWO/
2 GND 14 PA16/PGMD4 26 PA6/PGMNOE 38 JTAGSEL
3 PB0/AD4 15 PA15/PGMD3 27 PA5/PGMRDY 39 TMS/SWDIO/PB6
4 PB1/AD5 16 PA14/PGMD2 28 PA4/PGMNCMD 40 TCK/SWCLK/PB7
5 PB2/AD6 17 PA13/PGMD1 29 NRST 41 VDDCORE
6 PB3/AD7 18 VDDCORE 30 TST 42 ERASE/PB12
7 VDDIN 19 PA12/PGMD0 31 PA3 43 DDM/PB10
8 VDDOUT 20 PA11/PGMM3 32 PA2/PGMEN2 44 DDP/PB11
AD0 21 PA10/PGMM2 33 VDDIO 45 XOUT/PB8 AD1 22 PA9/PGMM1 34 GND 46 XIN/PB9/PGMCK
11 PA19/PGMD7/
PGMM0 35 PA1/PGMEN1 47 VDDIO
12 PA20/AD3 24 PA7/XIN32/
PGMNVALID 36 PA0/PGMEN0 48 VDDPLL
6500AS–ATARM–11-Dec-09 SAM3S Summary 5. Power Considerations
5.1 Power Supplies
The SAM3S product has several types of power supply pins: VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V and 1.95V. VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers); USB transceiver; Backup part, 32kHz crystal oscillator and oscillator pads; ranges from 1.62V and 3.6V VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply; Voltage ranges from 1.8V to 3.6V VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator; voltage ranges from 1.62V and 1.95V.
5.2 Voltage Regulator
The SAM3S embeds a voltage regulator that is managed by the Supply Controller. This internal regulator is intended to supply the internal core of SAM3S. It features two different operating modes: In Normal mode, the voltage regulator consumes less than 700 µA static current and draws 80 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. In Wait Mode quiescent current is only 7 µA. In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT) is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach Nor- mal mode is inferior to 100 µs. For adequate input and output power supply decoupling/bypassing, refer to the Voltage Regula- tor section in the Electrical Characteristics section of the datasheet.
5.3 Typical Powe ring Schematics
The SAM3S supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. Figure 5-1 shows the power schematics. As VDDIN powers the voltage re gulator, the ADC/DAC and the analog comparator, when the user does not want to use the embedded voltage regulator, it can be disabled by software via the SUPC (note that it is different from Backup mode).
6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 5-3. Backup Battery
5.4 Active Mode
Active mode is the normal running mode with the core clock runn ing from the fast RC oscillator, the main crystal oscillator or the PLLA. The po wer management controller can be used to adapt the frequency and to disable the peripheral clocks.
5.5 Low Power Modes
The various low power modes of the SAM3S are described below:
5.5.1 Backup Mode
The purpose of backup mode is to achieve the lo west power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time (<0.1ms). Total current consumption is 3 µA typical. The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. Backup mode is based on the Cortex-M3 deepsleep mode with the voltage regulator disabled. The SAM3S can be awakened from this mode through WUP0-15 pins, the supply monitor (SM), the RTT or RTC wake-up event. Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the System Con- trol Register of the Cortex-M3 set to 1. (See the Power management description in The ARM Cortex M3 Processor section of the product datasheet). Exit from Backup mode happens if one of the following enable wake up events occurs: ADC, DAC Analog Comp. USB Transceivers. VDDIN Voltage Regulator3.3V LDO Backup Battery + ON/OFF IN OUT VDDOUTMain Supply VDDCORE ADC, DAC, Analog Comparator Supply (2.4V-3.6V) VDDIO VDDPLL PIOx (Output) WAKEUPx External wakeup signal Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode.
6500AS–ATARM–11-Dec-09 SAM3S Summary WKUPEN0-15 pins (level transition, configurable debouncing) Supply Monitor alarm R T C a l a r m RTT alarm
5.5.2 Wait Mode
The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup ti me of less than 10 µs. Current Consumption in Wait mode is typically 15 µA (total current consum ption) if the internal voltage regulator is used or 8 µA if an external regulator is used. In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and memories power supplies are still powered. From this mode, a fast start up is available. This mode is entered via Wait for Event (WFE) instructions with LPM = 1 (Low Power Mode bit in PMC_FSMR). The Cortex-M3 is able to handle external events or internal events in order to wake-up the core (WFE). By configuring the external lines WUP0-15 as fast startup wake-up pins (refer to Section 5.7 “Fast Startup”). RTC or RTT Alarm and USB wake-up events can be used to wake up the CPU (exit from WFE). Entering Wait Mode: Select the 4/8/12 MHz fast RC oscillator as Main Clock Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR) Execute the Wait-For-Event (WFE) instruction of the processor Note: Internal Main cloc k resynchronization cycles are necessary between the writing of MOSCRCEN bit and the effective entry in Wait mode. Depending on the user application, Waiting for MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired instructions.
5.5.3 Sleep Mode
The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is application dependent. This mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with LPM = 0 in PMC_FSMR. The processor can be woke up from an interrupt if WFI instruction of the Cortex M3 is used, or from an event if the WFE instruction is used to enter this mode.
6500AS–ATARM–11-Dec-09 SAM3S Summary
5.5.4 Low Power Mode Summary Table
The modes detailed above are the main low power modes. Each part can be set to on or off sep- arately and wake up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low power modes. Notes: 1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12 MHz fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time taken for wake up until the first instruction is fetched. 2. The external loads on PIOs are not taken into account in the calculation. 3. Supply Monitor current consumption is not included. 4. Total Current consumption. 5. 5 µA on VDDCORE, 15 µA for total current consumption (using internal voltage regulator), 8 µA for total current consumption (without using internal voltage regulator). 6. Depends on MCK frequency. 7. In this mode the core is supplied and not clocked but some peripherals can be clocked. Table 5-1. Low Power Mode Configuration Summary Mode SUPC, 32 kHz Oscillator RTC RTT Backup Registers, POR (Backup Region) Regulator Core Memory Peripherals Mode Entry Potential Wake Up Sources Core at Wake Up PIO State while in Low Power Mode PIO State at Wake Up Consumption (2) (3) Wake-up Time(1) Backup Mode ON OFF OFF (Not powered) WFE +SLEEPDEEP bit = 1 WUP0-15 pins SM alarm RTC alarm RTT alarm Reset Previous state saved PIOA & PIOB & PIOC Inputs with pull ups 3 µA typ (4) < 0.1 ms Wait Mode ON ON Powered (Not clocked) WFE +SLEEPDEEP bit = 0 +LPM bit = 1 Any Event from: Fast startup through WUP0-15 pins RTC alarm RTT alarm USB wake-up Clocked back Previous state saved Unchanged 5 µA/15 µA (5) < 10 µs Sleep Mode ON ON Powered(7) (Not clocked) WFE or WFI +SLEEPDEEP bit = 0 +LPM bit = 0 Entry mode =WFI Interrupt Only; Entry mode =WFE Any Enabled Interrupt and/or Any Event from: Fast start-up through WUP0-15 pins RTC alarm RTT alarm USB wake-up Clocked back Previous state saved Unchanged (6) (6)
6500AS–ATARM–11-Dec-09 SAM3S Summary
5.6 Wake-up Sources
The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a s equence which automatically reenables the core power supply and the SRAM power supply, if they are not already enabled. Figure 5-4. Wake-up Source WKUP15 WKUPEN15WKUPT15 WKUPEN1 WKUPEN0 Debouncer SLCK WKUPDBC WKUPS RTCEN rtc_alarm SMEN sm_out Core Supply Restart WKUPIS0 WKUPIS1 WKUPIS15 Falling/Rising Edge Detector WKUPT0 Falling/Rising Edge Detector WKUPT1 Falling/Rising Edge Detector WKUP0 WKUP1 RTTEN rtt_alarm
6500AS–ATARM–11-Dec-09 SAM3S Summary
5.7 Fast Startup
The SAM3S allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT). The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start- up signal to the Power Management Controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded 4 MHz fast RC oscillator, switches the master clock on this 4MHz clock and reenables the processor clock. Figure 5-5. Fast Start-Up Sources RTCEN rtc_alarm RTTEN rtt_alarm USBEN usb_wakeup fast_restart WKUP15 FSTT15 WKUP1 WKUP0 FSTT0 FSTT1 Falling/Rising Edge Detector Falling/Rising Edge Detector Falling/Rising Edge Detector
6500AS–ATARM–11-Dec-09 SAM3S Summary 6. Input/Output Lines The SAM3S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to mu ltiplexing capabilities of the PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs.
6.1 General Purpose I/O Lines
GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such as pull-up or pull-down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming of these modes is performed independently for each I/O line through the PIO controller user interface. For more details, refer to the product PIO control- ler section. The input output buffers of the PIO lines are supplied through VDDIO power supply rail. The SAM3S embeds high speed pads able to handle up to 32 MHz for HSMCI (MCK/2), 45 MHz for SPI clock lines and 35 MHz on other lines. See AC Characteristics Section in the Electrical Characteristics Section of the datasheet for more details. Typical pull-up and pull-down value is 100 kΩ for all I/Os. Each I/O line also embeds an ODT (On-Die Termination), see Figure 6-1. It consists of an inter- nal series resistor termination scheme fo r impedance matching between the driver output (SAM3S) and the PCB trace impedance preventing signal reflection. The series resistor helps to reduce IOs switching current (di/ dt) thereby reducing in turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between devices or between boards. In conclusion ODT helps diminish signal integrity issues. Figure 6-1. On-Die Termination
6.2 System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few. Described below are the SAM3S system I/O lines shared with PIO lines: These pins are software configurable as general purpose I/O or system pins. At startup the default function of these pins is always used. PCB Trace Z0 ~ 50 Ohms Receiver SAM3 Driver with Rodt Zout ~ 10 Ohms Z0 ~ Zout + Rodt ODT 36 Ohms Typ.
6500AS–ATARM–11-Dec-09 SAM3S Summary Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the user application sets PB12 into PIO mode, 2. In the product Datasheet Refer to: Slow Clock Generator of the Supply Controller section. 3. In the product Datasheet Refer to: 3 to 20 MHZ Crystal Osillator information in PMC section.
6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SW DIO, TDO/SWO, TDI and commonly provided on a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 3-1 on page 6. At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer to the Debug and Test Section of the product datasheet. SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 k Ω to GND, so that it can be left uncon- nected for normal operations. By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to the Debug and Test Section. Table 6-1. System I/O Configuration Pin List. SYSTEM_IO bit number Default function after reset Other function Constraints for normal start Configuration
12 ERASE PB12 Low Level at startup (1)
In Matrix User Interface Registers (Refer to the SystemIO Configuration Register in the Bus Matrix section of the product datasheet.)
10 DDM PB10 -
11 DDP PB11 -
7 TCK/SWCLK PB7 -
6 TMS/SWDIO PB6 -
5 TDO/TRACESWO PB5 -
4 TDI PB4 -
- PA7 XIN32 - See footnote (2) below - PA8 XOUT32 - - PB9 XIN - See footnote (3) below - PB8 XOUT -
6500AS–ATARM–11-Dec-09 SAM3S Summary
6.3 Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3S series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet.
6.4 NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse and the reset con- troller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 kΩ . By default, the NRST pin is configured as an input.
6.5 ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 k Ω to GND, so that it can be left unconnected for normal operations. This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high during less than 100 ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform a Flash erase operation. The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a PIO pin. If the ERASE pin is used as a standa rd I/O, startup level of this pin must be low to prevent unwanted erasing. Please refer to Section 11.2 “Peripheral Sig- nal Multiplexing on I/O Lines” on page 44 . Also, if the ERASE pin is used as a standard I/O output, asserting the pin to low does not erase the Flash.
6500AS–ATARM–11-Dec-09 SAM3S Summary 7. Processor and Architecture
7.1 ARM Cortex-M3 Processor
Version 2.0 Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit Harvard processor architecture enabling simultaneous instruction fetch with data load/store Three-stage pipeline Single cycle 32-bit multiply Hardware divide Thumb and Debug states Handler and Thread modes Low latency ISR entry and exit
7.2 APB/AHB bridge
The SAM3S product embeds one peripheral bridge: The peripherals of the bridge are clocked by MCK.
7.3 Matrix Masters
The Bus Matrix of the SAM3S product manages 4 masters, which means that each master can perform an access concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for each master. In order to sim- plify the addressing, all the masters have the same decodings.
7.4 Matrix Slaves
The Bus Matrix of the SAM3S product manages 5 slaves. Each slave has its own arbiter, allow- ing a different arbitration per slave. Table 7-1. List of Bus Matrix Masters Master 0 Cortex-M3 Instruction/Data Master 1 Cortex-M3 System Master 2 Peripheral DMA Controller (PDC) Master 3 CRC Calculation Unit Table 7-2. List of Bus Matrix Slaves Slave 0 Internal SRAM Slave 1 Internal ROM Slave 2 Internal Flash Slave 3 External Bus Interface Slave 4 Peripheral Bridge
6500AS–ATARM–11-Dec-09 SAM3S Summary
7.5 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired and shown as “-” in the following table.
7.6 Peripheral DMA Controller
Handles data transfer between peripherals and memories Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory Next Pointer management for reducing interrupt latency requirement The Peripheral DMA Controller handles transfer requests from the channel according to the fol- lowing priorities (Low to High priorities): Table 7-3. SAM3S Master to Slave Access Masters 0 1 2 3 Slaves Cortex-M3 I/D Bus Cortex-M3 S Bus PDC CRCCU
0 Internal SRAM - X X X
1 Internal ROM X - X X
2 Internal Flash X - - X
3 External Bus Interface - X X X
4 Peripheral Bridge - X X -
Table 7-4. Peripheral DMA Controller Instance Name Channel T/R 100 & 64 Pins 48 Pins PWM Transmit x x TWI1 Transmit x x TWI0 Transmit x x UART1 Transmit x x UART0 Transmit x x USART1 Transmit x N/A USART0 Transmit x x DAC Transmit x N/A SPI Transmit x x SSC Transmit x x HSMCI Transmit x N/A PIOA Transmit x x TWI1 Receive x x TWI0 Receive x x UART1 Receive x N/A
6500AS–ATARM–11-Dec-09 SAM3S Summary
7.7 Debug and Test Features
Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset. Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling Instrumentation Trace Macrocell (ITM) for support of printf style debugging IEEE1149.1 JTAG Boundary-can on All Digital Pins UART0 Receive x x USART1 Receive x x USART0 Receive x x ADC Receive x x SPI Receive x x SSC Receive x x HSMCI Receive x N/A PIOA Receive x x Table 7-4. Peripheral DMA Controller (Continued) Instance Name Channel T/R 100 & 64 Pins 48 Pins
6500AS–ATARM–11-Dec-09 SAM3S Summary 8. Product Mapping Figure 8-1. SAM3S Product Mapping Address memory space Code
1 MByte
+0x40 TC0 TC2 +0x80 TC1 TC3 0x40014000 TC1 TC4 +0x40 TC1 TC5 +0x80 TWI0 0x40018000 TWI1 0x4001C000 PWM 0x40020000 USART0 0x40024000 USART1 0x40028000 Reserved 0x4002C000 Reserved 0x40030000 UDP 0x40034000 ADC 0x40038000 DACC 0x4003C000 ACC 0x40040000 CRCCU 0x40044000 0x40048000 System Controller 0x400E0000 0x400E2600 0x40100000 0x40200000 0x40400000 0x60000000 External RAM SMC Chip Select 0 0x60000000 SMC Chip Select 1 Undefined
32 MBytes
+0x10 RTT +0x30 WDT +0x50 RTC +0x60 GPBR +0x90 0x400E1600 0x4007FFFF Internal Flash Internal ROM Reserved Peripherals External SRAM 0x60000000 0xA0000000 System 0xE0000000 0xFFFFFFFF Reserved Reserved Reserved Reserved Reserved Reserved Reserved
6500AS–ATARM–11-Dec-09 SAM3S Summary 9. Memories
9.1 Embedded Memories
9.1.1 Internal SRAM
The ATSAM3S4 product (256-Kbyte internal Flash version) embeds a total of 48 Kbytes high- speed SRAM. The ATSAM3S2 product (128-Kbyte internal Flash version) embeds a total of 32 Kbytes high- speed SRAM. The ATSAM3S1 product (64-Kbyte internal Flas h version) embeds a total of 16 Kbytes high- speed SRAM. The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000. The SRAM is in the bit band region. The bit band alias region is mapped from 0x2200 0000 to 0x23FF FFFF.
9.1.2 Internal ROM
The SAM3S product embeds an Internal ROM, which contains the SAM Boot Assistant (SAM- BA), In Application Programming routines (IAP) and Fast Flash Programming Interface (FFPI). At any time, the ROM is mapped at address 0x0080 0000.
9.1.3 Embedded Flash
9.1.3.1 Flash Overview
The Flash of the ATSAM3S4 (256-Kbytes internal Flash version) is organized in one bank of 1024 pages (Single plane) of 256 bytes. The Flash of the ATSAM3S2 (128-Kbytes internal Flash version) is organized in one bank of 512 pages (Single plane) of 256 bytes. The Flash of the ATSAM3S1 (64-Kbytes internal Flash version) is organized in one bank of 256 pages (Single plane) of 256 bytes. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface.
9.1.3.2 Flash Power Supply
The Flash is supplied by VDDCORE.
9.1.3.3 Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (EEF C) manages accesses performed by the mas- ters of the system. It enab les reading the Flash and writing t he write buffer. It also contains a User Interface, mapped on the APB. The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32- bit internal bus. Its 128-bit wide memory interface increases performance. The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
6500AS–ATARM–11-Dec-09 SAM3S Summary One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic.
9.1.3.4 Flash Speed
The user needs to set the number of wait states depending on the frequency used. For more details, refer to the AC Characteristics sub section in the product Electrical Character- istics Section.
9.1.3.5 Lock Regions
Several lock bits used to protect write and er ase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. If a locked-region’s erase or program command occurs, the command is aborted and the EEFC triggers an interrupt. The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.1.3.6 Security Bit Feature
The SAM3S features a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, Core Registers and Internal Peripherals either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of the EEFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted. It is important to note that the assertion of the ERASE pin should always be longer than 200 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.
9.1.3.7 Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the cal- ibration bits.
9.1.3.8 Unique Identifier
Each device integrates its own 64-bit unique i dentifier. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the unique identifier. Table 9-1. Number of Lock Bits Product Number of Lock Bits Lock Region Size ATSAM3S4 16 16 kbytes (64 pages) ATSAM3S2 8 16 kbytes (64 pages) ATSAM3S1 4 16 kbytes (64 pages)
6500AS–ATARM–11-Dec-09 SAM3S Summary
9.1.3.9 Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program- ming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST and PA0 and PA1are tied low.
9.1.3.10 SAM-BA
® Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART and USB. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
9.1.3.11 GPNVM Bits
The SAM3S features three GPNVM bits that can be cleared or set respectively through the com- mands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
9.1.4 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed via GPNVM. A general-purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash. The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur- pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface. Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.
9.2 External Memories
The SAM3S features an External Bus Interface to provide the interface to a wide range of exter- nal memories and to any parallel peripheral.
9.2.1 Static Memory Controller
8 - b i t D a t a B u s Up to 24-bit Address Bus (up to 16 MBytes linear per chip select) Up to 4 chip selects, Configurable Assignment Multiple Access Modes supported Table 9-2. General Purpose Non-volatile Memory Bits GPNVMBit[#] Function
0 Security bit
1 Boot mode selection
6500AS–ATARM–11-Dec-09 SAM3S Summary – Chip Select, Write enable or Read enable Control Mode – Asynchronous read in Page Mode supported (4- up to 32-byte page size) Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time Slow Clock mode supported Additional Logic for NAND Flash
6500AS–ATARM–11-Dec-09 SAM3S Summary 10. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc... See the system controller block diagram in Figure 10-1 on page 36
6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 10-1. System Controller Block Diagram Software Controlled Voltage Regulator Matrix SRAM Watchdog Timer Cortex-M3 Flash Peripherals Peripheral Bridge Zero-Power Power-on Reset Supply Monitor (Backup) RTC Power Management Controller Embedded 32 kHz RC Oscillator Xtal 32 kHz Oscillator Supply Controller Brownout Detector (Core) Reset Controller Backup Power Supply Core Power Supply PLLA vr_on vr_mode ON out rtc_alarm SLCK rtc_nreset proc_nreset periph_nreset ice_nreset Master Clock MCK SLCK NRST MAINCK FSTT0 - FSTT15 XIN32 XOUT32 osc32k_xtal_en Slow Clock SLCK osc32k_rc_en VDDIO VDDCORE VDDOUT ADVREF ADx WKUP0 - WKUP15 bod_core_on lcore_brown_out RTT rtt_alarmSLCK rtt_nreset XIN XOUT VDDIO VDDIN PIOx USB Transeivers VDDIO DDP DDM MAINCK DAC Analog Circuitry DACx PLLB PLLBCK PLLACK Embedded 12 / 8 / 4 MHz RC Oscillator Main Clock MAINCK SLCK 3 - 20 MHz XTAL Oscillator FSTT0 - FSTT15 are possible Fast Startup Sources, generated by WKUP0-WKUP15 Pins, but are not physical pins. VDDIO XTALSEL General Purpose Backup Registers vddcore_nreset vddcore_nreset PIOA/B/C Input/Output Buffers ADC Analog Circuitry Analog Comparator
6500AS–ATARM–11-Dec-09 SAM3S Summary
10.1 System Controller and Peripherals Mapping
Please refer to Section 8-1 “SAM3S Product Mapping” on page 30. All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2 Power-on-Reset, Brownout and Supply Monitor
The SAM3S embeds three features to monitor, warn and/or reset the chip: Power-on-Reset on VDDIO Brownout Detector on VDDCORE Supply Monitor on VDDIO
10.2.1 Power-on-Reset
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but also during power down. If VDDIO goes below the threshold voltage, the entire chip is reset. For more information, refer to the Electrical Characteristics section of the datasheet.
10.2.2 Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by soft- ware through the Supply Controller (SUPC_MR). It is especially recommended to disable it during low-power modes such as wait or sleep modes. If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more infor- mation, refer to the Supply Controller (SUPC) and Electrical Characteristics sections of the datasheet.
10.2.3 Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is not ac tive by default. It can be activated by software and is fully programmable with 16 steps for the threshold (between 1.9V to 3.4V). It is controlled by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply mon- itor power consumption by a factor of up to 2048. For more information, refer to the SUPC and Electrical Characteristics sections of the datasheet.
10.3 Reset Controller
The Reset Controller is based on a Power-on-Reset cell, and a Supply Monitor on VDDCORE. The Reset Controller is capable to return to the software the source of the last reset, either a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the NRST pin input/output. It is capable to shape a reset signal for the exter nal devices, simplifying to a minimum connection of a push-button on the NRST pin to implement a manual reset. The configuration of the Reset Controller is saved as supplied on VDDIO.
10.4 Supply Controller (SUPC)
The Supply Controller controls the power suppl ies of each section of the processor and the peripherals (via Voltage regulator control) The Supply Controller has its own reset circuitr y and is clocked by the 32 kHz Slow clock generator.
6500AS–ATARM–11-Dec-09 SAM3S Summary The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power power-on reset allows the Supply Controller to start properly, while the soft- ware-programmable brownout detector allows det ection of either a battery discharge or main voltage loss. The Slow Clock generator is based on a 32 kH z crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock defaul ts to the RC oscillator, but th e software can enable the crystal oscillator and select it as the Slow Clock source. The Supply Controller starts up the device by sequentially enabling the internal power switches and the Voltage Regulator, then it generates the proper reset signals to the core power supply. It also enables to set the system in different low power modes and to wake it up from a wide range of events.
10.5 Clock Generator
The Clock Generator is made up of: One Low Power 32768Hz Slow Clock oscillator with bypass mode One Low-Power RC oscillator One 3-20 MHz Crystal Oscillator, which can be bypassed One Fast RC oscillator factory programmed, 3 output frequencies can be selected: 4, 8 or 12 MHz. By default 4 MHz is selected. One 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller One 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and to the peripherals. The input frequency of PLLA is from 7.5 and 20 MHz.
6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 10-2. Clock Generator Block Diagram
10.6 Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides: the Processor Clock, HCLK the Free running processor clock, FCLK the Cortex SysTick external clock the Master Clock, MCK, in particular to the Matrix and the memory interfaces the USB Clock, UDPCK independent peripheral clocks, typically at the frequency of MCK three programmable clock outputs: PCK0, PCK1 and PCK2 The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized. By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at 4 MHz. The user can trim the 8 and 12 MHz RC Oscillator frequency by software. Power Management Controller XIN XOUT Main Clock MAINCK ControlStatus PLL and Divider A PLLA Clock PLLACK 3-20 MHz Main Oscillator PLL and Divider B On Chip 32 kHz RC OSC Slow Clock SLCKXIN32 XOUT32 Slow Clock Oscillator Clock Generator XTALSEL PLLB Clock PLLBCK On Chip 12/8/4 MHz RC OSC MAINSEL
6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 10-3. SAM3S Power Management Controller Block Diagram The SysTick calibration value is fixed at 8000 which allows the generation of a time base of 1 ms with SystTick clock at 8 MHz (max HCLK/8 = 64 MHz/8).
10.7 Watchdog Timer
16-bit key-protected only-once-Programmable Counter Windowed, prevents the processor to be in a dead-lock on the watchdog access.
10.8 SysTick Timer
24-bit down counter Self-reload capability Flexible System timer
10.9 Real Time Timer
Real Time Timer, allowing backup of time with different accuracies – 32-bit free-running back-up counter – Integrates a 16-bit programmable prescaler running on slow clock MCK periph_clk[..] int SLCK MAINCK PLLACK Prescaler /1,/2,/4,...,/64 HCK Processor Clock Controller Sleep Mode Master Clock Controller Peripherals Clock Controller ON/OFF USB Clock Controller SLCK MAINCK PLLACK Prescaler /1,/2,/4,...,/64 Programmable Clock Controller PLLBCK pck[..] PLLBCK PLLBCK UDPCK ON/OFF ON/OFF FCLK SystTick Divider
6500AS–ATARM–11-Dec-09 SAM3S Summary – Alarm register capable to generate a wake-up of the system through the Shut Down Controller
10.10 Real Time Clock
Low power consumption Full asynchronous design Two hundred year calendar Programmable Periodic Interrupt Alarm and update parallel load Control of alarm and update Time/Calendar Data In
10.11 General Purpose Backup Registers
Eight 32-bit general-purpose backup registers
10.12 Nested Vectored Interrupt Controller
Thirty maskable external interrupts Sixteen priority levels Processor state automatically saved on interrupt entry, and restored on Dynamic reprioritization of interrupts Priority grouping. – selection of preempting interrupt levels and non-preempting interrupt levels. Support for tail-chaining and late arrival of interrupts. – back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead.
10.13 Chip Identification
Chip Identifier (CHIPID) registers permit recognition of the device and its revision. JTAG ID: 0x05B2D03F Table 10-1. SAM3S Chip IDs Register Chip Name Flash Size (KBytes) Pin Count DBGU_CIDR CHIPID_EXID ATSAM3S4A (Rev A) 256 48 0x28800960 0x0 ATSAM3S2A (Rev A) 128 48 0x288A0760 0x0 ATSAM3S1A (Rev A) 64 48 0x28890560 0x0 ATSAM3S4B (Rev A) 256 64 0x28900960 0x0 ATSAM3S2B (Rev A) 128 64 0x289A0760 0x0 ATSAM3S1B (Rev A) 64 64 0x28990560 0x0 ATSAM3S4C (Rev A) 256 100 0x28A00960 0x0 ATSAM3S2C (Rev A) 128 100 0x28AA0760 0x0 ATSAM3S1C (Rev A) 64 100 0x28A90560 0x0
6500AS–ATARM–11-Dec-09 SAM3S Summary
10.14 UART
T w o - p i n U A R T – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter
10.15 PIO Controllers
3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79 I/O Lines Fully programmable through Set/Clear Registers Multiplexing of four peripheral functions per I/O Line For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) – Input change, rising edge, falling edge, low level and level interrupt – Debouncing and Glitch filter – Multi-drive option enables driving in open drain – Programmable pull-up or pull-down on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time Synchronous output, provides Set and Clear of several I/O lines in a single write Table 10-2. PIO available according to pin count Version 48 pin 64 pin 100 pin PIOA 21 32 32 PIOB 13 15 15 PIOC -- 3 2
6500AS–ATARM–11-Dec-09 SAM3S Summary 11. Peripherals
11.1 Peripheral Identifiers
Table 11-1 defines the Peripheral Identifiers of the SAM3S. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 11-1. Peripheral Identifiers Instance ID Instance Name NV IC Interrupt PMC Clock Co ntrol Instance Description 0S U P C X Supply Controller 1R S T C X Reset Controller 2R T C X Real Time Clock 3R T T X Real Time Timer 4W D T X Watchdog Timer 5P M C X Power Management Controller
6 EEFC X Enhanced Embedded Flash Controller
10 SMC X X SMC
11 PIOA X X Parallel I/O Controller A
12 PIOB X X Parallel I/O Controller B
13 PIOC X X Parallel I/O Controller C
14 USART0 X X USART 0
15 USART1 X X USART 1
18 HSMCI X X High Speed Multimedia Card Interface
19 TWI0 X X Two Wire Interface 0
20 TWI1 X X Two Wire Interface 1
21 SPI X X Serial Peripheral Interface
22 SSC X X Synchronous Serial Controller
23 TC0 X X Timer/Counter 0
24 TC1 X X Timer/Counter 1
25 TC2 X X Timer/Counter 2
26 TC3 X X Timer/Counter 3
27 TC4 X X Timer/Counter 4
28 TC5 X X Timer/Counter 5
29 ADC X X Analog-to-Digital Converter
30 DACC X X Digital-to-Analog Converter
31 PWM X X Pulse Width Modulation
32 CRCCU X X CRC Calculation Unit
33 ACC X X Analog Comparator
34 UDP X X USB Device Port
6500AS–ATARM–11-Dec-09 SAM3S Summary
11.2 Peripheral Signal Mult iplexing on I/O Lines
The SAM3S product features 2 PIO controllers on 48-pin and 64-pin versions (PIOA, PIOB) or 3 PIO controllers on the 100-pin version, (PIOA, PI OB, PIOC), that multiplex the I/O lines of the peripheral set. The SAM3S 64-pin and 100-pin PIO Controllers control up to 32 lines. (See, Table 10-2.) Each line can be assigned to one of three peripheral functions: A, B or C. The multiplexing tables in the following pages define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO Controllers. The column “Comments” has been inserted in this table for the user’s own com- ments; it may be used to track how pins are defined in an application. Note that some peripheral functions which are output only, might be duplicated within the tables.
6500AS–ATARM–11-Dec-09 SAM3S Summary
11.2.1 PIO Controller A Multiplexing
Table 11-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B Periphera l C Extra Function System Function Comments PA0 PWMH0 TIOA0 A17 WKUP0 High drive PA1 PWMH1 TIOB0 A18 WKUP1 High drive PA2 PWMH2 SCK0 DATRG WKUP2 High drive PA3 TWD0 NPCS3 High drive PA4 TWCK0 TCLK0 WKUP3 PA5 RXD0 NPCS3 WKUP4 PA6 TXD0 PCK0 PA7 RTS0 PWMH3 XIN32 PA8 CTS0 ADTRG WKUP5 XOUT32 PA9 URXD0 NPCS1 PWMFI0 WKUP6 PA10 UTXD0 NPCS2 PA11 NPCS0 PWMH0 WKUP7 PA12 MISO PWMH1 PA13 MOSI PWMH2 PA14 SPCK PWMH3 WKUP8 PA15 TF TIOA1 PWML3 WKUP14/PIODCEN1 PA16 TK TIOB1 PWML2 WKUP15/PIODCEN2 PA17 TD PCK1 PWMH3 AD0 PA18 RD PCK2 A14 AD1 PA19 RK PWML0 A15 AD2/WKUP9 PA20 RF PWML1 A16 AD3/WKUP10 PA21 RXD1 PCK1 AD8 64/100-pin versions PA22 TXD1 NPCS3 NCS2 AD9 64/100-pin versions PA23 SCK1 PWMH0 A19 PIODCCLK 64/100-pin versions PA24 RTS1 PWMH1 A20 PIODC0 64/100-pin versions PA25 CTS1 PWMH2 A23 PIODC1 64/100-pin versions PA26 DCD1 TIOA2 MCDA2 PIODC2 64/100-pin versions PA27 DTR1 TIOB2 MCDA3 PIODC3 64/100-pin versions PA28 DSR1 TCLK1 MCCDA PIODC4 64/100-pin versions PA29 RI1 TCLK2 MCCK PIODC5 64/100-pin versions PA30 PWML2 NPCS2 MCDA0 WKUP11/P IODC6 64/100-pin versions PA31 NPCS1 PCK2 MCDA1 PIODC7 64/100-pin versions
6500AS–ATARM–11-Dec-09 SAM3S Summary
11.2.2 PIO Controller B Multiplexing
Table 11-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A Peripheral B Periphera l C Extra Function System Function Comments PB0 PWMH0 AD4 PB1 PWMH1 AD5 PB2 URXD1 NPCS2 AD6/ WKUP12 PB3 UTXD1 PCK2 AD7 PB4 TWD1 PWMH2 TDI PB5 TWCK1 PWML0 WKUP13 TDO/TRACESWO PB6 TMS/SWDIO PB7 TCK/SWCLK PB8 XOUT PB9 XIN PB10 DDM PB11 DDP PB12 PWML1 ERASE PB13 PWML2 PCK0 DAC0 64/100-pin versions PB14 NPCS1 PWMH3 DAC1 64/100-pin versions
6500AS–ATARM–11-Dec-09 SAM3S Summary
11.2.3 PIO Controller C Multiplexing
Table 11-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments PC0 D0 PWML0 100-pin version PC1 D1 PWML1 100-pin version PC2 D2 PWML2 100-pin version PC3 D3 PWML3 100-pin version PC4 D4 NPCS1 100-pin version PC5 D5 100-pin version PC6 D6 100-pin version PC7 D7 100-pin version PC8 NWE 100-pin version PC9 NANDOE 100-pin version PC10 NANDWE 100-pin version PC11 NRD 100-pin version PC12 NCS3 AD12 100-pin version PC13 NWAIT PWML0 AD10 100-pin version PC14 NCS0 100-pin version PC15 NCS1 PWML1 AD11 100-pin version PC16 A21/NANDALE 100-pin version PC17 A22/NANDCLE 100-pin version PC18 A0 PWMH0 100-pin version PC19 A1 PWMH1 100-pin version PC20 A2 PWMH2 100-pin version PC21 A3 PWMH3 100-pin version PC22 A4 PWML3 100-pin version PC23 A5 TIOA3 100-pin version PC24 A6 TIOB3 100-pin version PC25 A7 TCLK3 100-pin version PC26 A8 TIOA4 100-pin version PC27 A9 TIOB4 100-pin version PC28 A10 TCLK4 100-pin version PC29 A11 TIOA5 AD13 100-pin version PC30 A12 TIOB5 AD14 100-pin version PC31 A13 TCLK5 100-pin version
6500AS–ATARM–11-Dec-09 SAM3S Summary 12. Embedded Peripherals Overview
12.1 Serial Peripheral Interface (SPI)
Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection Very fast transfers supported – Transfers with baud rates up to MCK – The chip select line may be left active to speed up transfers on the same device
12.2 Two Wire Interface (TWI)
Master, Multi-Master and Slave Mode Operation Compatibility with Atmel two-wire interface, serial memory and I 2C compatible devices One, two or three bytes for slave address Sequential read/write operations Bit Rate: Up to 400 kbit/s General Call Supported in Slave Mode Connecting to PDC channel capabilities optimizes data transfers in Master Mode only – One channel for the receiver, one channel for the transmitter – Next buffer support
12.3 Universal Asynchronous R eceiver Transceiver (UART)
T w o - p i n U A R T – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter
6500AS–ATARM–11-Dec-09 SAM3S Summary
12.4 Universal Synchronous Asynchrono us Receiver Transceiver (USART)
Programmable Baud Rate Generator with Fractional Baud rate support 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding – Full modem line support on USART1 (DCD-DSR-DTR-RI) RS485 with driver control signal ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit SPI Mode –M a s t e r o r S l a v e – Serial Clock programmable Phase and Polarity – SPI Serial Clock (SCK) Frequency up to MCK/4 IrDA modulation and demodulation – Communication at up to 115.2 Kbps Test Modes – Remote Loopback, Local Loopback, Automatic Echo
12.5 Synchronous Serial Controller (SSC)
Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader) Contains an independent receiver and transmitter and a common clock divider Offers configurable frame sync and data length Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
12.6 Timer Counter (TC)
Six 16-bit Timer Counter Channels Wide range of functions including: – Frequency Measurement – Event Counting
6500AS–ATARM–11-Dec-09 SAM3S Summary – Interval Measurement – Pulse Generation –D e l a y T i m i n g – Pulse Width Modulation – Up/down Capabilities Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals Two global registers that act on all three TC Channels Quadrature decoder – Advanced line filtering – Position / revolution / speed 2-bit Gray Up/Down Counter for Stepper Motor
12.7 Pulse Width Modulatio n Controller (PWM)
One Four-channel 16-bit PWM Controller, 16-bit counter per channel Common clock generator, providing Thirteen Different Clocks – A Modulo n counter providing eleven clocks – Two independent Linear Dividers working on modulo n counter outputs – High Frequency Asynchronous clocking mode Independent channel programming – Independent Enable Disable Commands – Independent Clock Selection – Independent Period and Duty Cycle, with Double Buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform – Independent Output Override for each channel – Independent complementary Outputs with 12-bit dead time generator for each channel – Independent Enable Disable Commands – Independent Clock Selection – Independent Period and Duty Cycle, with Double Buffering Synchronous Channel mode – Synchronous Channels share the same counter – Mode to update the synchronous channels registers after a programmable number of periods Connection to one PDC channel – Offers Buffer transfer without Processor Intervention, to update duty cycle of synchronous channels independent event lines which can send up to 4 triggers on ADC within a period
6500AS–ATARM–11-Dec-09 SAM3S Summary Programmable Fault Input providing an asynchronous protection of outputs Stepper motor control (2 Channels)
12.8 High Speed Multimedia Card Interface (HSMCI)
4-bit or 1-bit Interface Compatibility with MultiMedia Ca rd Specification Version 4.3 Compatibility with SD and SDHC Memo ry Card Specification Version 2.0 Compatibility with SDIO Specification Version V1.1. Compatibility with CE-ATA Specification 1.1 Cards clock rate up to Master Clock divided by 2 Boot Operation Mode support High Speed mode support Embedded power management to slow down clock rate when not used HSMCI has one slot supporting – One MultiMediaCard bus (up to 30 cards) or – One SD Memory Card – One SDIO Card Support for stream, block and multi-block data read and write
12.9 USB Device Port (UDP)
USB V2.0 full-speed compliant,12 Mbits per second. Embedded USB V2.0 full-speed transceiver Embedded 2688-byte dual-port RAM for endpoints Eight endpoints – Endpoint 0: 64 bytes – Endpoint 1 and 2: 64 bytes ping-pong – Endpoint 3: 64 bytes – Endpoint 4 and 5: 512 bytes ping-pong – Endpoint 6 and 7: 64 bytes ping-pong – Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints Suspend/resume logic Integrated Pull-up on DDP Pull-down resistor on DDM and DDP when disabled
12.10 Analog-to-Digital Converter (ADC)
up to 16 Channels, 10/12-bit resolution up to 1 MSample/s programmable sequence of conversion on each channel Integrated temperature sensor Single ended/differential conversion
6500AS–ATARM–11-Dec-09 SAM3S Summary Programmable gain: 1, 2, 4
12.11 Digital-to-Analog Converter (DAC)
Up to 2 channel 12-bit DAC Up to 2 mega-samples conversion rate in single channel mode Flexible conversion range Multiple trigger sources for each channel 2 Sample/Hold (S/H) outputs Built-in offset and gain calibration Possibility to drive output to ground Possibility to use as input to analog comparator or ADC (as an internal wire and without S/H stage) Two PDC channels Power reduction mode
12.12 Static Memory Controller
16-Mbyte Address Space per Chip Select 8- bit Data Bus Word, Halfword, Byte Transfers Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select Programmable Data Float Time per Chip Select External Wait Request Automatic Switch to Slow Clock Mode Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes NAND FLASH additional logic supporting NAND Flash with Multiplexed Data/Address buses Hardware Configurable number of chip select from 1 to 4 Programmable timing on a per chip select basis
12.13 Analog Comparator
One analog comparator High speed option vs. low power option Selectable input hysteresis: – 0, 20 mV, 50 mV Minus input selection: – DAC outputs – Temperature Sensor –A D V R E F – AD0 to AD3 ADC channels Plus input selection: – All analog inputs
6500AS–ATARM–11-Dec-09 SAM3S Summary output selection: – Internal signal – external pin – selectable inverter window function Interrupt on: – Rising edge, Falling edge, toggle – Signal above/below window, signal inside/outside window
12.14 Cyclic Redundancy Check Calculation Unit (CRCCU)
32-bit cyclic redundancy check automatic calculation CRC calculation between two addresses of the memory
6500AS–ATARM–11-Dec-09 SAM3S Summary 13. Package Drawings The SAM3S series devices are available in LQFP, QFN and LFBGA packages. Figure 13-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 13-2. 100-ball LFBGA Package Drawing
6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 13-3. 64- and 48-lead LQFP Package Drawing
6500AS–ATARM–11-Dec-09 SAM3S Summary Table 13-1. 48-lead LQFP Package Dimensions (in mm) Symbol Millimeter Inch Min Nom Max Min Nom Max A – –1 . 6 0– – 0 . 0 6 3 A1 0.05 – 0.15 0.002 – 0.006 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC E 9.00 BSC 0.354 BSC E1 7.00 BSC 0.276 BSC R2 0.08 – 0.20 0.003 – 0.008 θ 1 0 ° –– 0 ° –– θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.09 – 0.20 0.004 – 0.008 L1 1.00 REF 0.039 REF e 0.50 BSC. 0.020 BSC. D2 5.50 0.217 E2 5.50 0.217 Tolerances of Form and Position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003
6500AS–ATARM–11-Dec-09 SAM3S Summary Table 13-2. 64-lead LQFP Package Dimensions (in mm) Symbol Millimeter Inch Min Nom Max Min Nom Max A – –1 . 6 0– – 0 . 0 6 3 A1 0.05 – 0.15 0.002 – 0.006 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.383 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.383 BSC R2 0.08 – 0.20 0.003 – 0.008 θ 1 0 ° –– 0 ° –– θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.09 – 0.20 0.004 – 0.008 L1 1.00 REF 0.039 REF e 0.50 BSC. 0.020 BSC. D2 7.50 0.285 E2 7.50 0.285 Tolerances of Form and Position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003
6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 13-4. 48-pad QFN Package
6500AS–ATARM–11-Dec-09 SAM3S Summary Table 13-3. 48-pad QFN Package Dimensions (in mm) Symbol Millimeter Inch Min Nom Max Min Nom Max A2 – 0.65 0.70 – 0.026 0.028 A3 0.20 REF 0.008 REF D 7.00 bsc 0.276 bsc E 7.00 bsc 0.276 bsc e 0.50 bsc 0.020 bsc Tolerances of Form and Position aaa 0.10 0.004 bbb 0.10 0.004 ccc 0.05 0.002
6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 13-5. 64-pad QFN Package Drawing
6500AS–ATARM–11-Dec-09 SAM3S Summary 14. Ordering Information Table 14-1. Ordering Code MRL Flash (Kbytes) Package (Kbytes) Package Type Temperature Operating Range ATSAM3S4CA-AU A 256 QFP100 Green Industrial -40°C to 85°C ATSAM3S4CA-CU A 256 BGA100 Green Industrial -40°C to 85°C ATSAM3S4BA-AU A 256 QFP64 Green Industrial -40°C to 85°C ATSAM3S4BA-MU A 256 QFN64 Green Industrial -40°C to 85°C ATSAM3S4AA-AU A 256 QFP48 Green Industrial -40°C to 85°C ATSAM3S4AA-MU A 256 QFN48 Green Industrial -40°C to 85°C ATSAM3S2CA-AU A 128 QFP100 Green Industrial -40°C to 85°C ATSAM3S2CA-CU A 128 BGA100 Green Industrial -40°C to 85°C ATSAM3S2BA-AU A 128 QFP64 Green Industrial -40°C to 85°C ATSAM3S2BA-MU A 128 QFN64 Green Industrial -40°C to 85°C ATSAM3S2AA-AU A 128 QFP48 Green Industrial -40°C to 85°C ATSAM3S2AA-MU A 128 QFN48 Green Industrial -40°C to 85°C ATSAM3S1CA-AU A 64 QFP100 Green Industrial -40°C to 85°C ATSAM3S1CA-CU A 64 BGA100 Green Industrial -40°C to 85°C ATSAM3S1BA-AU A 64 QFP64 Green Industrial -40°C to 85°C ATSAM3S1BA-MU A 64 QFN64 Green Industrial -40°C to 85°C ATSAM3S1AA-AU A 64 QFP48 Green Industrial -40°C to 85°C ATSAM3S1AA-MU A 64 QFN48 Green Industrial -40°C to 85°C
6500AS–ATARM–11-Dec-09 SAM3S Summary
Revision History
Doc. Rev Comments Change Request Ref. 6500AS First issue
6500AS–ATARM–11-Dec-09 SAM3S Summary
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