ATSAM2133B ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Single-chip Synthesizer + Effects, Features include – High-quality Wavetable Synthesis, Serial MIDI In & Out, MPU-401 (UART) – Effects: Reverb + Chorus, on MIDI and/or Audio In – Up to 64-voice Polyphony – Surround on Two or Four Speakers with Intensity/Delay Control – Four-band Parametric Equalizer – Audio-in Processing through Reverb, Chorus, Equalizer, Surround Low Chip Count in Applications – ATSAM2133B Synthesizer, ROM/Flash, DAC – Built-in (32K x 16) Effects RAM Low-power – 40 mA Typical Operating Current, <1 µA Power-down – 2.5V and 3.3V Supply – Built-in Power Switch 16-bit Samples, 44.1 KHz Sampling Rate, 24 dB Digital Filter per Voice Available Wavetable Firmwares and Sample Sets – CleanWave8 ® Low-cost General MIDI 1-MB Firmware + Sample Set – CleanWave32 ® Top-quality 4-MB Firmware + Sample Set – Other Sample Sets Available under special conditions Built-in ROM Debugger, Flash Programmer through Dedicated Pins – Fast Product-to-market Small Footprint – 12 x 12 mm, 0.4 mm Pitch, 100-lead TQFP Package – 10 x 10 mm, 0.8 mm Pitch 100-ball CBGA Package Typical Applications – Portable Telephones – Computer Karaoke, Portable Karaoke Systems – Keyboards, Portable Keyboard Instruments
Description
The A TSAM2133B is a low-cost derivative of the A TSAM97xx series. It retains the same high-quality synthesis with up to 64-voice polyphony. The A TSAM2133B maxi- mum wavetable memory is 16 MB and the parallel communication is via a standard MPU-401. The integrated 32K x 16 RAM allows for high-quality effects without addi- tional components. The highly integrated architecture of the A TSAM2133B combines a specialized high- performance RISC-based digital signal processor (Synthesis/DSP) and a general-pur- pose 16-bit CISC-based control processor on a single chip. An on-chip memory management unit (MMU) allows the synthesis/DSP and the control processor to share external ROM and/or RAM memory devices. An intelligent peripheral I/O interface function handles other I/O interfaces, such as the MPU port, the on-chip MIDI UART , and the Codec control interface, with minimum intervention from the control processor. Sound Synthesis ATSAM2133B Low-power Synthesizer with Effects and Built-in RAM Rev. 2694A–DRMSD–05/03
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Figure 2. Low-cost Karaoke, Hand-held Karaoke Figure 3. Low-cost Keyboard Instrument
2694A–DRMSD–05/03 General Description Block Diagram Synthesis/DSP Engine The synthesis/DSP engine operates on a frame timing basis with the frame subdivided into 64 process slots. Each process is, in turn, divided into 16 micro-instructions known as algorithms. Up to 32 synthesis/DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the device to be programmed for a number of audio signal genera- tion/processing applications. The synthesis/DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24 dB resonant filtering for each voice. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms. A typical application will use half the capacity of the synthesis/DSP engine for synthesis, thus providing state-of-the-art 32-voice wavetable polyphony. The remaining processing power will be used for typical functions such as reverberation, chorus, audio-in process- ing, surround effect, equalizer, etc. Frequently-accessed synthesis/DSP parameter data are stored in five banks of on-chip RAM memory. Sample data or delay lines, which are accessed relatively infrequently, are stored in external ROM or internal 32K x 16 RAM memory. The combination of local- ized micro-program memory and localized parameter data allows micro-instructions to execute in 20 ns (50 MIPS). Separate buses from each of the on-chip parameter RAM memory banks allow highly parallel data movement to increase the effectiveness of each micro-instruction. With this architecture, a single micro-instruction can accomplish up to six simultaneous operations (add, multiply, load, store, etc.), providing a potential throughput of 300 million operations per second (MOPS). ATSAM2133B P16 Processor 16-bit CISC Processor Core includes 256 x 16 Data RAM Synthesis/DSP 64-slot RISC DSP Core includes 512 x 32 Alg RAM 128 x 28 MA1 RAM 256 x 28 MA2 RAM 256 x 28 MB RAM 256 x 16 MX RAM 256 x 12 MY RAM 64 x 13 ML RAM 32K x 16 RAM MMU Memory Management Unit ROM Debug/Flash Prog I/O Functions includes Control/Status MIDI UART Timers Codec Data I/F Host I/F FIFO MIDI MPU Debug/Flash Prog ROM or Flash Codec + DAC
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2694A–DRMSD–05/03 P16 Control Processor and I/O Functions The P16 control processor is a general-purpose 16-bit CISC processor core that runs from external memory. It includes 256 words of local RAM data memory. The P16 control processor writes to the parameter RAM blocks within the synthe- sis/DSP core in order to control the synthesis process. In a typical application, the P16 control processor parses and interprets incoming commands from the MIDI UART or from the MPU-401 interface and then controls the Synthesis/DSP by writing into the parameter RAM banks in the DSP core. Slowly-changing synthesis functions, such as LFOs, are implemented in the P16 control processor by periodically updating the DSP parameter RAM variables. The P16 control processor interfaces with other peripheral devices, such as the system control and status registers, the on-chip MIDI UART, the on-chip timers and the MPU- 401 interface through specialized intelligent peripheral I/O logic. This I/O logic auto- mates many of the system I/O transfers to minimize the amount of overhead processing required from the P16. The MPU-401 interface is implemented using one address line (A0), a chip select signal, read and write strobes from the host and an 8-bit data bus (D0 - D7). Karaoke and keyboard applications can take advantage of the 8-bit MPU-401 interface to communicate with the ATSAM2133B at high speed, with the MIDI IN and MIDI OUT signals remaining available. Memory Management Unit (MMU) The Memory Management Unit (MMU) block allows external ROM/Flash and/or internal 32K x 16 RAM memory resources to be shared between the synthesis/DSP and the P16 control processor. This allows a single device (i.e., internal RAM) to serve as delay lines for the synthesis/DSP and as data memory for the P16 control processor.
Table 1. Pin by Function - 100-lead TQFP Package PWR Power ground - all GND pins should be returned to digital ground. connected to PWROUT , the output of the built-in power switch. should not be lower than VC2 . must be connected to nominal 2.5V . PWROUT 78 PWR Power switch output. Use this pin to supply 2.5V core power by connecting it to all V C2 pins. CS 2 IN Chip select from host, active low. WR 4 IN Write from host, active low. RD 3 IN Read from host, active low. IRQ 1 TSOUT T ri-state output pin, active high. RESET 22 IN Master reset input, active low. used to drive external ICs; use CKOUT instead. CLBD 94 OUT Audio data bit clock, provides timing to DABD0 - 1, DAAD. DAAD 98 IN Stereo serial audio data input. P0 - P3 18 - 21 I/O General-purpose programmable I/O pins. just after RESET, then the internal ROM debugger/flash programmer is started. DBDA T A 91 I/O Debug data. Allows serial communication for debug/flash programming. DBACK 89 OUT Debug acknowledge. T oggled each time a bit is received/sent on DBDA T A.
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OUT External memory address (ROM/Flash). Up to 16 MB. WCS 53 OUT External ROM/FLASH chip select, active low. WWE 55 OUT External FLASH write enable, active low. WOE 54 OUT External ROM/FLASH output enable, active low. LFT 85 ANA PLL low-pass filter, should be connected to an external RC network. TEST 23 IN T est pin, should be returned to GND. RESET applied. When unused, this pin must be connected to VC2 . Table 1. Pin by Function - 100-lead TQFP Package (Continued)
Table 2. Pinout by Pin Number - 100-lead TQFP Package
1 IRQ 26 WA2 51 WA21 76 GND
5 A0 30 VC3 55 WWE 80 GND
7 D1 32 WA6 57 VC3 82 X2
10 GND 35 WA9 60 WD2 85 LFT
11 VC2 36 GND 61 WD3 86 VC2
12 D4 37 VC2 62 WD4 87 VC2
13 D5 38 WA10 63 WD5 88 CKOUT
14 D6 39 WA11 64 WD6 89 DBACK
15 D7 40 WA12 65 WD7 90 DBCLK
17 VC3 42 WA14 67 WD9 92 DABD1
18 P0 43 WA15 68 GND 93 DABD0
19 P1 44 VC3 69 VC3 94 CLBD
20 P2 45 GND 70 WD10 95 WSBD
21 P3 46 WA16 71 WD11 96 GND
22 RESET
47 WA17 72 WD12 97 VC3
23 TEST 48 WA18 73 WD13 98 DAAD
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Table 3. Pin by Function - 100-ball LFBGA Package connected to PWROUT , the output of the built-in power switch. CS C1 IN Chip select from host, active low. WR C2 IN Write from host, active low. RD D2 IN Read from host, active low. IRQ B1 TSOUT T ri-state output pin, active high. H3 IN Master reset input, active low. cannot be used to drive external ICs; use CKOUT instead. CLBD C4 OUT Audio data bit clock, provides timing to DABD0 - 1, DAAD. DAAD A2 IN Stereo serial audio data input. P0 - P3 G1, G3, H2, H1 I/O General-purpose programmable I/O pins.
OUT External memory address (ROM/FLASH). Up to 16 Mega bytes. G9 OUT External ROM/FLASH chip select, active low. WWE G8 OUT External FLASH write enable, active low. WOE H9 OUT External ROM/FLASH output enable, active low. LFT A6 ANA PLL low pass filter. Should be connected to an external RC network. TEST J1 IN T est pin. Should be returned to GND. to VC2 , then RESET applied. When unused this pin must be connected to VC2 . Table 3. Pin by Function - 100-ball LFBGA Package (Continued)
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Table 4. Pinout by Pin Number - 100-ball LFBGA Package
Table 5. Absolute Maximum Ratings sections of this specification is not implied. Table 6. Recommended Operating Conditions Table 7. DC Characteristics (tA = 25°C, VC2 = 2.5V ± 10%, VC3 = 3.3V ± 10%)
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All timings refer to tCK , the internal master clock period. quency at X1 is 12.288 MHz (48 kHz sampling rate). ns access time while providing state-of-the-art 44.1 kHz sampling rate. Table 8. Crystal Frequency Selection Parameters
Figure 5. Host Interface Write Cycle Table 9. PC Host Interface Timing Parameters
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Table 10. External ROM/Flash Timing Parameters
Figure 7. External Flash Write Cycle Table 11. External Flash Timing Parameters
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Figure 9. Digital Audio Frame Format Notes: 1. Selection between I2S and Japanese format is a firmware option. Table 12. Digital Audio Timing Parameters
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2694A–DRMSD–05/03 Recommended Board Layout Like all HCMOS high integration ICs, the following simple rules of board layout are man- datory for reliable operation: GND, VC3, VC2 Distribution and Decouplings All GND, VC3, VC2 pins should be connected. A GND plane is strongly recommended below the ATSAM2133B. The board GND + VC3 distribution should be in grid form. Recommended VC2 decoupling is 0.1 µF at each corner of the IC with an additional 10 µF decoupling close to the crystal. VC3 requires a single 0.1uF decoupling. Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C- R and the ATSAM2133B should be short and shielded. The ground return from the com- pensation capacitors and LFT filter should be the GND plane from ATSAM2133B. Buses Parallel layout between D0 - D7 and WA0 - WA21/WD0 - WD15 should be avoided. The D0 - D7 bus is an asynchronous type bus. Even on short distances, it can induce pulses on WA0 - WA21/WD0 - WD15 that can corrupt address and/or data on these buses. A ground plane should be implemented below the D0 - D7 bus, which is connected to the host and to the ATSAM2133B GND. A ground plane should be implemented below the WA0 - WA21/WD0 - WD15 bus, which is connected to the ROM/Flash grounds and to the ATSAM2133B. Analog Section A specific AGND ground plane should be provided, which is connected to the GND ground by a single trace. No digital signals should cross the AGND plane. Refer to the Codec vendor recommended layout for correct implementation of the ana- log section.
Figure 12. Recommended Crystal Compensation and LFT Filter
470 Ohm
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Table 13. 100-lead TQFP Package Dimensions (in mm)
Figure 14. Low Profile Fine Pitch 100-ball Grid Array (LFBGA)(Bottom View) Note: A1 Ball in lower left-hand corner.
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