ATR2730-TLPY

ATR2730 ATMEL | Alldatasheet

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• Supply Voltage: 8.5V  RF Frequency Range: 1400 MHz to 1550 MHz  IF Frequency Range: 150 MHz to 250 MHz  Enhanced IM3 Rejection  Overall Gain Control Range: 30 dB Typically  DSB Noise Figure: 10 dB  Gain-controlled Amplifier and L-band Mixer  Power-down Function for the Analog Part  On-chip Gain-control Circuitry  On-chip VCO, Typical Frequency 1261.568 MHz  Internal VCO Can Be Overdriven by an External LO  On-chip Frequency Synthesizer – Fixed LO Divider Factor: 2464 – Nine Selectable Reference Divider Factors: 32, 33, 35, 36, 48, 49, 63, 64, 65 – A Reference Oscillator (C an Be Overdriven by an External Reference Signal) – Tri-state Phase Detector with Programmable Charge Pump – Programmable Deactivation of Tuning Output – Lock-status Indication – Test Interface 1. Description The ATR2730 is a monolithically integrated L-band down-converter circuit fabricated with Atmel®’s advanced UHF5S technology. This IC covers all functions of an L-band down-converter in a DAB receiver. The device includes a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain control block, a power-save function for the analog part, an L-band o scillator, and a complete freq uency synthesizer unit. The frequency synthesizer block consists of a reference oscillator/buffer, a reference divider, an RF divider, a tri-state phase detector, a loop filter amplifier, a lock detector, a programmable charge pump, a test interface, and a control interface. L-band Down-converter for DAB Receivers ATR2730 Preliminary 4903C–DAB–03/07

4903C–DAB–03/07 ATR2730 [Preliminary] Figure 1-1. Block Diagram Charge pump Tristate phase detectorReference counter : Nref Control interface Test interface VCO RF counter : 2464 Lock detector Band- gap Analog part Power save (analog part) Internal 5V supply voltage for frequency synthesizer Voltage stabilizer Lock detector 20 kΩ 15 16 111 17 6, 7, 8, 21, 22, 23, 24 19 3 AGC RF VREF SI1 SI2 PLCK PD CD CITIOSCE TH OSCBPSM TANK NRF 20 928 IF VCC1 VCC3 VCC2 GND VCC4

4903C–DAB–03/07 ATR2730 [Preliminary] 2. Pin Configuration Figure 2-1. Pinning SSO28 PLCK TI CD PD CI VCC2 GND TANK GND GND VREF PSM SI2 VCC1 OSCB AGC TH OSCE IF VCC3 GND GND GND GND NRF VCC4 SI1 RF

4903C–DAB–03/07 ATR2730 [Preliminary] Table 2-1. Pin Description Pin Symbol Function

1 PSM Power save mode

2 SI2 Control input

3 VCC1 Supply voltage VCO

4 VREF Reference pin of VCO

5 TANK Tank pin of VCO

6, 7, 8, 21, 22, 23, 24 GND Ground

9 VCC2 Supply voltage PLL

10 CI Control input

11 TI Test interface

12 CD Active filter output

13 PD Tri-state charge pump output

14 PLCK Lock-indication output (open collector)

15 OSCB Input of internal oscillator/buffer

16 OSCE Output of internal oscillator/buffer

17 TH Threshold voltage of comparator

18 AGC Charge-pump output of comparator, AGC input for amplifier and mixer

19 IF Intermediate frequency output

20 VCC3 Supply voltage

25 NRF RF input (inverted)

26 RF RF input

27 SI1 Control input

28 VCC4 Supply voltage

4903C–DAB–03/07 ATR2730 [Preliminary] 3. Functional Description The ATR2730 is an L-band down-converter circuit covering a gain-controlled amplifier, a gain-controlled mixer, an output buffer, a gain c ontrol circuitry, an L- band oscillator, and a fre- quency synthesizer block. Designed for applications in a DAB receiver, the circuit down-converts incoming L-band signals in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in the range of 190 MHz to 230 MHz, which can be handled by a subsequent DAB tuner. A block diagram of this circuit is shown in Figure 1-1 on page 2.

3.1 Gain-controlled Amplifier

RF signals applied to the RF input pin are amplified by a gain-controlled amplifier. The comple- mentary pin NRF is not internally blocked; it is recommended to block this pin carefully by an external capacitor. The gain-control voltage is gener ated by internal gain-control circuitry. The output signal of this amplifier is fed to a gain-controlled mixer.

3.2 Gain-controlled Mixe r and Output Buffer

The purpose of this mixer is to down-convert the L-band signal in the frequency range of 1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz. Like the amplifier, the gain of the mixer is controlled by the gain-control circuitry. The IF signal is buffered and filtered by a one-pole low-pass filter at a 3 dB frequency of about 500 MHz, and then it is fed to the single-ended output pin IF.

3.3 Gain-control Circuitry

The gain-control circuitry measures the signal power, compares it with a certain power level and generates control voltages for the gain-controlled amplifier and mixer. An equivalent circuit of this functional block is shown in Figure 10-1 on page 14. In order to meet this functionality, the output signal of the buffer amplifier is weakly band-pass fil- tered (transition range of about 60 MHz to 550 MHz), rectified, low-pass filtered, and fed to a comparator whose threshold can be defined by an ex ternal resistor, RTH, at pin TH. By varying the value of this resistor, a power threshold of about –33 dBm to –20 dBm can be selected. In order to achieve a good intermodulation ratio, it is recommended to keep the power threshold below –25 dBm. An appropriate application is shown in Figure 8-1 on page 12 . Depending on the selection made by the comparator, a charge pump charges or discharges a capacitor which is applied to the AGC pin. By varying this capacitor, different time constants of the AGC loop can be realized. The voltage arising at the AGC pin is used to control the gain setting of the gain-controlled amplifier and mixer. The voltage at pin AGC is in the range of 5.75V for maxi- mum gain and 0.3V for minimum gain. This voltage can be use to control a dual-gate GaAs-FET in front of the ATR2730 to achieve an extended AGC range. By applying an external voltage to the AGC pin, the internal AGC loop can be overdriven.

4903C–DAB–03/07 ATR2730 [Preliminary]

3.4 Voltage-controlled Oscillator

A voltage-controlled oscilla tor supplies an LO signal to the mi xer. An equivalent circuit of this oscillator is shown in Figure 10-2 on page 14. In the application circuits (Figure 10-3 on page 15 and Figure 11-1 on page 16), a ceramic coaxial resonator is applied to the oscillator's TANK and VREF pins. It should be noted that Vref has to be blocked carefully. Figure 11-1 shows a different application where the oscillator is overdriven by an external osc illator. In either case, a DC path at a low impedance must be established between the TANK and VREF pins. The output signal of the oscillator is fed to the LO divider block of t he frequency synthesize r unit which locks the VCO’s frequency on the frequency of a reference oscillator. Figure 9-1 on page 13 shows the typical phase-noise performance of the oscillator in locked state.

3.5 Overall Properties of the Signal Path

The overall gain of this circuit amounts to 24 dB, the gain-control range is about 30 dB. With a new AGC concept in the amplifier and mixer, the ATR2730 reaches better intermodulation dis- tances (DIM3) at higher IF-output power levels.

3.6 Power Save Mode

For VPSM > 2V (pin 1) the power consumption in the analog part (gain-controlled amplifier and mixer and gain-controlled circuitry) is reduc ed by 80%. The VCO and the PLL is not influenced by the power-down mode.

3.7 Frequency Synthesizer

The frequency synthesizer block consists of a reference oscillator, a reference divider, an LO divider in order to divide the frequency of the internal oscillator, a tri-state phase detector, a lock detector, a programmable charge pump, a loop filter amplifier, a control interface, and a test interface. The control interface is accessed by three control pins, CI, SI1 and SI2. The test inter- face provides test signals which represent output signals of the reference and the LO divider. The purpose of this unit is to lock the frequency f VCO of the internal VCO on the frequency f ref of the reference signal applied to the input pin OSCB phase-locked loop according to the following equation: fVCO = SF × fref /S Fref where: SF = 2464, SFref is the scaling factor of the reference divider according to Table 3-1

4903C–DAB–03/07 ATR2730 [Preliminary]

3.8 Reference Oscillator

An on-chip crystal oscillator generates the reference signal which is fed to the reference divider. By connecting a quartz crystal to pins OSCE and OSCB according to Figure 11-2 on page 16 , this oscillator generates a high ly stable reference signal. The ATR2731 (Atmel’s one-chip front-end IC) offers the reference signal at pin FREF. This reference signal (LC filtered to sup- press harmonics) can be used to overdrive the oscillator. In this application (see Figure 11-3 on page 16) the reference signal has to be applied to the pin OSCB and the pin OSCE must be left open.

3.9 Reference Divider

Nine different scaling factors of the reference divider can be selected by different voltage set- tings at the input pins SI1 and SI2: 32, 33 divider factors result in reference oscillator frequencies shown in Table 3-1. Note: 1. These scaling factors result in an output frequ ency of the reference divider of 512 kHz. If har- monics of the Bd. 3 VCO fall in the L-band reception band, these spurious signals can influence the AGC of ATR2730, which could be a problem for small incoming signals. In this case it is possible to switch the reference divider from n ref to nref +1 .

3.10 LO Divider

The LO divider is operated at the fixed division ratio 2464. Assuming the settings described in the section “Reference Divider” , the oscillator's frequency is controlled to be 1261.568 MHz in the locked state, and the output frequency of the RF divider is 512 kHz.

3.11 Phase Comparator, Char ge Pump and Loop Filter

The tri-state phase detector causes the charge pump to source or sink current at the output pin PD depending on the phase relation of its input signals, which are provided by the reference and the RF divider respectively. Using the control pin CI, two different values of this current can be selected, and the charge-pump current can be switched off. The input of the high-gain amplifier (output pin CD), which is implemented in order to construct a loop filter as shown in the application circuit, can be switched to GND by means of the control pin CI (see Table 3-2 on page 8 ). In the application circuit, the loop filter is completed by con- necting the pins PD and CD by an appropriate RC network. Table 3-1. Scaling Factors of the Reference Frequency Voltage at Pin SI1 Voltage at Pin SI2 SF ref Reference Oscillator Frequency GND OPEN 36 18.432 MHz GND VCC 33 – GND GND 48 24.576 MHz OPEN OPEN 65 – OPEN VCC 63 – OPEN GND 64 32.768 MHz VCC OPEN 35 17.920 MHZ VCC VCC 32 16.384 MHz VCC GND 49 –

4903C–DAB–03/07 ATR2730 [Preliminary]

3.12 Lock Detector

An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If a phase lock is detected, the open collector output pin PLCK is set to HIGH. It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the voltage at the control pin CI is chosen to be half the supply voltage, or if this control pin is left open, the lock-detector function is deactivated and the logical value of the PLCK output is undefined.

3.13 Test Interface

If the input control pin CI is left open (high im pedance state), a test signal, which monitors the output frequency of the reference divider, appears at the output pin TI. Analogous to the reference divider, a test signal monitoring the output frequency of the RF divider appears at the test interface output pin TI, if the input control pin CI is connected to V CC/2. Table 3-2. Control Interface (CI) Settings CI PD PLCK TI GND 200 µA Ok – Vs 300 µA Ok – VCC/2 0 µA Undefined RF divider Open Connected to GND Undefined Reference divider

4903C–DAB–03/07 ATR2730 [Preliminary] 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Pins Symbol Value Unit Supply voltage 3, 9, 20 and 28 V CC –0.3 to +9.5 V RF input voltage 25 and 26 V RF 750 mV pp Voltage at pin AGC 18 V AGC 0.5 to 6 V Voltage at pin TH 17 V TH –0.3 to +4.0 V Input voltage at pin TANK (internal oscillator overdriven) 5V TANK 1V pp Current at IF output 19 I IF 4.0 mA Reference input voltage (diff.) 15 OSCB 1 V pp Control input voltage 1, 2, 10 and 27 CI, SI1, SI2, PD –0.3 to +9.5 V PLCK output current 14 I PLCK 0.5 mA PLCK output voltage 14 V PLCK –0.3 to +5.5 V Junction temperature T j 125 °C Storage temperature T stg –40 to +125 °C 5. Operating Range Parameters Pins Symbol Value Unit Supply voltage 3, 9, 20 and 28 V CC 8 to 9.35 V Ambient Temperature T amb –40 to +85 °C 6. Thermal Resistance Parameters Symbol Value Unit Junction ambient SSO28 (mod.) R thJA 50 K/W

4903C–DAB–03/07 ATR2730 [Preliminary] 7. Electrical Characteristics Operating conditions: VCC = 8.5V, Tamb = 25° C unless otherwise specified. (See application circuit Figure 10-3 on page 15.) No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.1 Supply current (max. gain) pRF = –60 dBm VPSM < 0.5V IS,MAX 40 48 mA A 1.2 Supply current (min. gain) pRF = –10 dBm VPSM < 0.5V IS,MIN 41 50 mA B

1.3 Supply current

(power-save mode) pRF = –10 dBm VPSM > 2V IS,PD 20 24 mA A

2 Amplifier Mixer Pin 26 26 → 19

2.1 Maximum conversion gain p RF = –60 dBm g c,max 20 24 dB A

2.2 Minimum conversion gain p RF = –15 dBm g c,min –8d B B

2.3 AGC range ∆gc 28 32 dB A

2.4 Third-order 2-tone

pRF1 + pRF2 = –10 dBm pRF1 + pRF2 = –15 dBm dim3 30 dB dB B A

2.5 DSB noise figure

(50Ω system) Maximum gain Minimum gain NF 10 dB dB D 3R F I n p u t 2 6

3.1 Frequency range f in,RF 1400 1550 MHz C

3.2 Maximum input power dim3 ≥ 20 dB p in,max,RF –6d B m C

3.3 Input impedance Z in,RF 200 || 1 Ω || pF D

4.1 Frequency range f out,IF 150 250 MHz C

4.2 Output impedance Z out,IF 50 Ω D

4.3 Voltage standing wave ratio VSWR IF 2.0 D 5G a i n C o n t r o l

5.1 Threshold adjustment External resistor 17 R TH 100 k Ω D

5.2 Charge pump current

pRF = –10 dBm VAGC = 3.5V 18 I CP ,P 75 100 125 µA A pRF = –60 dBm VAGC = 3.5V ICP ,N –125 –100 –75 µA A

5.3 Minimum gain control

voltage pRF = –10 dBm 18 V AGCmin 0.1 0.6 V A

5.4 Maximum gain control

voltage pRF = –60 dBm 18 V AGCmax 5.5 5.75 V A 6V C O 5 6.1 Frequency f LO 1000 1261.568 1500 MHz

6.2 Phase noise 1 kHz distance L 1kHz –75 dBc/Hz C

6.3 Minimum input power VCO overdriven, see

“Application Circuit” (Figure 10-3 on page 15) pLO,MIN –11 dBm C

6.4 Maximum input power p LO,MAX –5d B m C

7 Frequency Synthesizer

7.1 RF divide factor SF 2464 A

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4903C–DAB–03/07 ATR2730 [Preliminary]

7.2 Reference divide factor

SI1 = GND, SI2 = GND SI1 = GND, SI2 = VCC SI1 = GND, SI2 = open SI1 = VCC, SI2 = GND SI1 = VCC, SI2 = VCC SI1 = VCC, SI2 = open SI1 = open, SI2 = GND SI1 = open, SI2 = VCC SI1 = open, SI2 = open SF ref A

7.3 Input frequency range f

7.4 Input sensitivity 15 V refs 30 mV rms C

7.5 Maximum input signal 15 V refmax 300 mV rms C

7.6 Input impedance Single-ended Z ref 2.7k || 2.5 k Ω || pF D

8 Phase Detector

8.1 Charge-pump current

Pin CI connected to GND 13 I PD2 160 200 240 µA A Pin CI connected to VCC IPD1 240 300 360 µA A Pin CI connected to VCC/2 I PD1,tri 100 nA A 8.2 Output voltage PD Pin CI open 13 V PD 0.3 V A

8.3 Internal reference frequency f PD 512 kHz B

8.4 Typical tuning voltage range 12 V tune 0.3 5 V C

9 Lock Indication PLCK 14

9.1 Leakage current V PLCK = 5.5V I PLCK 10 µA A 9.2 Saturation voltage I PLCK = 0.25 mA V PLCK,sat 0.5 V A

10 Control Inputs SI 2 and 27

10.1 Input voltage Pin connected to GND V L 00 . 1 V CC A

10.2 Pin open V M Open A

10.3 Pin connected to V CC VH 0.9 1 V CC A

11 Control Input CI 10

11.1 Input voltage Pin connected to GND V L 00 . 1 V CC A 11.2 Pin connected to V CC/2 V M 0.5 V CC A

11.3 Pin open V open Open A

11.4 Pin connected to V CC VH 0.9 1 V CC A

12 Test Interface TI 11

12.1 Reference test frequency Pin CI open f test,ref 512 kHz B

12.2 LO test frequency Pin CI = V CC/2 f test,LO 512 kHz B

12.3 Voltage swing Rload ≥ 1M Ω, Cload ≤ 15 pF ,

Pin CI open or VCC/2 Vsw 400 mV pp C

13 Power-save Mode PSM 1

13.1 PSM not active V PSM 0.6 V A 13.2 PSM active V PSM 2.0 V A 7. Electrical Characteristics (Continued) Operating conditions: VCC = 8.5V, Tamb = 25° C unless otherwise specified. (See application circuit Figure 10-3 on page 15.) No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4903C–DAB–03/07 ATR2730 [Preliminary] 9. Phase-noise Performance Measurement conditions: Values acquired at pin 19 with HP 70000 spectrum analyzer. RF input (pin 26) is blocked with 100 pF to GND. A low phase-noise signal generator (Marconi® 2042) was taken as PLL reference. Figure 9-1. Phase-noise Performance Operating Conditions: fREF = 17.92 MHz, –10 dB, IPD = 200 µA Center 1.261 568 GHz Span 50.00 kHz RB 100 Hz VB 100 Hz RL -29.29 dBm ATTEN 10 dB 10.00 dB/DIV ST 15.00 sec < -75 dBc/Hz

4903C–DAB–03/07 ATR2730 [Preliminary] 10. Equivalent Circuits Figure 10-1. AGC Control Circuit Figure 10-2. VCO Circuit

60 MHz

550 MHz

Resonator: Ceramic coaxial resonator Murata ® 3 × 3 mm, 1.6 GHz DRR030 KE1R600TC Resonator VREF BBY5147 kΩ TANK15 pF 1 pF 100 pF 1.8 pF VTune VCC

4903C–DAB–03/07 ATR2730 [Preliminary] Figure 10-3. Application Circuit Example: reference divider factor = 35, fREF = 17.92 MHz, charge-pump current = 200 µA PLCK TI CD PD CI VCC2 GND TANK GND GND VREF PSM SI2 VCC1 2135 468 7 9 13 14 1110 12 2728 OSCB IF AGC TH OSCE VCC3 GND GND GND GND NRF VCC4 SI1 RF 8.5V 10 nF 100 pF 26 24 25 23 21 22 20 16 15 1819 17 100 pF 100 pF 100 kΩ 1 kΩ1 kΩ47 kΩ 56 kΩ IF RF VAGC 8.5V Power save 8.5V 100 pF 100 pF 100 pF 10 nF 100 pF 8.5V 10 nF ATR2730 1 nF 1 nF 15 pF D1 3.3 nF 1) 100 pF 1) 3.3 nF 1) 1) optional 1.8 pF 10 nF 68 pF Quartz crystal 1 nF 1 nF 1 pF 3.3 µF 100 pF 33 pF Lock indication 18 pF

4903C–DAB–03/07 ATR2730 [Preliminary] 13. Package Information 14. Revision History 12. Ordering Information Extended Type Number Package Remarks ATR2730-TLSY SSO28 Tube, Pb-free ATR2730-TLPY SSO28 Taped and reeled according to IEC 286-3, 180 µm size, Pb-free ATR2730-TLQY SSO28 Taped and reeled according to IEC 286-3, 330 µm size, Pb-free Dimensions in mm specifications according to DIN technical drawings 9.35-0.25 1528 141 Issue: 1; 10.03.04 Drawing-No.: 6.543-5056.03-4 8.45±0.05 1.3±0.05 0.15 ±0.05 0.65±0.05 5.4±0.2 4.4±0.1 6.45±0.150.25±0.05 0.05+0.1 Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4903C-DAB-03/07 • Put datasheet in a new template

• Section 12 “Ordering Information” on page 17 changed

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