ATR2406

ATR2406_06 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Fully Integrated Low IF Receiver
• Fully Integrated GFSK Modulator for 72, 144, 288, 576 and 1152 Kbits/s
• High Sensitivity of Typically –93 dBm Due to Integrated LNA
• High Output Power of Typically +4 dBm
• Multi-channel Operation – 95 Channels – Support Frequency Hopping (ETSI) and Digital Modulation (FCC)
• Supply-voltage Range 2.9V to 3.6V (Unregulated)
• Auxiliary Voltage Regulator on Chip (3.2V to 4.6V)
• Low Current Consumption
• Few Low-cost External Components
• Integrated Ramp-signal Generator and Power Control for an Additional Power Amplifier
• Low Profile Lead-free Plastic Package QFN32 (5 mm × 5 mm × 0.9 mm)
• RoHs Compliant

Applications

• High-tech Multi-user Toys
• Wireless Game Controllers
• Telemetry
• Wireless Audio/Video
• Electronic Point of Sales
• Wireless Head Set
• FCC CFR47, Part 15, ETSI EN 300 328, EN 300 440 and ARIB STD-T-66 Compliant Radio Links

Description

The ATR2406 is a single chip RF transceiver intended for applications in the 2.4-GHz ISM band. The QFN32-packaged IC is a complete transceiver including image rejec- tion mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, power-ramping generator for external power amplifier, integrated synthesizer, and a fully integrated VCO and TX filter. No mechanical adjustment is necessary in production. The RF transceiver offers a clock recovery function on-chip. Low-IF 2.4-GHz ISM Transceiver ATR2406 4779L–ISM–09/06

4779L–ISM–09/06 ATR2406 Table 2-1. Pin Description Pin Symbol Function PU_REG Power-up input for auxiliary regulator REF_CLK Reference frequency input RSSI Received signal strength indicator output VS_IFD Digital supply voltage VS_IFA Analog supply voltage for IF circuits RX-CLOCK RX-CLOCK, if RX mode with clock recovery is active IC Internally connected. Connect to VS if internal AUX regulator is not used IREF External resistor for band-gap reference REG_CTRL Auxiliary voltage regulator control output VREG Auxiliary voltage regulator output VS_REG Auxiliary voltage regulator supply voltage REG_DEC Decoupling pin for VCO_REG VREG_VCO VCO voltage regulator VTUNE VCO tuning voltage input CP Charge-pump output VS_SYN Synchronous supply voltage VS_TRX Transmitter receiver supply voltage RX_IN2 Differential receiver input 2 RX_IN1 Differential receiver input 1 TX_OUT TX driver amplifier output RAMP_OUT Ramp generator output for PA power ramping IC Internally connected, do not connect on PCB IC Internally connected, do not connect on PCB RX_ON RX control input TX_ON TX control input nOLE Open loop enable input PU_TRX RX/TX/PLL/VCO power-up input RX_DATA RX data output TX_DATA TX data input CLOCK 3-wire-bus: Clock input DATA 3-wire-bus: Data input ENABLE 3-wire-bus: Enable input Paddle GND Ground

4779L–ISM–09/06 ATR2406 Functional Description 3.1 Receiver The RF signal at RF_IN is differentially fed through the LNA to the image rejection mixer IR_MIXER, driving the integrated low-IF band-pass filter. The IF frequency is 864 kHz. The limiting IF_AMP with an integrated RSSI function feeds the signal to the digital demodulator DEMOD. No tuning is required. Data slicing is handled internally. 3.2 Clock Recovery For a 1152-kBit/s data rate, the receiver has a clock recovery function on-chip. The receiver includes a clock recovery circuit which regenerates the clock out of the received data. The advantage is that this recovered clock is synchronous to the clock of the transmitting device (and thus to the transmitted data), which significantly reduces the load of the process- ing microcontroller. The falling edge of the clock is the optimal sampling position for the RX_Data signal, so at this event the data must be sampled by the microcontroller. The recovered clock is available at pin 6. 3.3 Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian filter (GF) and fed to the fully integrated VCO operating at twice the output frequency. After modulation, the signal is frequency divided by 2 and fed to the internal preamplifier PA. This preamplifier supplies typi- cally +4 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled internally so that spu- rious requirements are fulfilled. 3.4 Synthesizer The IR_MIXER, the PA, and the programmable counter (PC) are driven by the fully integrated VCO, using on-chip inductors and varactors. The output signal is frequency divided to supply the desired frequency to the TX_DRIVER, the 0/90 degree phase shifter for the IR_MIXER, and to be used by the PC for the phase detector (PD) (fPD = 1.728 MHz). Open loop modula- tion is supported. 3.5 Power Supply An integrated band-gap–stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided.

4779L–ISM–09/06 ATR2406 Electrostatic sensitive device. Observe precautions for handling. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage auxiliary regulator VS –0.3 +4.7 V Supply voltage VS –0.3 +3.6 V Control voltages Vcontr –0.3 VS V Storage temperature Tstg –40 +125 Input RF level PRF +10 dBm ESD protection VESD_ana TBD V VESD_dig TBD V Operating Range Parameters Symbol Min. Max. Unit Supply voltage VS 2.9 3.6 V Auxiliary regulator supply voltage VS_BATT 3.2 4.6 V Temperature ambient Tamb –10 +60 Input frequency range fRX 2400 2483 MHz

4779L–ISM–09/06 ATR2406

Electrical Characteristics

VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply 1.1 Supply voltage With AUX regulator VS 3.2 3.6 4.6 V 1.2 Supply voltage Without AUX regulator VS 2.9 3.0 3.6 V 1.3 RX supply current CW mode (peak current) IS mA Burst mode at 10 Kbits/s(4) IS 625 µA 1.4 TX supply current CW mode (peak current) IS mA Burst mode at 10 Kbits/s(4) IS 500 µA 1.5 Battery lifetime of a remote control application using an AVR® See Section 10. ”Appendix: Current Calculations for a Remote Control” on page 20 1.6 Supply current in power-down mode With AUX regulator PU_TRX = 0; PU_REG = 0 IS < 1 µA 1.7 Supply current in power-down mode Without AUX regulator PU_TRX = 0; PU_REG = 0 IS < 1 µA Voltage Regulator 2.1 AUX regulator VREG 3.0 V 2.2 VCO regulator VREG_VCO 2.7 V Transmitter Part 3.1 TX data rate 72/144/288/576/1152 kBits/s 3.2 Output power PTX dBm 3.3 TX data filter clock 9 taps in filter fTXFCLK 10.368/13.824 MHz 3.4 Frequency deviation To be tuned by GFCS bits GFFM_nom ±400 kHz 3.5 Frequency deviation scaling(3) GFFM = GFFM_nom × GFCS (Refer to bus protocol D9 to D11) GFCS 130 3.6 Frequency drift With standard loop filter and slot length of 1400 µs (Refer to the application note “ATR2406 Loop Filter and Data Rates”) ∆fo (drift) ±40 kHz 3.7 Harmonics BW = 100 kHz(1) –41.2 dBm 3.8 Spurious emissions 30 – 1000 MHz 1 – 12.75 GHz 1.8 – 1.9 GHz 5.15 – 5.3 GHz BW = 100 kHz(1) –57 –57 –57 –57 dBm dBm dBm dBm Ramp Generator, Pin 21 4.1 Minimum output voltage TX_ON = low Vmin 0.7 V 4.2 Maximum output voltage Refer to bus protocol D12 to D13 Vmax 1.1 1.9 V 4.3 Rise time tr µs 4.4 Fall time tf µs Notes: 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Fre- quency (Smart RF) firmware. Conducted measured. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter. For further information refer to the application notes. 3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. 4. Burst mode with 0.9% duty cycle

4779L–ISM–09/06 ATR2406 Receiver Part 5.1 RX input impedance Differential Zin 170 + j0 Ω 5.2 Sensitivity At input for BER ≤10-3 at 1152 kBits/s(1) –93 dBm 5.3 Third order input intercept point IIP3 –15 dBm 5.4 Intermodulation rejection BER < 10-3, wanted at -83 dBm, level of interferers in channels N + 2 and N + 4(1) IM3 dBc 5.5 Co-channel rejection BER < 10-3, wanted at –76 dBm(1) RCO –11 dBc 5.6 Adjacent channel rejection ±1.728 MHz BER < 10-3, wanted at –76 dBm, adjacent level referred to wanted channel level(1) Ri (N – 1) dBc 5.7 Bi-adjacent channel rejection ±3.456 MHz BER < 10-3, wanted at –76 dBm, bi-adjacent level referred to wanted channel level(1) Ri (N – 2) dBc 5.8 Rejection with ≥ 3 channels separation ≥±5.128 MHz BER < 10-3, wanted at –76 dBm, n ≥3 adjacent level referred to wanted channel level(1) Ri (n ≥ 3) dBc 5.9 Out of band rejection > 6 MHz BER < 10-3, wanted at –83 dBm at

2.45 GHz(1)

Bldf>6MHz dBc 5.10 Out of band rejection

2300 MHz to 2394 MHz

2506 MHz to 2600 GHz

BER < 10-3, wanted at –83 dBm at 5.11 Out of band rejection

30 MHz to 2300 MHz

2600 MHz to 6 GHz

BER < 10-3, wanted at –83 dBm at 6.1 Maximum RSSI output voltage Under high RX input signal level VRSSImax 2.1 V 6.2 RSSI output voltage, monotonic over range –96 dBm to –36 dBm With –33 dBm at RF input With –96 dBm at RF input VRSSI 1.9 0.1 V V VCO 7.1 Oscillator frequency defined at TX output Over full temperature range(1) 2400 2483 MHz 7.2 Frequency control voltage range VVTUNE 0.5 VCC – 0.5 V 7.3 VCO tuning input gain defined at TX output GVCO 240 MHz/V Electrical Characteristics (Continued) VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Notes: 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Fre- quency (Smart RF) firmware. Conducted measured. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter. For further information refer to the application notes. 3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. 4. Burst mode with 0.9% duty cycle

4779L–ISM–09/06 ATR2406 Synthesizer 8.1 External reference input frequency D7 = 0 D7 = 1 REF_CLK 10.368 13.824 MHz MHz 8.2 Sinusoidal input signal level (peak-to-peak value) AC-coupled sine wave REF_CLK 500 1000 mVPP 8.3 Scaling factor prescaler SPSC 8.4 Scaling factor main counter SMC 86/87/88/89 8.5 Scaling factor swallow counter SSC Phase Detector 9.1 Phase detector comparison frequency fPD 1728 kHz Charge-pump Output 10.1 Charge-pump output current VCP = 1/2 VCC ICP mA 10.2 Leakage current VCP = 1/2 VCC IL ±100 1000 pA Timing Conditions(1)(2) 11.1 Transmit to receive time Reference clock stable TX →RX time 200 µs 11.2 Receive to transmit time Reference clock stable RX →TX time 200 µs 11.3 Channel switch time Reference clock stable CS time 200 µs 11.4 Power down to transmit Reference clock stable PD →TR time 250 µs 11.5 Power down to receive Reference clock stable PD →RX time 200 µs 11.6 Programming register Reference clock stable PRR time µs 11.7 PLL settling time Reference clock stable PLL set time 200 µs Interface Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE 12.1 HIGH-level input voltage Logic 1 VIH 1.4 3.1 V 12.2 LOW-level input voltage Logic 0 VIL –0.3 +0.4 V 12.3 HIGH-level output voltage Logic 1 VOH 3.1 V 12.4 LOW-level output voltage Logic 0 VOL V 12.5 Input bias current Logic 1 or logic 0 Ibias µA 12.6 3-wire bus clock frequency fCLKmax MHz Electrical Characteristics (Continued) VS = 3.6V with AUX regulator, Tamb = 25°C, unless otherwise specified No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Notes: 1. Measured and guaranteed only on the Atmel® evaluation board, including microstrip filter, balun, and Smart Radio Fre- quency (Smart RF) firmware. Conducted measured. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter. For further information refer to the application notes. 3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. 4. Burst mode with 0.9% duty cycle

4779L–ISM–09/06 ATR2406 PLL Principle Figure 7-1. PLL Principle Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = 1728 kHz × (SMC × 32 + SSC) Phase frequency Divider by 2 PA driver detector PD VCO Mixer fPD = 1728 kHz Gaussian filter GF Reference counter RC REF_CLK

13.824 MHz

REF_CLK Baseband controller

10.368 MHz

4779L–ISM–09/06 ATR2406 Table 7-1 shows the LO frequencies for RX and TX in the 2.4-GHz ISM band. There are 95 channels available. Since the ATR2406 supports wideband modulation with 400-kHz devia- tion, every second channel can be used without overlap in the spectrum. 7.1 TX Register Setting The following 16-bit word has to be programmed for TX. Note: D12 and D13 are only relevant if ramping generator in conjunction with external PA is used, otherwise it can be programmed 0 or 1. The VRAMP voltage is used to control the output power of an external power amplifier. The voltage ramp is started with the TX_ON signal. These bits are only relevant in TX mode. Table 7-1. LO Frequencies Mode fIF / kHz Channel fANT / MHz fVCO / MHz divided by 2 SMC SSC N TX 2401.056 2401.056 2779 2401.920 2401.920 2780 ... ... ... ... ... ... C93 2481.408 2481.408 2872 C94 2482.272 2482.272 2873 RX 864 2401.056 2401.920 2780 2401.920 2402.784 2781 ... ... ... ... ... ... C93 2481.408 2482.272 2873 C94 2482.272 2483.136 2874 MSB LSB Data bits D15 D14 D13 D12 D11 D10 PA GFCS RC MC SC Table 7-2. Output Power Settings with Bits D12 - D13 PA (Output Power Settings) D13 D12 RAMP_OUT (Pin 21) 1.3V 1.35V 1.4V 1.75V

4779L–ISM–09/06 ATR2406 7.2 RX Register Setting There are two RX settings possible. For a data rate of 1152 kBits/s, an internal clock recovery function is implemented. 7.3 Register Setting Without Clock Recovery Must be used for data rates below 1.152 Mbits/s. Note: X values are not relevant and can be set to 0 or 1. 7.4 RX Register Setting with Internal Clock Recovery Recommended for 1.152-Mbit/s data rate. The output pin of the recovered clock is pin 6. The falling edge of the recovered clock signal samples the data signal. Note: X values are not relevant and can be set to 0 or 1. 7.5 PLL Settings RC, MC and SC bits control the synthesizer frequency as shown in Table 7-3, Table 7-4 on page 12 and Table 7-5 on page 12. Formula for calculating the frequency: TX frequency: fANT = 864 kHz × (32 × SMC + SSC) RX frequency: fANT = 864 kHz × (32 × SMC + SSC – 1) MSB LSB Data bits D15 D14 D13 D12 D11 D10 X X X X X RC MC SC MSB Data bits D24 D23 D22 D21 D20 D19 D18 D17 D16 LSB Data bits D15 D14 D13 D12 D11 D10 X X X X X RC MC SC Table 7-3. PLL Settings of the Reference Counter Bit D7 RC (Reference Counter) CLK Reference

4779L–ISM–09/06 ATR2406 7.6 GFCS Adjustment The Gaussian filter control setting (GFCS) is used to compensate for production tolerances by tuning the modulation deviation in production to the nominal value of 400 kHz. These bits are only relevant in TX mode. Table 7-4. PLL Settings of the Main Counter Bits D5 to D6 MC (Main Counter) SMC Table 7-5. PLL Settings of the Swallow Counter Bits D0 to D4 SC (Swallow Counter) SSC ... ... ... ... ... ... Table 7-6. GFCS Adjustment of Bits D9 - D11 GFCS D11 D10 GFCS 60% 70% 80% 90% 100% 110% 120% 130%

4779L–ISM–09/06 ATR2406 7.7 Control Signals The various transceiver functions are activated by the following control signals. A timing pro- posal is shown in Figure 7-3 on page 14 7.8 Serial Programming Bus The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE). After setting the enable signal to low, the data is transferred bit by bit into the shift register on the rising edge of the clock signal, starting with the MSBit. When the enable signal has returned to high, the programmed information is active. Additional leading bits are ignored and there is no check made of how many clock pulses arrived during enable low. The programming of the transceiver is done by a 16-bit or 25-bit data word (for the RX clock recovery mode). 7.9 3-wire Bus Timing Figure 7-2. 3-wire Bus Protocol Timing Diagram Table 7-7. Control Signals and Functions Signal Functions PU_REG Activates AUX voltage regulator and the VCO voltage regulator supplying the complete transceiver PU_TRX Activates RX/TX blocks RX_ON Activates RX circuits: DEMOD, IF AMP, IR MIXER TX_ON Activates TX circuits: PA, RAMP GEN, Starts RAMP SIGNAL at RAMP_OUT nOLE Disables open loop mode of the PLL DATA CLOCK ENABLE TT TEC TS TC TH TL TPER Table 7-8. 3-wire Bus Protocol Table Time between two protocols TT 250 ns

4779L–ISM–09/06 ATR2406 Figure 7-3. Example TX and RX Timing Diagram Data 16/25 bits 16 bits REF_CLK REF_CLK Data Pin Name MODE Power-down Power-up Programming Active RX-slot Power-down optional Power-up optional Programming Active TX-slot Power-down > 40 µs > 200 µs > 50 µs valid signal > 200 µs > 40 µs > 50 µs VS 0 V 0 V VS PU_REG Pin 1 PU_TRX Pin 27 TX_DATA Pin 29 3W_CLK Pin 30 3W_DATA Pin 31 3W_ENA Pin 32 nOLE Pin 26 REF_CLK Pin 2 RX_ON Pin 24 TX_ON Pin 25 RX_DATA Pin 28 RSSI Pin 3 RAMP_OUT Pin 21 connected to RAMP_IN of optional PA Signals from TRX (Output) Signals to TRX (Input) Preamble (1-0-1-0) Note: 1. Keep input signals on low level during power-down state of TRX

4779L–ISM–09/06 ATR2406 7.10 Received Signal Strength Indication (RSSI) The RSSI is given as an analog voltage at the RSSI pin. A typical plot of the RSSI value is shown in Figure 7-4. Figure 7-4. Typical RSSI Value versus Input Power Table 7-9. Description of the Conditions/States Condition ATR2406 is switched off and the supply current is lower than 1 µA. Power up ATR2406 is powered up by toggling PU_REG and PU_TRX to high. PU_REG enables the external AUX regulator transistor including VCO regulator. PU_TRX enables internal blocks like the PLL and the VCO. Depending on the value of the external capacitors (for example, at the AUX regulator, if one is used), it is necessary to wait at least 40 µs until the different supply voltages have settled. Programming The internal register of the ATR2406 is programmed via the three-wire interface. At TX, this is just the PLL (transmit channel) and the deviation (Gaussian filter). At RX, this is just the PLL (receive channel) and, if the clock recovery is used, also the bits to enable this option. At the start of the three-wire programming, the enable signal is toggled from high to low to enable clocking the data into the internal register. When the enable signal rises again to high, the programmed data is latched. This is the time point at which the settling of the PLL starts. It is necessary to wait the settling time of 200 µs so that the VCO frequency is stable. The reference clock needs to be applied to ATR2406 for at least the time when the PLL is in operation, which is the programming state (C3) and the active slot (C4, C5). Out of the reference clock, several internal signals are also derived, for example, the Gaussian filter circuitry and TX_DATA sampling. This is the receive slot where the transmit burst is received and data as well as recovered clock are available. This is the active transmit slot. As soon as TX_DATA is applied to ATR2406, the signal nOLE toggles to low which enables modulation in open-loop mode. The preamble (1-0-1-0 pattern) should start being sent at the start of TX_ON. 0.0 0.5 1.0 1.5 2.0 2.5 -130 -110 -90 -70 -50 -30 -10 RF Level (dBm) RSSI Level (V)

4779L–ISM–09/06 ATR2406 Application Circuit The ATR2406 requires only a few low-cost external components for operation. A typical appli- cation is shown in Figure 8-3 on page 17. 8.1 Typical Application Circuit Figure 8-1. Microcontroller Interfacing with General Purpose MCU, Pin Connections between Microcontroller and ATR2406 Figure 8-2. Example with AVR MCU Note: 1. XTAL: for example, XRFBCC-NANL; 13.824 MHz, 10 ppm Order at: Taitien Electronic, Taitien Specific No.: A009-x-B26-3, SMD Microcontroller ATR2406 Configuration and control RF-DATA Interface TX_DATA RX_DATA RX-CLOCK DATA CLOCK ENABLE Ctrl_Lines XTAL_OUT REF_CLK XTAL(1) ATR2406 RF_CTRL RF_DATA AVR_MCU USART GPIO R

13.824 MHz XTAL

REF_CLK nOLE ENABLE CLOCK DATA TX_ON RX_ON PU_TRX PU_REG GPIO1 GPIO2 TXD RXD XCK GPIO3 GPIO4 GPIO5 TX_DATA RX_DATA RX-CLOCK RSSI

4779L–ISM–09/06 ATR2406 Figure 8-3. PU_REG REF_CLK RSSI VS_IFD VS_IFA RX-CLOCK IC IREF ENABLE DATA CLOCK TX_DATA RX_DATA PU_TRX nOLE TX_ON RX_ON IC IC RAMP_OUT TX_OUT RX_IN1 RX_IN2 VS_TRX REG_CTRL VREG VS_REG REG_DEC VREG_VCO VTUNE CP GND ENABLE DATA CLOCK TX_DATA RX_DATA PU_TRX nOLE TX_ON PU_REG REF_CLK RSSI C11 18p C24 4p7 62k C16 4µ7 C15 100n C23 4n7 C12 100n C13 4µ7 BC808 VS C17 NC C19 C18 68p 470n C21 2n2 G VS_SYN C14 NC C20 22n 1k0 C10 1p8 µStrip-balun RX_ON TP1 TP2 1p5 µStrip VBATT µStrip 5p6 IC2 ATR2406 IC2P GND Slug GND2 GND7 GND8 GND9 GND4 GND5 GND6 GND1 GND3 RX-CLOCK 390p C20, C21, COG dielectric RAMP_OUT RAMP J26 µStrip Lowpassfilter 2p2 2p2 1p8 RFOUT (Ant) J24 Select integrated F-antenna or SMA connector by setting the 0R resistor NC ANT2 ANT GND GND NC ANT F-antenna SMASI VBATT J11 VBATT TX_ON TX_DATA PU_TRX J12 J13 J14 J15 J16 J17 ENABLE DATA nOLE PU_REG RX-CLOCK RX_DATA CLOCK RX_ON J18 J19 J20 J21 VLSI Connector J10 RSSI REF_CLK 1k5 1k5

4779L–ISM–09/06 ATR2406 PCB Layout Design Figure 9-1. PCB Layout ATR2406-DEV-BOARD

4779L–ISM–09/06 ATR2406 Table 9-1. Bill of Materials Part Value Part Number Vendor Package Comment 5.6 pF GJM1555C1H5R6CB01 or GRM1555C1H5R6DZ01 Murata® 0402 C3, C10 1.8 pF GJM1555C1H1R8CB01 or GRM1555C1H1R8CZ01 Murata 0402 390 pF GRM1555C1H391JA01 Murata 0402 4.7 pF GJM1555C1H4R7CB01 or GRM1555C1H4R7CZ01 Murata 0402 NC C6, C7 2.2 pF GJM1555C1H2R2CB01 or GRM1555C1H2R2CZ01 Murata 0402 1.5 pF GJM1555C1H1R5CB01 or GRM1555C1H1R5CZ01 Murata 0402 C11 18 pF GRM1555C1H180JZ01B Murata 0402 C12, C15 100 nF GRM155R71C104KA88B Murata 0402 C13, C16 4.7 µF B45196H2475M109 Epcos® 3216 Optional(2) C14 1 nF GRM15R71H102KB01 Murata 0402 NC C17 3.3 nF GRM15R71H332KB01 Murata 0402 NC C18 68 pF GRM1555C1H680JZ01B Murata 0402 C19 470 nF GRM18F51H474ZB01 (0402) or GRM188R61A474KA61B (0603) Murata C20 22 nF, COG GRM21B5C1H223JA01 Murata 0805 COG, important for good RF performance C21 2.2 nF, COG GRM1885C1H222JA01 Murata 0603 COG, important for good RF performance C23 4.7 nF GRM155R71H472KA01B Murata 0402 C24 4.7 pF GRM1555C1H4R7CZ01B Murata 0402 8.2 nH WE-MK0402 744784082 Würth® Electronic 0402 NC, microstrip used 62 kΩ 62k, ≤5% Vishay® 0402 1.0 kΩ 1k0, ≤5% Vishay 0402 1.5 kΩ 1k5, ≤5% Vishay 0402 Ref_Clk level, optional(1) 1.5 kΩ 1k5, ≤5% Vishay 0402 Ref_Clk level, optional(1) IC2 ATR2406 ATR2406 Atmel MLF32 BC808-40 BC808-40, any standard type can be used, but it is important that be “–40”! Vishay, Philips®, etc. SOT-23 Optional(2) MSUB FR4 Notes: 1. Not necessary if supplied RefClk level is within specification range 2. If no AUX regulator is used, then T1 and C16 can be removed and a jumper is needed from the collector to the emitter pad. Additionally, pin 7 of the ATR2406 has to be connected to pin 4 or pin 5 to use the integrated F antenna, set jumper R2 (0R resistor 0603) Table 9-2. Parts Count Bill of Materials Parts Count Required (Minimal BOM) Optional (Depending on Application) Capacitors 0402 Capacitors >0402 Resistors 0402 Inductors 0402 Semiconductors

4779L–ISM–09/06 ATR2406 10. Appendix: Current Calculations for a Remote Control Assumptions: Basic Numbers: Amount of Current Needed to Transmit One Packet: Protocol A data packet consists of 24 bytes. 24 bytes = 240 bits (USART connection) Tpacket_length = 210 µs at 1.152 Mbits/s Channel The system will use five predefined channels for frequency hopping spread spectrum (FHSS) which gives improved immunity against interferers Loop filter Loop filter settling time will be 110 µs Handheld device If not in use, the handheld device will be in power-down mode with the AVR’s watchdog timer disabled. The AVR power-down current is typically 1.25 µA. If an external voltage regulator is used, additional power-down current has to be taken into account Base station device The base station will periodically scan all the channels of the used subset. The base station will stay on one channel for 2 seconds. If the base station receives a correct packet, an acknowledge will be returned to the handheld device. The power consumption of the base station device is not power-sensitive, as this part of the application is normally mains powered Peak current ATR2406 in TX at 1.152 Kbits/s 42 mA Peak current ATR2406 in RX at 1.152 Kbits/s 57 mA Peak current ATR2406 with synthesizer running 26 mA Current ATmega88 active 5 mA Current ATmega88 power down (no WDT) 1.25 µA Current ATmega88 power down (+ WDT) 5 µA Loop settling time of ATR2406 110 µs Configuration of ATR2406 30 µs Time needed for exchanging a packet at 1.152 Kbits/s 210 µs Q1 = (0.005A + 0.026A) × 5030 µs = 155 µAs (charge up time ATR2406 + AVR internal calculations) Q2 = (0.005A + 0.026A) × 30 µs = 0.93 µAs (charge for configuring the ATR2406) Q3 = (0.005A + 0.026A) × 110 µs = 3.41 µAs (charge for settling the loop filter) Q4 = (0.005A + 0.042A) × 210 µs = 9.87 µAs (charge for transmitting the packet) Q5 = (0.005A) × 250 µs = 1.25 µAs (charge for turn around (TX to RX, RX to TX, etc.)) Q6 = (0.005A + 0.026A) × 30 µs = 0.93 µAs (charge for configuring the ATR2406) Q7 = (0.005A + 0.026A) × 60 µs = 1.86 µAs (charge for settling the loop filter) Q8 = (0.005A + 0.057A) × 50 µs = 3.10 µAs (charge until valid data can be received) Q9 = (0.005A + 0.057A) × 210 µs = 13.02 µAs (charge for receiving the packet) Q10 = (0.005A + 0.057A) × 50 µs = 3.1 µAs (charge for latency before receiving)

4779L–ISM–09/06 ATR2406 A successful packet exchange needs the following charge Q = Q1 + Q2 + Q3 + Q4 + Q5 + Q6 + Q7 + Q8 + Q9 + Q10 = 192.47 µAs As the described system is a FHSS system with 5 different channels, the system has to do this up to five times before the packet is acknowledged by the base station. The average will be 2.5 times. In the case of an interfered environment, some more retries may be required; there- fore, it is assumed the factor will be 3. The power-up time is included only once, as the cycle will be completed without powering up and down the handheld in order to be as power efficient as possible. Average current needed for a packet exchange: 155 µAs + (37.5 µAs × 3) = 267.5 µAs If the device will be used 1000 times a day →3.1 µA Average current in active mode: → System Power Down current: Current ATmega88: 1.25 µA Current ATR2406: 1.0 µA Current VREG (+ ShutDown): 2.75 µA Assumed average power-down current is 5 µA. →Overall power consumption is 8.1 µA It is assumed the system uses a small battery with a capacity of 100 mAh. This is 100.000 µAh. →Battery lifetime will be around: 12345 hours = 514 days = 1.4 years. The most important factor is to get the power-down current as low as possible! Example: Assume a system where the handheld is used just 10 times per day. →Iactive = 0.031 µA and assuming the power-down current of this device is just 4 µA. →I = 0.031 µA + 4 µA = 4.03 µA →Battery lifetime will be around 24807 hours = 1033 days = 2.83 years. →Power-down current is the main factor influencing the battery lifetime.

4779L–ISM–09/06 ATR2406 12. Package Information 11. Ordering Information Extended Type Number Package Remarks MOQ ATR2406-PNQG QFN32 - 5x5 Taped and reeled, Pb-free 4000 ATR2406-DEV-BOARD RF module ATR2406-DEV-KIT2 Complete evaluation kit and reference design ATR2406 + ATmega88

4779L–ISM–09/06 ATR2406 13. Recommended Footprint/Landing Pattern Figure 13-1. Recommenced Footprint/Landing Pattern Table 13-1. Recommended Footprint/Landing Pattern Signs Sign Size A 3.2 mm B 1.2 mm C 0.3 mm a 1.1 mm b 0.3 mm c 0.2 mm d 0.55 mm e 0.5 mm

4779L–ISM–09/06 ATR2406 14. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4779L-ISM-08/06

• Table “Electrical Characteristics” on pages 6 to 8 changed
• Section 10 “Appendix: Current Calculations for a Remote Control” on pages 20 to 21 changed
• Table “Ordering Information” on page 22 changed
• Minor corrections to grammar and style throughout document 4779K-ISM-06/06
• Put datasheet in a new template
• Table “Electrical Characteristics” on pages 6 to 8 changed
• Section 10 “Appendix: Current Calculations for a Remote Control” on pages 20 to 21 added
• Ordering Information on page 22 changed

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