ATR0797 ATMEL | Alldatasheet
Document overview
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Technical content
Features
Gain Control in 20-dB Steps Very Low I/Q Amplitude and Phase Errors High Input P1dB Small and Optimized Package for High Reliability and Performance
Applications
Infrastructure Digital Communication Systems GSM/Cellular Transceivers ISM Band Transceivers Benefits Fully Integrated Device with Reduced External Component Count Electrostatic sensitive device. Observe precautions for handling.
Description
The ATR0797 is a multi-purpose demodulator RFIC. The silicon monolithic integrated circuit is designed with Atmel’s advanced SiGe technology. This demodulator is capa- ble of both quadrature demodulation or direct IF output. Features include switchable gain control on a frequency range from 65 MHz to 300 MHz. The device performs a very low amplitude as well as phase error and allows high input P1dB. The ATR0797 targets a variety of system applications for communications including 3G wireless. Figure 1. Block Diagram
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Figure 2. Pinning
1 BBIN Baseband I-axis negative output, self biasing
2 BBIP Baseband I-axis positive output, self biasing
3 VCC 5 V power supply
4 GC2 Gain control input, stage 2, 5 V CMOS levels
5 GC1 Gain control input, stage 1, 5 V CMOS levels
6 GND Ground
7 VCC 5 V power supply
8 IFP IF positive input, self biasing, AC-coupled
9 IFN IF negative input, self biasing, AC-coupled
10 VCC 5 V power supply
11 GND Ground
12 LON Local oscillator, negative input, self biasing, AC-coupled
13 LOP Local oscillator, positive input, self biasing, AC-coupled
14 VCC 5 V power supply
15 BBQN Baseband Q-axis negative output, self biasing
16 BBQP Baseband Q-axis positive output, self biasing
4665D–SIGE–08/04 Product Description Atmel’s ATR0797 is a variable gain I-Q demodulator designed for use in receiver IF sec- tions, that are typically existing in superheterodyne RF architectures. The ATR0797 has two gain stages that are independent of each other. These gain stages are broadband differential amplifiers eac h with a digital control pin to set the gain. Since the amplifiers have approximately the same gain, setting GC1 high and GC2 low results in approximately the same gain as setting GC1 low and GC2 high. Former setting offers better noise figures. The IF input is a differential input that has internal bias circuitry to set the common mode voltage. The use of blocking capacitors to facilitate AC coupling is highly recommended to avoid changing the common mode voltage. Either input may be driven single ended if the other input is connected to ground through an AC short such as a 1000 pF capacitor. This typically results in slightly lower input P1dB. The two matched mixers are configured with the quadrature LO generator to provide in- phase and quadrature baseband outputs. The LO and IF ports offer a differential 50 Ω impedance. The passives at these ports (parallel L-R network) and the package itse lf adds inductance that tends to degrade return loss. The ATR0797 features immunity from changes in LO power. The gain features change by less than 0.6 dB over a 6 dB range of LO power. Also note the excellent I/Q balance, which typically falls within 0.1 dB and 1 degree from 65 MHz to 300 MHz, and varies less than 0.05 dB and 0.5 degree over temperature (-40°C to +85°C). The frequency response of the IF and LO ports is dominated by the L-R network on the input. When de-embedded, the gain and P1dB response is within 0.5 dB from 65 MHz to 300 MHz. The figures in the datasheet illustrate a typical ATR0797’s performance with respect to temperature. Note that these numbers include the effect of the R-L network in the IF port. Evaluation board design and equipment constraints: Please take into account that the evaluation board uses baluns on the I/Q outputs, and these baluns limit the low frequency response of the device. For true baseband opera- tion, the baluns should be removed, and the differential signals used directly. The 27 pF capacitor on the evaluation board is appropriate for lower frequencies.
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4665D–SIGE–08/04 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referred to GND. Parameters Symbol Value Unit Supply voltage V CC 5.5 V LO input LOP , LON 10 dBm IF input IFN, IFP 10 V Operating temperature T OP -40 to +85 °C Storage temperature T stg -65 to +150 °C Note: The device may not survive all maximums applied simultaneously. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 35 K/W
Electrical Characteristics
Test conditions: VCC = 5 V , Tamb = 25°C, LO input: 0 dBm at 200 MHz IF input: at 200.1 MHz, GC1 = 0, GC2 = 0; 0 dBm IF input: at 200.1 MHz, GC1 = 1, GC2 = 0; -20 dBm IF input: at 200.1 MHz, GC1 = 1, GC2 = 1; -40 dBm No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type (1)
1 IF Input (I/Q Mixing to Baseband)
1.1 Frequency range 8-9 f 65 120 -
1.2 IF input return loss 50 Ω nominal
differential input(2) 8-9 RL 20 dB D
1.3 IF input common
mode voltage Internally generated 8, 9 V CH 2V
1.4 Gain
Gain set = high; GC1 = GC2 = 1 2-1, 16-15 G3 2 3 5 3 8 d B A
1.5 Input P1dB 1, 2,
15, 16 P1dB -29 -27 dBm C
1.6 DSB Noise figure 2-1,
1.7 Gain
Gain set = medium; GC1 = 1; GC2 = 0 or GC1 = 0; GC2 = 1 2-1, 16-15 G1 2 1 5 1 7 d B A
1.8 Input P1dB 1, 2,
15, 16 P1dB -8 -6 dBm C
1.9 DSB Noise figure 2-1,
NF 14.5 dB D Notes: 1. Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 2. The parasitic inductance of the package, the board, and L5, L6 must be matched out at the center frequency with a series capacitor to achieve 20 dB of port match. 3. The parasitic inductance of the package must be matched out to reach 20 dB port match above 100 MHz.
4665D–SIGE–08/04
1.10 Gain
Gain set = low; GC1 = GC2 = 0 2-1, 16-15 G- 7 - 4 - 2 d B A
1.11 Input P1dB 1, 2,
15, 16 P1dB 12 14 dBm C
1.12 DSB Noise figure 2-1,
2 I/Q Output
2.1 I/Q output frequency
1, 2, 15, 16 fI/Q DC 500 MHz D
2.2 I/Q output amplitude
2-1, 16-15 -0.2 +0.2 dB A
2.3 I/Q phase error 2-1,
2.4 I/Q output common
1, 2, 15, 16 2.5 V A
2.5 I/Q output differential
2-1, 16-15 Voffset -100 +100 mV A
2.6 I/Q output return loss 50 Ω nominal
differential output(3) 1, 2, 15, 16 RLI/Q 20 dB D
3 LO input
3.1 LO input level 13-12 P LO -3 0 +3 dBm D
3.2 Return loss 13-12 RL LO 20 dB D
3.3 LO frequency range 13-12 RL LO 65 300 MHz D
4 Miscellaneous
4.1 Supply voltage 3, 7,
10, 14 VCC 4.75 5 5.25 V A
4.2 Supply current 3, 7,
10, 14 ICC 195 mA A
4.3 GC1, GC2 logic level
low 4, 5 V IL 0 0.3 × VCC VD
4.4 GC1, GC2 logic level
high 4, 5 V IH 0.7 × VCC VCC VD
4.5 GC1, GC2 input
impedance 4, 5 Z 40 k Ω D Electrical Characteristics (Continued) Test conditions: VCC = 5 V , Tamb = 25°C, LO input: 0 dBm at 200 MHz IF input: at 200.1 MHz, GC1 = 0, GC2 = 0; 0 dBm IF input: at 200.1 MHz, GC1 = 1, GC2 = 0; -20 dBm IF input: at 200.1 MHz, GC1 = 1, GC2 = 1; -40 dBm No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type (1) Notes: 1. Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 2. The parasitic inductance of the package, the board, and L5, L6 must be matched out at the center frequency with a series capacitor to achieve 20 dB of port match. 3. The parasitic inductance of the package must be matched out to reach 20 dB port match above 100 MHz.
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Figure 3. Gain versus Temperature Figure 4. Noise Figure versus Temperature Figure 5. Amplitude Difference versus LO Frequency
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Figure 9. Demo Test Board Schematic Table 1. Bill of Materials
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4665D–SIGE–08/04
Package Information
Ordering Information
Extended Type Number Package Remarks ATR0797-6CPH PSSO16 Lead free
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