ATR0603

ATR0603 ATMEL | Alldatasheet

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Technical content

Features

• Very Low Power Design  Single IF Architecture  Excellent Noise Performance  1-bit ADC on Chip  Small QFN Package (4 mm × 4 mm, 24 Pins)  Highly Integrated, Few External Components  Advanced BiCMOS Technology (UHF6s)  Supply Switch for External Circuitry (e.g., TCXO)  Non-ESD-sensitive Device 1. Description The ATR0603 is a single-IF GPS front-end IC, designed to meet the requirements of mobile and automotive applications. Excellent RF performance combined with high bandwidth and a low noise figure enables high-quality GPS solutions, and its very low power consumption is a perfect match for portable devices. Featuring a fully inte- grated balanced frequency synthesizer, only a few external components are required. The gain of the IF amplifier can be set to three different levels in order to meet the requirements for various applications. Several types of external oscillators can be con- nected to the robust TCXO interface. The startup logic allows significant power saving due to very low power-down current and the ability to disable the external TCXO or even other external components. CMOS output drivers deliver a 1-bit data signal and a 16.367667-MHz clock signal to the baseband interface. Figure 1-1. Block Diagram XREF XIN XSUP AMP2AMP1BP D A NBP BPI NBPI VDIG SIG SC NRF RF VCO PLL Startup logic GND ATR0603 PU VCC GPS Front-end IC ATR0603 Preliminary 4950B–GPS–11/06

4950B–GPS–11/06 ATR0603 [Preliminary] 2. Pin Configuration Figure 2-1. Pinning QFN24 (4 mm × 4m m ) AMP1 NBPI BPI NBP BP VCC GND GND XREF XIN GND XSUP VDIG SC SIG PU VCC AMP2 VCC MO GND NRF RF TEST 871 2 11109 2324 19 2021 Paddle GND Table 2-1. Pin Description Pin Symbol Type (1) Function Paddle GND S Common ground 1G N DS G r o u n d 2G N DS G r o u n d

3 XREF A_I TCXO interface ground

4 XIN A_I TCXO interface signal

6 XSUP XS External circuitry supply switch

7 VCC S Analog supply

8 MO A_O Test buffer output (f

IF) 9G N DS G r o u n d

10 NRF A_I Complementary RF input

11 RF A_I RF input

12 TEST D_I Enable test buffer

13 VCC S Analog supply

14 BP A_O IF filter interface (mixer output, open collector)

15 NBP A_O IF filter interface (complem entary mixer output, open collector)

16 BPI A_I IF filter interface (IF input)

17 NBPI A_I IF filter interface (complementary IF input)

18 AMP1 D_I IF gain control bit #1

19 AMP2 D_I IF gain control bit #2

20 VCC S Analog supply

21 PU D_I Power-up signal input

22 SIG D_O Data output

23 SC D_O Sample clock

24 VDIG S Digital supply

Notes: 1. Type: A_I = Analog input, A_O = Analog output, D_I = Digital input, D_O = Digital output, S = Supply, XS = External supply

4950B–GPS–11/06 ATR0603 [Preliminary] 3. Functional Description

3.1 General Description

The ATR0603 GPS receiver IC has been especi ally designed for GPS applications in both mobile phone and automotive applications. From this system poi nt of view, it incorporates high- est isolation between GPS and cellular bands, as well as very low power consumption. The L1 input signal (f RF) is a direct sequence spread spectr um (DSSS) signal with a center fre- quency of: fRF = 1575.42 MHz. The digital modulation scheme is bi-phase shift keying (BPSK) with a chip rate of 1.023 Mbps. As the input signal power at the antenna is approximately –140 dBm, the desired signal is below the thermal noise floor.

3.2 Startup Logic

The startup logic ensures reliable operation wi thin the recommended operating conditions. The external power control signal PU is passed through a Schmitt trigger input to eliminate voltage ripple and prevent undesired behavior during startup and shutdown. This block includes a switch to supply external circuits, for example, the TCXO. This switch is controlled by the power control signal PU.

3.3 TCXO Interface

This receiver is designed for use with an external TCXO. The TCXO output signal is fed to a bal- anced input buffer. The recommended reference frequency is: fTCXO = 16.367667 MHz. Connecting the supply pin of the TCXO to the XSUP pin of ATR0603 allows for a power down of the TCXO when the ATR0603 is shut off (see Section 3.2).

3.4 VCO/PLL

The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no external components are required. The VCO combines very good phase noise behavior and excellent spurious suppression. The relation between the reference frequency (f TCXO) and the VCO center frequency (fVCO) is given by: fVCO =f TCXO × 90 = 16.367667 MHz × 90 = 1473.09003 MHz.

3.5 RF Mixer/Image Filter

Combined with the antenna, an external LNA provides a first bandpass filtering of the signal. For the LNA, Atmel®’s ATR0610 is recommended, due to its low noise figure, high linearity and low power consumption. The output of the LNA drives a SAW filter, which provides image rejection for the mixer and the required isolation of all GSM bands. The output of the SAW filter is fed into a highly linear mixer with high conversion gain and excellent noise performance. The IF frequency (fIF) is given by: fIF =f RF –f VCO = 1575.42 MHz – 1473.09003 MHz = 102.32997 MHz.

4950B–GPS–11/06 ATR0603 [Preliminary]

3.6 IF Filter

The mixer directly drives an external LC bandpass filter via open collector outputs. In order to provide highest selectivity and conversion gain, it is recommended to design the external filter, according to the application proposal in chapter 10, as a 2-pole filter with a quality factor Q > 25.

3.7 IF Amplifier

The output of the IF filter drives an IF amplifier which is combined with additional low-pass filter- ing. The gain of this amplifier can be set to three different levels in order to optimally charge the input of the following analog-to-digital converter for each application. The gain is internally set to high gain mode but can be adjusted by using external pull-down resistors at pin 18 (AMP1) and pin 19 (AMP2). If high gain mode is desired, pins 18 and 19 have to be left floating (see Section 8. ”Electrical Characteristics” ).

3.8 A/D Converter

The analog-to-digital converter stage has a total resolution of 1 bit. It comprises a sub-sampling unit, clocked by the reference frequency (f TCXO). The frequency spectrum of the digital output signal (fOUT), present at the data output SIG, is then given by: f OUT = ⏐ fIF –f TCXO × n⏐ . The selected sub-sampling factor (n = 6) leads to the designated digital output signal, with a center frequency given by: f OUT = ⏐ fIF – f TCXO × 6⏐ = ⏐ 102.32997 MHz – 16.367667 MHz × 6⏐ = 4.123968 MHz.

3.9 Clock and Data Driver

CMOS output drivers provide the output bit as well as the system clock to the baseband IC. The amplitude of this signal strongly depends on the value for the digital supply voltage (see Section 8. ”Electrical Characteristics” on page 7).

4950B–GPS–11/06 ATR0603 [Preliminary] 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Analog supply voltage V CC –0.3 to +3.7 V Digital supply voltage V DIG –0.3 to +3.7 V Input voltage V in –0.3 to +3.7 V Max. supply voltage difference: ∆(VDIG – VCC) V ∆DIG 0.5 V Max. supply voltage difference: ∆(VPU – VCC) V ∆PU 0.5 V Operating temperature T op –40 to +85 °C Storage temperature T stg –55 to +125 °C 5. Thermal Resistance Parameters Symbol Value Unit Thermal Resistance R th 45 K/W 6. Operating Range Parameters Symbol Value Unit Analog supply voltage V CC 2.6 to 3.6 V Digital supply voltage V DIG 1.6 to 3.6 V Temperature range Temp –40 to +85 °C Input frequency f RF 1575.42 MHz Reference frequency f TCXO 16.3 to 16.4 MHz 7. ESD Characteristics Parameters Symbol Used Norm Value Unit ESD level HBM (Human Body Model) V HBM ESD-STM5.1-2001 JESD22-A114D 2006 AEC-Q100-002-Ref-D 4000 V ESD level MM (Machine Model) V MM EIA/JESD22 A115 A 300 V ESD level CDM (Charged Device Model) V CDM ESD-STM.5.3.1-1999 1000 V

4950B–GPS–11/06 ATR0603 [Preliminary] 8. Electrical Characteristics Temperature = +25°C Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified. No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type*

1 Common

1.1 Analog supply current

VCC = 3.6V, VDIG = 1.6V, V PU =1 . 6 V 7, 13, 20 IS 10.5 mA A

1.2 Analog supply current

VCC = 2.6V, VDIG = 1.6V, VPU =1 . 6 V 7, 13,

20 IS 9m A A

1.3 Mixer core current

VCC = 3.6V, VDIG = 1.6V, VPU =1 . 6 V 14, 15, 16, 17 IBP 1.5 mA A

1.4 Mixer core current

VCC = 2.6V, VDIG = 1.6V, V PU =1 . 6 V 14, 15, 16, 17 IBP 1.4 mA A

1.5 Digital supply current (1)

VCC = 3.6V, VDIG = 3.3V, VPU =1 . 6 V 24 I DIG 1.4 mA A

1.6 Digital supply current (1)

VCC = 2.6V, VDIG = 1.6V, VPU =1 . 6 V 24 I DIG 1.0 mA A

1.7 Supply current in

power-down mode VPU =V PU,off 7, 13, 14, 15, 16, 17, 20, 24 IPD 5µ A A

1.8 Noise figure (SSB) NF tot 8d B C

2.1 Output frequency f TCXO = 16.367667 MHz 14, 15 f IF 102.32997 MHz A

2.2 Input impedance

(balanced) fRF = 1575.42 MHz 10, 11 Z 11 10 – j80 Ω C

2.3 Conversion gain Recommended IF filter 8 G MIX 20 dB B

2.4 Noise figure (SSB) 8 NF MIX 6.8 dB C 3I F A m p l i f i e r

3.1 IF gain0 AMP1 = AMP2 = low 18, 19 G IF0 28 dB D

3.2 IF gain1 AMP1 = X(2),

AMP2 = low 18, 19 G IF1 42 dB D

3.3 IF gain2 AMP1 = low, AMP2 = X 18, 19 G IF2 42 dB D

3.4 IF gain3 AMP1 = AMP2 = X 18, 19 G IF3 56 dB D

*) Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Capacitive load (C L = 10 pF) at pins 22, 23 2. X represents a pin left floating (internal pull up)

4950B–GPS–11/06 ATR0603 [Preliminary] 9. Output Interface Figure 9-1. Data Output SIG Is Valid with Rising Edge of Sample Clock SC

4 Clock and Data Driver

4.1 Clock driver frequency f TCXO = 16.367667 MHz 23 f CLK 16.367667 MHz A 4.2 Clock input level f TCXO = 16.367667 MHz 3, 4 V TCXO 0.1 0.5 V pp D 4.3 Clock output level, high C load,max =1 0p F 2 3 V CLK,high 0.9 × VDIG VB 4.4 Clock output level, low C load.max =1 0p F 2 3 V CLK,low 0.1 × VDIG VB 4.5 Data output level, high C load,max =1 0p F 2 2 V Data,high 0.9 × VDIG VB 4.6 Data output level, low C load,max =1 0p F 2 2 V Data,low 0.1 × VDIG VB

5 Startup Logic

5.1 Voltage level power-on 21 V PU,on 1.4 V A 5.2 Voltage level power-off 21 V PU,off 0.8 V A

5.3 Voltage level at XSUP Ixsup =2m A ,

VPU =V PU,on 6V XSUP (VCC – 0.1) V A 8. Electrical Characteristics (Continued) Temperature = +25°C Minimum/maximum limits are at +25°C ambient temperature, unless otherwise specified. No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Capacitive load (C L = 10 pF) at pins 22, 23 2. X represents a pin left floating (internal pull up) SIG SC T = 1/16.367667 MHz

4950B–GPS–11/06 ATR0603 [Preliminary] 10. Application Circuit Figure 10-1. Application Example Note: See also the recommended IF filter layout, shown in Figure 10-2 on page 9. XREF XIN

6 XSUP

D A NBP BPI NBPI TEST VDIG 24 SIG Data out VDIG VCC SC 23 MO 812 220 nH 68Ω 220 nH 220 nH 220 nH TCXO NRF VCC PU RF LNA section (opt.) 10 nF 47 pF 1.3 pF 1.5 pF SAW B4060ATR0610 VCO PLL Startup logic 1.3 pF 4.3 pF 10 nF 5.6 nH 100 nF 4.7 nH GND ATR0603 PU 4.3 pF Sample clock VCC 20 VCC 13 VCC 7 100 nF 100 nF

4950B–GPS–11/06 ATR0603 [Preliminary] Figure 10-2. Recommended IF Filter: Layout versus Schematic Note: Mutual inductance between the four inductors Lc to Lf plays an important role in the IF filter char- acteristics. In any design, the layout arrangement shown in Figure 10-2 should be followed as closely as possible. Measurements: A = 2.8 mm; B = 1.4 mm Lc to Lf: Wire-wound SMD inductors, size 0603 (see Table 11-1 on page 11) Table 10-1. Specifications of Recommended TCXO (Rakon; IT5325BE 16.367667 MHz) Parameter Comment Min. Nominal Max. Unit Nominal frequency Nominal frequency referenced to 25°C 16.367667 MHz Frequency deviation Within operating temperature range ±2.5 ppm Temperature range Operating temperature range –40 85 °C Output waveform DC-coupled clipped sine wave Output voltage (peak to peak) At minimum supply voltage 0.8 V Current At maximum supply voltage 1.5 mA Output load capacitance Tolerable load capacitance 9 11 pF 171615 Ca Cb 1514 17 16 Lc Ld Le Lf BP NBP BPI NBPI Ca Cb VCCA B Lc Ld Le Lf

4950B–GPS–11/06 ATR0603 [Preliminary] 11. Demonstration Board Figure 11-1. Schematic of Demonstration Board (Without LNA Section) C35 C31 C23 C34 XREF XIN D A NBP BPI NBPI AMP1 18 SIG 22 SC 23 L1L2

12 TEST

1473.09003 MHz

4950B–GPS–11/06 ATR0603 [Preliminary] Figure 11-2. Photo of Evaluation Board (Including LNA Section) Table 11-1. Bill of Materials for the Demonstration Board (Without LNA Section) Qty Value Parts Tolerance Voltage Material Manufacturer Manufacturer Order Code

2 J2, J3 Molex ® 90120-0762

3 J1, J4, J5 Molex 90120-0763

10 R 2 V i s h a y

® CRCW0402000Z 2 1p3 C12, C18 0.1 pF 16V C0G Taiyo Yuden ® EVK105CH1R3BW 2 4p3 ±0p1 C3, C4 0.1 pF C0G Murata ® GRM1555C1H4R3GZ01B 1 5n6 2% Multilayer L7 2% Würth ® Elektronik 744784056G 2 10µ C5, C34 20% 16V Vishay 293D106X0016B2 1 10n C1 5% 16V X7R Vishay VJ0402Y103JXJ 1 68 R1 5% Vishay CRCW0402680J 4 100n C2, C7, C23, C31 20% 16V Y5V Vishay VJ0402V104MXJ 1 100p C35 5% 25V C0G Vishay VJ0402A101JXXA. 1 142-0711-821 P1 Johnson Components ™ 142-0711-821 4 220n 2% L1, L2, L3, L4 2% Coilcraft® alternatively Würth Elektronik 0603CS-R22XGB 744761222G

1 ATR0603-PFQW IC1 Atmel ATR0603

1 B4060 FI1 Epcos

® B39162-B4060-U810

1 IT5325BE

16.367667 MHz XO2 2.0 ppm Rakon IT5325BE Ref. no. 34365

1 R125426 P2 Radiall ® 125426

4950B–GPS–11/06 ATR0603 [Preliminary] 12. Recommended Footprint (QFN24 - 4 mm × 4m m ) Figure 12-1. Recommended Footprint 2.6 × 2.6 metal pad 0.4 × 0.4 (16 ×) solder stop opening solder stop overlap 0.05 ∅ 0.25 (9 ×) 0.30 0.50 All dimensions in mm Scale 10 : 1

4950B–GPS–11/06 ATR0603 [Preliminary] 14. Package Information 13. Ordering Information Extended Type Number Package Remarks ATR0603-PFQW QFN24 - 4 mm × 4 mm Taped and reeled 0.23±0.07 0.4±0.1 0.9±0.1 0.2 Z 10:1 Z 2.6±0.15 2.5 0.5 nom. 12 7 19 24 Bottom Top Pin1 identification specifications according to DIN technical drawings Issue: 1; 28.11.05 Drawing-No.: 6.543-5123.01-4 Not indicated tolerances ±0.05 Dimensions in mm Package: QFN_ 4 x 4_24L Exposed pad 2.6 x 2.6

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