ATMLH412 ATMEL | Alldatasheet
Document overview
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- PDF pages: 12
Technical content
Features
- Low-voltage and Standard-voltage Operation ⎯ 1.8 (V CC = 1.8V to 5.5V)
- Internally Organized as 32,768 x 8
- Two-wire Serial Interface
- Schmitt Trigger, Filtered Inputs for Noise Suppression Two-wire Serial EEPROM 256K (32,768 x 8) ATMLH412 8568A–SEEPR–11/08
- Bidirectional Data Transfer Protocol
- 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility
- Write Protect Pin for Hardware and Software Data Protection
- 64-byte Page Write Mode (Partial Page Writes Allowed)
- Self-timed Write Cycle (5 ms Max)
- High Reliability ⎯ Endurance: One Million Write Cycles ⎯ Data Retention: 40 Years
- Lead-free/Halogen-free Devices Available
- 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead Ultra Thin Small Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages
- Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Description
of serial electrically erasable and programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-volta ge operation are ess ential. The devices are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin SAP, 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is available in a 1.8V (1.8V to 5.5V) version. Table 1. Pin Configurations
Figure 1. Block Diagram
) for compatibility with other ATMLHxx devices. W 8568A–SEEPR–11/08 1. Pin Descriptions SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data trans fer. This pin is open drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to V CC hen the pins are hardwired, as many as eight 256K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “ Device Addressing ”) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to V CC , all write operations to the memory are inhibite d. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacit ive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.
addressing requires a 15-bit data word address. Table 2. Pin Capacitance Note: 1. This parameter is characterized and is not 100% tested. Table 3. DC Characteristics max are reference only and are not tested.
Table 4. AC Characteristics (Industrial Temperature) Test conditions are listed in Note 2. Note: 1. This parameter is ensured by characterization and is not 100% tested.
- AC measurement conditions:
Figure 7. Output Acknowledge
most significant bits as shown. This is common to all two-wire EEPROM devices. Figure 8. Device Addressing circuit that biases them to a logic low condition if the pins are allowed to float. and a write operation is initiated if this bit is low.
following stop condition (refer to Figure 13). Figure 13. Sequential Read