ATL25 ATMEL | Alldatasheet
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Table 1. ATL25 Array Organization
- Routing site = 4 transistors
- Nominal 2-input NAND gate FO = 2 at 2.5V
Table 2. Design Systems Supported memory blocks and/or cores so an underlayer layout model can be created.
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Table 3. Design Flow
A T L 2 5S e r i e sA S I C 1414C–ASIC-08/02 Pin Definition Requirements The corner pads are reserved for power and ground only. All other pads are fully programma- ble as input, output, bidirectional, power, or ground. When implementing a design with 3.3V compliant buffers, an appropriate number of pad sites must be reserved for the V DD 3p i n s , which are used to distribute 3.3V power to the compliant buffers. Design Options Logic Synthesis Atmel can accept RTL designs in Verilog or VHDL HDL formats. Atmel fully supports Synop- sys for Verilog or VHDL simulation as well as synthesis. Of the two HDL formats, Verilog and VHDL, Atmel’s preferred HDL format for ASIC design is Verilog. ASIC Design Translation Atmel has successfully translated existing designs from most major ASIC vendors into Atmel ASICs. These designs have been optimized for speed and gate count and modified to add logic or memory, or replicated as a pin-for-pin compatible, drop-in replacement. FPGA and PLD Conversions Atmel has successfully translated existing FPGA/PLD designs from most major vendors into Atmel ASICs. There are four primary reasons to convert from an FPGA/PLD to an ASIC: Conversion of high-volume devices for a single or combined design is cost effective. Performance can often be optimized for speed or low power consumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing on-board space requirements. In situations where an FPGA/PLD was used for fast cycle time prototyping, an ASIC may provide a lower cost answer for long-term volume production.
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ing a prior instruction execution, enabling the execution of one instruction per clock cycle. timer/counter, programmable watchdog timer and SPI. Figure 3. AVR 8-bit RISC Microcontroller Core
pose 32-bit microprocessors, which offer high performance with very low power consumption. decoded, and a third instruction is being fetched from memory. interrupt controller, timer counter and watchdog timer. Figure 4. ARM7TDMI 32-bit RISC Microprocessor Core
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1414C–ASIC-08/02 ARM920T™ 32-bit RISC Microprocessor Core The ARM920T extends the capabilities of the popular ARM7TDMI, while maintaining code compatibility and Thumb instruction compression. Enhancements include Harvard architecture and a memory management unit with virtual addressing support (allowing the use of advanced platform operating systems such as Windows CE ™ , Linux ®, Symbian OS ™ and VxWorks ™ ). 16 Kbyte data and instruction caches are included. ARM946E-S™ 32-bit RISC Microprocessor Core The ARM946E-S is a synthesizable version of the ARM9E-S core, with similar features to the ARM920T. The ARM9E-S instruction set adds saturation logic to enhance DSP implementa- tion, as well as double-word data moves. Additional DSP features include a single cycle 16 x 32 Multiply Accumulate (MAC) Unit. A memory protection unit is provided, but without full virtual memory support. As a result, the ARM946E-S is more suited to deeply embedded tasks that do not require extended-platform OS support. Cache sizes can be tailored to the applica- tion, resulting in a (potentially) smaller die size compared to the ARM920T. OakDSPCore® Digital Signal Processing Core Atmel’s hard macro OakDSPCore is a 16-bit, general purpose, low-power, low-voltage and high-speed Digital Signal Processor (DSP). Oak is designed for mid-to-high-end telecommunications and consumer electronics applica- tions, where low-power and portability are major requirements. Among the applications supported are digital cellular telephones, fast modems, advanced facsimile machines and hard disk drives. Oak is available as a DSP core in Atmel ’s ASIC cell library, to be utilized as an engine for a DSP-based ASIC. It is specified with several levels of modularity in SRAM, ROM and I/O blocks, allowing efficient DSP-based ASIC development. Oak is aimed at achieving the best cost-performance factor for a given (small) silicon area. As a key element of a system-on-chip, it takes into account such requirements as program size, data memory size, glue logic and power management. The Oak core consists of three main execution units operating in parallel: the Computation/Bit- Manipulation Unit (CBU), the Data Addressing Arithmetic Unit (DAAU) and the Program Con- trol Unit (PCU). The core also contains ROM and SRAM addressing units, and Program Control Logic (PCL). All other peripheral blocks that are application specific are defined as part of the user-specific logic and implemented around the DSP core on the same silicon die. Oak has an enhanced set of DSP and general microprocessor functions to meet most applica- tion requirements. The Oak programming model and instruction set are aimed at the straightforward generation of efficient and compact code. MIPS64™ 5Kf™ 64-bit RISC Microprocessor Core The MIPS64 5Kf is a synthesizable MIPS64 5K family core that provides 64-bit address and data paths along with an onboard IEEE 754-compliant Floating Point Unit. A built-in memory management unit with virtual addressing support allows the use of platform operating systems such as Windows CE and others. Also provided are configurable instruction and data caches, as well as a multiply divide unit capable of single cycle 32 x 16 Multiply Accumulate (MAC) operations. Teak and PalmDSPCore® Digital Signal Processing Cores The Teak and Palm are synthesizable dual-MAC DSP cores from DSP Group, Inc. The Teak is a fixed-point 16-bit DSP, whereas the Palm can be configured for 16-bit, 20-bit or 24-bit fixed-point math. Both cores are optimized for high MIPs per mW, with performance targeted to handling filtering, voice compression/decompression and modem functions for portable and wireless applications such as 3G digital cellular. Hardware support is also provided for imple- menting Viterbi forward error correction.
A T L 2 5S e r i e sA S I C 1414C–ASIC-08/02 The Teak and Palm cores both have a comprehensive suite of development tools that are easy to learn and are intended to support rapid code development. A C compiler that supports in-line assembly language and provides language extensions to enhance C code optimization is provided. An assembler and linker are also provided. Both emulation (using test silicon) and source-level simulation of C and assembly language enhance software verification.
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mance of the finished product. Table 4. 2.5-volt DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted.
Table 5. 3.3-volt DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted.
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employed to provide both the user and Atmel with the ability to test the finished product. defined for digital testers, should be employed to create a suite of manufacturing tests. be isolated for test without impinging upon the normal functionality. The glue logic can be designed using full SCAN techniques to enhance its testability. design in its anticipated operating modes. Table 6. I/O Buffer DC Characteristics
and ceramic quad flatpacks, thin quad flatpacks, ceramic pin grid arrays and ball grid arrays. Note: 1. Require customer design substrate. Table 7. Packaging Options –Partial List
Printed on recycled paper. © Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard warranty w h i c hi sd e t a i l e di nA t m e l’s Terms and Conditions located on the Company ’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel ’s products are not authorized for use as critical components in life support devices or systems. Atmel Headquarters Atmel Operations Corporate Headquarters
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literature@atmel.com Web Site http://www.atmel.com 1414C–ASIC–ASIC-08/02 Atmel ® and AVR ® a r er e g i s t e r e dt r a d e m a r k so fA t m e l . ARM7TDMI ™ , ARM920T ™ and ARM946E-S ™ are trademarks of ARM Limited; MIPS64 ™ 5Kf™ are trademarks of MIPS T echnologies, Inc.; T eak ™ and PalmDSPCore ™ are trademarks of DSP Group; Cadence ® is a registered trademark and Opus ™ , NC Verilog ™ ,P e a r l™ , Verilog-XL ™ and BuildGates ™ are trademarks of Cadence Design Systems, Inc.; Mentor Graphics ® and ModelSim ® are registered trademarks and Leonardo Spectrum ™ is a trademark of Mentor Graphics; Design Compiler ™ , PrimeTime ™ ,V C S™ and Floorplan Manager ™ are trade- marks and Synopsys ® and TetraMax ® are registered trademarks of Synopsys; Novas Software ® and Debussy ® are registered trademarks of Novas Software, Inc.; Silicon Perspective ™ i sat r a d e m a r ka n dF i r s tE n c o u n t e r® is a registered trademark of Silicon Perspective; Windows CE ™ is a trademark of Microsoft Corp.; Linux ™ is a trademark of Linus T orvalds; Symbian OS ™ is a trademark of Symbian Limited; VxWorks ™ is a trademark of Wind River Systems, Inc. Other terms and product names may be the trademarks of others.