ATFS05

ATFS05 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Designed to Store Configurator Programs for Field Programmable System Level Integrated Circuits (FPSLICs)  In-System Programmable (ISP) via 2-wire Bus  Spare Memory Available for System Parameters Storage  Low-power CMOS EEPROM Process  Available in 6 mm x 6 mm x 1 mm 8-lead LAP Package (Pin Compatible Across Product Family)  Emulation of Atmel’s AT24CXXX Serial EEPROMs  Available in 3.3V ± 10% L V  Low-power Standby Mode  High-reliability – Endurance: 100,000 Write Cycles – Data Retention: 90 Years for Industrial Parts (at 85 °C) and 190 Years for Commercial Parts (at 70°C)

Description

The FPSLIC Support Devices provide an easy-to-use, cost-effective configuration memory for programming Field Programmable System Level Integrated Circuits by using a simple serial-access procedure to configure one or more FPSLIC devices. See Table 1 for a list of supported FPSLIC devices. The FPSLIC Support Device can be programmed with industry-standard program- mers, Atmel’s ATDH2200E Programming Kit or Atmel’s A TDH2225 ISP Cable. Pin Configurations 8-lead LAP Table 1. ATFS FPSLIC Support Devices

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3017C–FPSLI–07/02 Block Diagram Device Description The control signals for the FPSLIC Support Device (CE , RESET/OE and CCLK) inter- face directly with the FPSLIC control signals. All FPSLIC devices can control the entire configuration process and retrieve data from the FPSLIC Support Device without requir- ing an external intelligent controller. The RESET /OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET /OE is driven Low, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also con- trols the output of the FPSLIC Support Device. If CE is held High after the RESET /OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET /OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE . When the FPSLIC Support Device has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other FPSLIC Support Devices. Upon power-up, the address counter is automatically reset. EEPROM CELL MATRIX ROW DECODER COLUMN DECODER TC CECLK RESET/OE CEO(A2) DATA BIT COUNTER PROGRAMMING DATA SHIFT REGISTER PROGRAMMING MODE LOGIC ROW ADDRESS COUNTER POWER ON RESET SER_EN

3017C–FPSLI–07/02 Pin Description 8L A P Pin Name I/O Description 1 DA TA I/O T ri-state DA TA output for configuration. Open-collector bi-directional pin for programming. 2C L K I Clock input. Used to increment the internal address and bit counter for reading and programming. 3 RESET /OE I Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. 4C E I Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode ( SER_EN Low). 5 GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended. 6 A2 I Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. 7 SER_EN I Serial enable must be held High during FPSLIC loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. 8V CC +3.3V power supply pin

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3017C–FPSLI–07/02 FPSLIC Master Serial Mode Summary The I/O and logic functions of the FPSLIC devices are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the mode pins. In Master Mode, the FPSLIC automatically loads the configuration program from an external memory. The FPSLIC Support Device has been designed for compatibility with the Master Mode. Control of Configuration Most connections between the FPSLIC device and the FPSLIC Support Device are sim- ple and self-explanatory:  The DATA output of the FPSLIC Support Device drives DIN of the FPSLIC devices.  The master FPSLIC CCLK output drives the CLK input of the FPSLIC Support Device.  SER_EN must be connected to V CC (except during ISP). Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at V CC supply only. Programming super voltages are generated inside the chip. Standby Mode The FPSLIC Support Device enters a low-power standby mode whenever CE is asserted High. In this mode, the ATFS05 consumes less than 50 µA of current at 3.3V. The output remains in a high-impedance state regardless of the state of the OE input.

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3017C–FPSLI–07/02 Absolute Maximum Ratings* Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. Exposure to Abso- lute Maximum Rating conditions for extended periods of time may affect device reliability. Voltage on Any Pin CC +0.5V Operating Conditions Symbol Description ATFS05/10/40 UnitsMin Max VCC Commercial Supply voltage relative to GND -0°Ct o+ 7 0°C 3.0 3.6 V Industrial Supply voltage relative to GND -40°Ct o+ 8 5°C 3.0 3.6 V

3017C–FPSLI–07/02 DC Characteristics – ATFS05 VCC =3 . 3 V±1 0 % Symbol Description Min Max Units VIH High-level Input Voltage 2.0 V CC V VIL Low-level Input Voltage 0 0.8 V VOH High-level Output Voltage (IOH =- 2 . 5m A ) Commercial 2.4 V VOL Low-level Output Voltage (IOL =+ 3m A ) 0 . 4 V VOH High-level Output Voltage (IOH =- 2m A ) Industrial 2.4 V VOL Low-level Output Voltage (IOL =+ 3m A ) 0 . 4 V ICCA Supply Current, Active Mode 5 mA IL Input or Output Leakage Current (V IN =V CC or GND) -10 10 µA ICCS Supply Current, Standby Mode Commercial 50 µA Industrial 100 µA DC Characteristics – ATFS10/40 VCC =3 . 3 V± 10% Symbol Description Min Max Units VIH High-level Input Voltage 2.0 V CC V VIL Low-level Input Voltage 0.0 0.8 V VOH High-level Output Voltage (IOH =- 2 . 5m A ) Commercial 2.4 V VOL Low-level Output Voltage (IOL =+ 3m A ) 0 . 4 V VOH High-level Output Voltage (IOH =- 2m A ) Industrial 2.4 V VOL Low-level Output Voltage (IOL =+ 3m A ) 0 . 4 V ICCA Supply Current, Active Mode 5 mA IL Input or Output Leakage Current (V IN =V CC or GND) -10 10 µA ICCS Supply Current, Standby Mode Commercial 100 µA Industrial 100 µA

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3017C–FPSLI–07/02 AC Characteristics AC Characteristics When Cascading CE RESET/OE CLK DATA TSCE TLC THC TCACTOE TCE TOH THOE TSCE THCE TDF TOH TCDF TOCK LAST BIT TOCE TOCE TOOE FIRST BIT RESET/OE CE CLK DATA CEO

3017C–FPSLI–07/02 Notes: 1. AC test lead = 50 pF . 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. Note: 1. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. AC Characteristics for ATFS05 VCC =3 . 3 V±1 0 % Symbol Description Commercial Industrial UnitsMin Max Min Max TOE (1) OE to Data Delay 50 55 ns TCE (1) CE to Data Delay 60 60 ns TCAC (1) CLK to Data Delay 75 80 ns TOH Data Hold from CE,O E,o rC L K 0 0 n s TDF (2) CE or OE to Data Float Delay 55 55 ns TLC CLK Low Time 25 25 ns THC CLK High Time 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 35 60 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns THOE OE High Time (guarantees counter is reset) 25 25 ns FMAX Maximum Input Clock Frequency 10 10 MHz AC Characteristics for ATFS05 when Cascading VCC =3 . 3 V±1 0 % Symbol Description Commercial Industrial UnitsMin Max Min Max TCDF (1) CLK to Data Float Delay 60 60 ns FMAX Maximum Input Clock Frequency 8 8 MHz

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3017C–FPSLI–07/02 Notes: 1. AC test load = 50 pF . 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. Note: 1. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. AC Characteristics for ATFS10/40 VCC =3 . 3 V±1 0 % Symbol Description Commercial Industrial UnitsMin Max Min Max TOE (1) OE to Data Delay 50 55 ns TCE (1) CE to Data Delay 55 60 ns TCAC (1) CLK to Data Delay 55 60 ns TOH Data Hold From CE,O E,o rC L K 0 0 n s TDF (2) CE or OE to Data Float Delay 50 50 ns TLC CLK Low Time 25 25 ns THC CLK High Time 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 30 35 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns THOE OE High Time (guarantees counter is reset) 25 25 ns FMAX MAX Input Clock Frequency 15 10 MHz AC Characteristics for ATFS10/40 when Cascading VCC =3 . 3 V± 10% Symbol Description Commercial Industrial UnitsMin Max Min Max TCDF (1) CLK to Data Float Delay 50 50 ns FMAX MAX Input Clock Frequency 12.5 10 MHz

3017C–FPSLI–07/02 Thermal Resistance Coefficients(1) Note: 1. For more information refer to the “Thermal Characteristics of Atmel ’s Packages”application note, available on the Atmel web site. Device Package Type θJC [°C/W] θJA [°C/W] Airflow = 0 ft/min A TFS05 Leadless Array Package (LAP) 8CN4 45 115.71 A TFS10/40 Leadless Array Package (LAP) 8CN4 45 135.71

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3017C–FPSLI–07/02

Ordering Information

Ordering Code Package Operation Range A TFS05-CC A TFS10-CC A TFS40-CC 8CN4 8CN4 8CN4 Commercial (0°Ct o7 0°C) A TFS05-CI A TFS10-CI A TFS40-CI 8CN4 8CN4 8CN4 Industrial (-40°Ct o8 5°C) Package Type 8CN4 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP)

3017C–FPSLI–07/02 Packaging Information 8CN4 – LAP

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San Jose, CA 95131 TITLE DRAWING NO. R REV. 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) A8CN4 11/14/01 Pin1 Corner Marked Pin1 Indentifier 0.10 mm TYP Top View L b e Side View A Bottom View E D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.94 1.04 1.14 A1 0.30 0.34 0.38 b 0.45 0.50 0.55 1 D 5.89 5.99 6.09 E 4.89 5.99 6.09 e 1.27 BSC e1 1.10 REF L 0.95 1.00 1.05 1 L1 1.25 1.30 1.35 1 Note: 1. Metal Pad Dimensions.

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