ATF750CL-15XC

ATF750C ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Advanced, High-speed, Electrically-erasable Programmable Logic Device – Superset of 22V10 – Enhanced Logic Flexibility – Backward Compatible with ATV750B/BL and ATV750/L  Low-power Edge-sensing “L” Option with 1 mA Standby Current  D- or T-type Flip-flop  Product Term or Direct Input Pin Clocking  7.5 ns Maximum Pin-to-pin Delay with 5V Operation  Highest Density Programmable Logic Available in 24-pin Package – Advanced Electrically-erasable Technology – Reprogrammable – 100% Tested  Increased Logic Flexibility – 42 Array Inputs, 20 Sum Terms and 20 Flip-flops  Enhanced Output Logic Flexibility – All 20 Flip-flops Feed Back Internally – 10 Flip-flops are also Available as Outputs  Programmable Pin-keeper Circuits  Dual-in-line and Surface Mount Package in Standard Pinouts  Commercial and Industrial Temperature Ranges  20-year Data Retention  2000V ESD Protection  1000 Erase/Write Cycles Block Diagram

Description

The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays PROGRAMMABLE INTERCONNECT AND COMBINATORIAL LOGIC ARRAY LOGIC OPTION (UP T0 20 FLIP-FLOPS) OUTPUT OPTION 4T O8 PRODUCT TERMS (OE PRODUCT TERMS) I/O PINS INPUT PINS (CLOCK PIN) Rev. 0776F–01/00 High-speed Complex Programmable Logic Device ATF750C ATF750CL Pin Configurations Pin Name Function CLK Clock IN Logic Inputs I/O Bi-directional Buffers * No Internal Connection VCC +5V Supply (continued) DIP/SOIC/TSSOP CLK/IN IN IN IN IN IN IN IN IN IN IN GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN PLCC IN IN IN IN IN IN I/O I/O I/O I/O I/O I/O IN IN GND IN I/O I/O IN IN CLK/IN VCC I/O I/O

ATF750C(L)2 guarantee fast in-system performance. The ATF750C(L) is a high-performance CMOS (electrically-erasable) complex programmable logic device (CPLD) that utilizes Atmel ’s proven electrically-erasable technology. Each of the ATF750C(L)’s 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bi- directional I/O pins. Each flip-flop is individually config- urable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops. There are 171 total product terms available. There are two sum terms per output, providing added flexibility. A variable format is used to assign between four to eight product terms per sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare. Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individu- ally configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flip- flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. The ATF750C(L) is a low-power device with speeds as fast as 15 ns. The ATF750C(L) provides the optimum low-power CPLD solution. This device significantly reduces total system power, thereby allowing battery- powered operations. DC and AC Operating Conditions All members of the family are specified to operate in either one of two voltage ranges. Parameters are specified as noted to be either 2.7V to 3.6V, 5V ± 5% or 5V ± 10%. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V DC, which may under- shoot to -2.0V for pulses of less than 20 ns. Max- imum output pin voltage is V CC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. Voltage on Any Pin with Voltage on Input Pins with Respect to Ground (1) Programming Voltage with (1) 5V Operation Commercial -7.5, -10, -15 Industrial -10, -15 Operating Temperature (Ambient) 0 °C - 70°C- 4 0 °C - +85°C VCC Power Supply 5V ± 5% 5V ± 10%

ATF750C(L) Logic Options Combinatorial Output Registered Output Clock Mux Output Options Combined Terms Separate Terms Combined Terms Separate Terms SELECT LOGIC TO CELLCLOCK PRODUCT TERM CLK CKi CKMUX PIN

that previous high or low level. tors and eliminate their DC power consumption. Table 1. Software Compiler Mode Selection

ATF750C(L) Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. Input Test Waveforms and Measurement Levels tR, tF < 3 ns (10% to 90%) Output Test Load DC Characteristics Symbol Parameter Condition Min Typ Max Units ILI Input Load Current V IN = -0.1V to VCC + 1V 10 µA ILO Output Leakage Current VOUT = -0.1V to VCC + 0.1V 10 µA ICC Power Supply Current, Standby VCC = Max, VIN = Max, Outputs Open C-7, -10 Com. 125 180 mA Ind., Mil. 135 190 mA C-15 Com. 125 180 mA Ind., Mil. 135 190 mA CL-15 Com. 0.12 1 mA Ind., Mil. 0.15 2 mA IOS (1) Output Short Circuit Current VOUT = 0.5V -120 mA VIL Input Low Voltage 4.5 ≤ VCC ≤ 5.5V -0.6 0.8 V VIH Input High Voltage 2.0 V CC + 0.75 V VOL Output Low Voltage VIN = VIH or VIL, VCC = Min IOL = 16 mA Com., Ind. 0.5 V IOL = 12 mA Mil. 0.5 V IOL = 24 mA Com. 0.8 V VOH Output High Voltage VIN = VIH or VIL, VCC = Min IOH = -4.0 mA 2.4 V VCC 390 (750 MIL.) 300 (390 MIL.)

ATF750C(L)6 AC Waveforms, Product Term Clock(1) Note: 1. See ordering information for valid part numbers. AC Characteristics, Product Term Clock(1) Symbol Parameter -7 -10 C/CL-15 UnitsMin Max Min Max Min Max tPD Input or Feedback to Non-registered Output 7.5 10 15 ns tEA Input to Output Enable 7.5 10 15 ns tER Input to Output Disable 7.5 10 15 ns tCO Clock to Output 3 7.5 4 10 5 12 ns tCF Clock to Feedback 1 5 4 7.5 5 9 ns tS Input Setup Time 3 4 8/12 ns tSF Feedback Setup Time 3 4 7 ns tH H o l d T i m e 125 n s tP Clock Period 7 11 14 ns tW Clock Width 3.5 5.5 7 ns FMAX External Feedback 1/(tS + tCO)9 5 7 1 5 0 / 4 1 M H z Internal Feedback 1/(tSF + tCF) 125 86 62 MHz No Feedback 1/(tP) 142 90 71 MHz tAW Asynchronous Reset Width 5 10 15 ns tAR Asynchronous Reset Recovery Time 3 10 15 ns tAP Asynchronous Reset to Registered Output Reset 8 12 15 ns tSP Setup Time, Synchronous Preset 4 7 8 ns

ATF750C(L) AC Waveforms, Input Pin Clock(1) AC Characteristics, Input Pin Clock Symbol Parameter -7 -10 C/CL-15 UnitsMin Max Min Max Min Max tPD Input or Feedback to Non-registered Output 7.5 10 15 ns tEA Input to Output Enable 7.5 10 15 ns tER Input to Output Disable 7.5 10 15 ns tCOS Clock to Output 0 6.5 0 7 0 10 ns tCFS Clock to Feedback 0 3.5 0 5 0 5.5 ns tSS Input Setup Time 4 5 8/12.5 ns tSFS Feedback Setup Time 4 5 7 ns tHS H o l d T i m e 000 n s tPS Clock Period 7 10 12 ns tWS Clock Width 3.5 5 6 ns FMAXS External Feedback 1/(tSS + tCOS)9 5 8 3 5 5 / 4 4 M H z Internal Feedback 1/(tSFS + tCFS) 133 100 80 MHz No Feedback 1/(tPS) 142 100 83 MHz tAW Asynchronous Reset Width 5 10 15 ns tARS Asynchronous Reset Recovery Time 5 10 15 ns tAP Asynchronous Reset to Registered Output Reset 8 10 15 ns tSPS Setup Time, Synchronous Preset 5 5/9 11 ns

ATF750C(L)8 Functional Logic Diagram ATF750C, Upper Half

ATF750C(L) Functional Logic Diagram ATF750C, Lower Half

ATF750C(L)10 Preload of Registered Outputs The ATF750C(L) ’s registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A V IH level on the I/O pin will force the register high; a VIL will force it low, independent of the output polar- ity. The PRELOAD state is entered by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock term is pulsed high, the data on the I/O pins is placed into the register chosen by the select pin. Power-up Reset The registers in the ATF750C(L)s are designed to reset during power-up. At a point delayed slightly from V CC cross- ing VRST, all registers will be reset to the low state. The out- put state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. How- ever, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the fol- lowing conditions are required: 1. The V CC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock terms or pin high, and 3. The clock pin, or signals from which clock terms are derived, must remain stable during t PR. Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Level Forced on Registered Output Pin during Preload Cycle Select Pin State Register #0 State after Cycle Register #1 State after Cycle VIH Low High X VIL Low Low X VIH High X High VIL High X Low Parameter Description Typ Max Units tPR Power-up Reset Time 600 1000 ns VRST Power-up Reset Voltage 3.8 4.5 V Pin Capacitance f = 1 MHz, T = 25°C(1) Typ Max Units Conditions CIN 58 p F V IN = 0V COUT 68 p F V OUT = 0V

ATF750C(L) Using the ATF750C’s Many Advanced The ATF750C(L) ’s advanced flexibility packs more usable gates into 24 pins than any other logic device. The ATF750C(L)s start with the popular 22V10 architecture, and add several enhanced features:  Selectable D- and T-type Registers Each ATF750C(L) flip-flop can be individually configured as either D- or T-type. Using the T -type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage.  Selectable Asynchronous Clocks Each of the ATF750C(L)’s flip-flops may be clocked by its own clock product term or directly from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design.  A Full Bank of Ten More Registers The ATF750C(L) provides two flip-flops per output logic cell for a total of 20. Each register has its own sum term, its own reset term and its own clock term.  Independent I/O Pin and Feedback Paths Each I/O pin on the ATF750C(L) has a dedicated input path. Each of the 20 registers has its own feedback terms into the array as well. This feature, combined with individual product terms for each I/O’s output enable, facilitates true bi-directional I/O design. Synchronous Preset and Asynchronous Reset One synchronous preset line is provided for all 20 registers in the ATF750C(L). The appropriate input signals to cause the internal clocks to go to a high state must be received during a synchronous preset. Appropriate setup and hold times must be met, as shown in the switching waveform diagram. An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and slave halves of the flip- flops are reset when the input signals received force the internal resets high. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF750C(L) fuse patterns. Once the security fuse is programmed, all fuses will appear programmed during verify. The security fuse should be programmed last, as its effect is immediate.

ATF750C(L)12 ATF750C SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25°C) 100 120 140 SUPPLY VOLTAGE (V) ICC (mA) SUPPLY CURRENT VS. FREQUENCY STANDARD POWER (TA = 25°C) 120 160 0 5 10 25 50 75 100 FREQUENCY (MHz) ICC (mA) ATF750C/CL OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V) -50 -45 -40 -35 -30 -25 -20 -15 -10 44 . 555 . 56 SUPPLY VOLTAGE (V) IOH (mA) ATF750CL SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25°C) 100 120 140 160 SUPPLY VOLTAGE (V) ICC (µA) SUPPLY CURRENT VS. FREQUENCY LOW-POWER ("L") VERSION (TA = 25°C) 100 120 140 0 5 10 25 50 75 100 FREQUENCY (MHz) ICC (mA) ATF750C/CL OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C) -90.00 -80.00 -70.00 -60.00 -50.00 -40.00 -30.00 -20.00 -10.00 0.00 V OH (V) IOH (mA)

ATF750C(L) ATF750C/CL OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V) 44 . 555 . 56 SUPPLY VOLTAGE (V) IOL (mA) ATF750C/CL OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C) VOL (V) IOL (mA) ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5V,TA = 25°C) WITHOUT PIN-KEEPER -0.2 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 INPUT VOLTAGE (V) INPUT CURRENT (uA) ATF750C/CL OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C) 100 120 140 V OL (V) IOL (mA) ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5V,TA = 25°C) -25 -20 -15 -10 INPUT VOLTAGE (V) INPUT CURRENT (uA) ATF750C/CL INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 5V,TA = 35°C) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 INPUT VOLTAGE (V) INPUT CURRENT (mA)

ATF750C(L)14 Using “C” Product for Industrial To use commercial product for industrial ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%. ATF750C(L) Ordering Information tPD (ns) tCOS (ns) Ext. fMAXS (MHz) Ordering Code Package Operation Range 7.5 6.5 95 ATF750C-7JC 28J Commercial (0°C to 70°C) 10 7 83 ATF750C-10JC ATF750C-10PC ATF750C-10SC ATF750C-10XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF750C-10JI ATF750C-10PI ATF750C-10SI 28J 24P3 24S Industrial (-40°C to 85°C) 15 10 55 ATF750C-15JC ATF750C-15PC ATF750C-15SC ATF750C-15XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF750C-15JI ATF750C-15PI ATF750C-15SI 28J 24P3 24S Industrial (-40°C to 85°C) 15 10 44 ATF750CL-15JC ATF750CL-15PC ATF750CL-15SC ATF750CL-15XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF750CL-15JI ATF750CL-15PI ATF750CL-15SI 28J 24P3 24S Industrial (-40°C to 85°C) Package Type 28J 28-lead, Plastic J-leaded Chip Carrier (PLCC) 24P3 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24S 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24X 24-lead, 0.173" Wide, Thin Shrink Small Outline (TSSOP)

ATF750C(L)15 Packaging Information .045(1.14) X 45° PIN NO. 1 IDENTIFY .032(.813) .026(.660) .050(1.27) TYP .300(7.62) REF SQ .012(.305) .008(.203) .021(.533) .013(.330) .430(10.9) .390(9.91)SQ .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .456(11.6) .450(11.4) .495(12.6) .485(12.3) SQ SQ 1.27(32.3) 1.25(31.7) PIN .266(6.76) .250(6.35) .090(2.29) MAX .005(.127) MIN .070(1.78) .020(.508) .023(.584) .014(.356) .065(1.65) .040(1.02) .325(8.26) .300(7.62)

15 REF

.400(10.2) MAX .012(.305) .008(.203) .110(2.79) .090(2.29) .151(3.84) .125(3.18) SEATING PLANE .200(5.06) MAX 1.100(27.94) REF .020(.508) .013(.330) .299(7.60) .291(7.39) .420(10.7) .393(9.98) .105(2.67) .092(2.34) .050(1.27) BSC .616(15.6) .598(15.2) .012(.305) .003(.076) .013(.330) .009(.229) .050(1.27) .015(.381)8

0 REF

*Controlling dimension: millimeters 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AB 24P3, 24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 AF 24S, 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) 24X, 24-lead, 0.173" Wide, Thin Shrink Small Outline (TSSOP) Dimensions in Millimeters and (Inches)*

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