ATF22LV10CZ ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • 3.0V to 5.5V Operating Range
  • Advanced Low Voltage, Zero Power, Electrically Erasable Programmable Logic Device
  • Edge-Sensing “Zero” Power
  • Low Voltage Equivalent of ATF22V10CZ
  • “Zero” Standby Power (25 µA Maximum)
  • Ideal for Battery Powered Systems
  • 25 ns Maximum Propagation Delay
  • CMOS and TTL Compatible Inputs and Outputs
  • Latch Feature Hold Inputs to Previous Logic States
  • Advanced E2 Technology Reprogrammable 100% Tested
  • High Reliability CMOS Process

20 Year Data Retention

100 Erase/Write Cycles

2,000V ESD Protection 200 mA Latchup Immunity

  • Commercial and Industrial Temperature Ranges
  • Dual-in-Line and Surface Mount Standard Pinouts Block Diagram DIP/SOIC PLCC Note: For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For supe- rior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22. Top view Rev. 0779E/LV10CZ-E–05/98 CLK/IN IN IN IN IN IN IN IN IN IN IN GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN TSSOP Top View

DC and AC Operating Conditions Commercial Industrial Operating Temperature (Case) 0°C - 70°C -40°C - 85°C VCC Power Supply 3.0V - 5.5V 3.0V - 5.5V

Description

The ATF22LV10CZ is a high performance CMOS (Electri- cally Erasable) Programmable Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash mem- ory technology and provides 25 ns speed with stand-by current of 25 µA maximum. All speed ranges are specified over the 3.0V to 5.5V range for industrial and commercial temperature ranges. The ATF22LV10CZ provides a low voltage and edge- sensing “zero” power CMOS PLD solution with “zero” standby power (5 µA typical). The ATF22LV10CZ powers down automatically to the zero power mode through At- mel’s patented Input Transition Detection (ITD) circuitry when the device is idle. The ATF22LV10CZ is capable of operating at supply voltages down to 3.0V. Pin “keeper” circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power con- sumed by pull-up resistors. The ATF22LV10CZ macrocell incorporates a variable product term architecture. Each output is allocated from 8 to 16 product terms which allows highly complex logic functions to be realized. Two additional product terms are included to provide synchronous reset and asynchronous reset. These additional product terms are common to all 10 registers and are automatically cleared upon power up. Register Preload simplifies testing. A Security Fuse pre- vents unauthorized copying of programmed fuse patterns. Voltage on Any Pin with Voltage on Input Pins with Respect to Ground (1) Programming Voltage with (1) *NOTICE: Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Note: 1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum out- put pin voltage is Vcc + 0.75V dc, which may over- shoot to 7.0V for pulses of less than 20 ns.

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Functional Logic Diagram Description The Functional Logic Diagram describes the ATF22LV10CZ architecture. The ATF22LV10CZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured into one of four output configurations: active-high/low or registered/combinato- rial. The universal architecture of the ATF22LV10CZ can be programmed to emulate most 24-pin PAL devices. Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the contents of the ATF22LV10CZ. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Se- curity Fuse. DC Characteristics Symbol Parameter Condition Min Typ Max Units IIL Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL(MAX) -10 µA IIH Input or I/O High Leakage Current VCC - 0.7V ≤ VIN ≤ VCC 10 µA ICC Clocked Power Supply Current VCC = MAX, Outputs Open, f = 15 MHz Com. 55 85 mA Ind. 60 90 mA ISB Power Supply Current, Standby VCC = MAX, VIN = MAX, Outputs Open Com. 5 25 µA Ind. 5 50 µA IOS (1) Output Short Circuit Current VOUT = 0.5V -130 mA VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 V CC + 0.75 V VOL Output Low Voltage VIN = VIH or VIL VCC = MIN, IOL = 8 mA Com. Ind. 0.5 V VOH Output High Voltage VIN = VIH or VIL, VCC = MIN, IOH = -4.0 mA 2.4 V Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. ATF22LV10CZ

AC Characteristics (1) Symbol Parameter -25 Min Max Units tPD Input to Feedback to Non-Registered Output 3 25 ns tCF Clock to Feedback 13 ns tCO Clock to Output 2 15 ns tS Input or Feedback Setup Time 15 ns tH Input Hold Time 0 ns tP Clock Period 25 ns tW Clock Width 12.5 ns FMAX External Feedback 1/(tS + tCO ) Internal Feedback 1/(tS + tCF ) No Feedback 1/(tP) 33.3 35.7 40.0 MHz MHz MHz t EA Input to Output Enable 3 25 ns tER Input to Output Disable 3 25 ns tAP Input or I/O to Asynchronous Reset of Register 3 25 ns tSP Setup Time, Synchronous Preset 15 ns tAW Asynchronous Reset Width 25 ns tAR Asynchronous Reset Recovery Time 25 ns tSPR Synchronous Preset to Clock Recovery Time 15 ns Note: 1. See ordering information for valid part numbers. INPUTS, I/O REG. FEEDBACK SYNCH. PRESET CP ASYNCH. RESET REGISTERED OUTPUTS COMBINATORIAL OUTPUTS VALID VALID VALID VALID VALID VALID OUTPUT DISABLED OUTPUT DISABLED tS tH tW tW tP tARtAW tAPtCO tPD tER tEA tEAtER

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Note: Similar competitors’ devices are specified with slightly different loads. These load differ- ences may affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification conditions. Output Test Loads Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ Max Units Conditions C IN 58 p F V IN = 0V C OUT 68 p F V OUT = 0V Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. ATF22LV10CZ

The registers in the ATF22LV10CZ are designed to reset during power up. At a point delayed slightly from VCC crossing VRST , all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic and start below 0.7V 3. The clock must remain stable during TPR . 2. After TPR , all input and feedback setup times must be met before driving the clock pin high. Preload of Register Outputs The ATF22LV10CZ’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. Electronic Signature Word There are 64 bits of programmable memory that are al- ways available to the user, even if the device is secured. These bits can be used for user-specific data. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF22LV10CZ fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. Programming/Erasing Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/program- ming. Parameter Description Typ Max Units TPR Power-Up Reset Time 600 1,000 ns VRST Power-Up Reset Voltage 2.3 2.7 V

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All ATF22LV10CZ family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs and device outputs are at known states. These are rela- tively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams be- low). Input Diagram I/O Diagram ATF22LV10CZ

Functional Logic Diagram ATF22LV10CZ

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(ns) tS (ns) tCO (ns) Ordering Code Package Operation Range 25 15 15 ATF22LV10CZ-25JC 28J Commercial ATF22LV10CZ-25PC 24P3 (0 °C to 70°C) ATF22LV10CZ-25SC 24S ATF22LV10CZ-25XC 24X 15 15 ATF22LV10CZ-25JI 28J Industrial ATF22LV10CZ-25PI 24P3 (-40 °C to +85°C) ATF22LV10CZ-25SI 24S ATF22LV10CZ-25XI 24X Package Type 28J 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) 24P3 24-Lead, 0.300" Wide, Plastic Dual Inline Package (DIP) 24S 24-Lead, 0.300" Wide, Plastic Gull WIng Small Outline (SOIC) 24X 24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) ATF22LV10CZ