ATF22LV10CZ_05 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- 3.0V to 5.5V Operating Range Lowest Power in It Class Advanced Low-voltage, Zero-power, Electrically Erasable Programmable Logic Device “Zero” Standby Power (25 µA Maximum) (Input Transition Detection) Low-voltage Equivalent of ATF22V10CZ Ideal for Battery Powered Systems CMOS- and TTL-compatible Inputs and Outputs Inputs are 5V Tolerant Latch Feature Hold Inputs to Previous Logic States EE Technology – Reprogrammable – 100% Tested High-reliability CMOS Process – 20-year Data Retention – 10,000 Erase/Write Cycles – 2,000V ESD Protection – 200 mA Latch-up Immunity Commercial and Industrial Temperature Ranges Dual Inline and Surface Mount Standard Pinouts Green Package Options (Pb/Halide-free/RoHS Compliant) Available 1. Description The ATF22LV10CZ/CQZ is a high-performance CMOS (electrically erasable) pro- grammable logic device (PLD) t hat utilizes Atmel’s proven electrically erasable Flash memory technology and provides 25 ns s peed with standby current of 25 µA maxi- mum. All speed ranges are specified over the 3.0V to 5.5V range for industrial and commercial temperature ranges. The ATF22LV10CZ/CQZ provides a low-vo ltage and edge-sensing “zero” power CMOS PLD solution with “zero” st andby power (5 µA typical). The ATF22LV10CZ/CQZ powers down automatically to the zero power mode through Atmel’s patented Input Transition Detection (ITD) circuitry when the device is idle. The ATF22LV10CZ/CQZ is capable of operating at supply voltages down to 3.0V. Pin “keeper” circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power consumed by pull-up resistors. The “CQZ” combines this low high-frequency ICC of the “Q” design with the “Z” feature. The ATF22LV10CZ/CQZ macrocell incorporates a variable product term architecture. Each output is allocated from 8 to 16 product terms which allows highly complex logic functions to be realized. Two additional product terms are included to provide syn- chronous reset and asynchronous reset. These additional product terms are common to all 10 registers and are automatically cleared upon power-up. Register Preload sim- plifies testing. A security fuse prev ents unauthorized copying of programmed fuse patterns. High- performance EE PLD ATF22LV10CZ ATF22LV10CQZ 0779L–PLD–12/05
0779L–PLD–12/05 ATF22LV10C(Q)Z 3. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V DC, which may under- shoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is V CC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. Voltage on Any Pin with Voltage on Input Pins with Respect to Ground Programming Voltage with (1) 4. DC and AC Operating Conditions Commercial Industrial Operating Temperature (Ambient) 0 °C - 70°C- 4 0 °C - 85°C VCC Power Supply 3.0V - 5.5V 3.0V - 5.5V
0779L–PLD–12/05 ATF22LV10C(Q)Z Note: 1. Not more than one output at a ti me should be shorted. Duration of short circuit test should not exceed 30 sec. 2. For DC characterization, the test condition of V CC = Max corresponds to 3.6V.
4.1 DC Characteristics
Symbol Parameter Condition (2) Min Typ Max Units IIL Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL (Max) -10.0 µA IIH Input or I/O High Leakage Current (VCC - 0.2)V ≤ VIN ≤ VCC 10.0 µA ICC Clocked Power Supply Current VCC = Max Outputs Open, f = 15 MHz CZ-25 Com. 50.0 85.0 mA CZ-25 Ind. 55.0 90.0 mA CQZ-30 Com. 18.0 50.0 mA CQZ-30 Ind. 19.0 60.0 mA I SB Power Supply Current, Standby VCC = Max VIN = Max Outputs Open CZ-25 Com. 3.0 25.0 µA CZ-25 Ind. 4.0 50.0 µA CQZ-30 Com. 3.0 25.0 µA CQZ-30 Ind. 4.0 50.0 µA I OS (1) Output Short Circuit Current VOUT = 0.5V -130.0 mA VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 V CC + 0.75 V VOL Output Low Voltage VIN = VIH or VIL VCC = Min, IOL = 16 mA 0.5 V VOH Output High Voltage VIN = VIH or VIL VCCIO = Min, IOH = -2.0 mA 2.4 V VOH Output High Voltage I OH = -100 µA V CC - 0.2V V
0779L–PLD–12/05 ATF22LV10C(Q)Z
4.2 AC Waveforms
Note: 1. See ordering information for valid part numbers. INPUTS, I/O REG. FEEDBACK SYNCH. PRESET CP ASYNCH. RESET REGISTERED OUTPUTS COMBINATORIAL OUTPUTS VALID VALID VALID VALID VALID VALID OUTPUT DISABLED OUTPUT DISABLED tS tH tW tW tP tARtAW tAPtCO tPD tER tEA tEAtER
4.3 AC Characteristics (1)
-25 -30 UnitsMin Max Min Max tPD Input or Feedback to Non-registered Output 3.0 25.0 10.0 30.0 ns tCF Clock to Feedback 13.0 10.0 15.0 ns tCO Clock to Output 2.0 15.0 4.0 20.0 ns tS Input or Feedback Setup Time 15.0 18.0 ns tH Input Hold Time 0 0 ns tP Clock Period 25.0 30.0 ns tW Clock Width 12.5 15.0 ns fMAX External Feedback 1/(tS + tCO) Internal Feedback 1/(tS + tCF) No Feedback 1/(tP) 33.3 35.7 40.0 25.0 30.0 33.3 MHz MHz MHz t EA Input to Output Enable 3.0 25.0 10.0 30.0 ns tER Input to Output Disable 3.0 25.0 10.0 30.0 ns tAP Input or I/O to Asynchronous Reset of Register 3.0 25.0 10.0 3.0 ns tSP Setup Time, Synchronous Preset 15.0 20.0 ns tAW Asynchronous Reset Width 25.0 30.0 ns tAR Asynchronous Reset Recovery Time 25.0 30.0 ns tSPR Synchronous Preset to Clock Recovery Time 15.0 20.0 ns
0779L–PLD–12/05 ATF22LV10C(Q)Z
4.4 Input Test Waveforms
4.4.1 Input Test Waveforms and Measurement Levels
4.4.2 Output Test Loads
Note: Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification conditions.
4.5 Pin Capacitance
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
4.6 Power-up Reset
The registers in the ATF22LV10CZ/CQZ are designed to reset during power-up. At a point delayed slightly from V CC crossing V RST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine init ialization. However, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the following conditions are required: 1. The V CC rise must be monotonic and start below 0.7V. 2. The clock must remain stable during T PR. 3. After T PR, all input and feedback setup times must be met before driving the clock pin high.
4.7 Preload of Register Outputs
The ATF22LV10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file Table 4-1. Pin Capacitance (f = 1 MHz, T = 25°C(1)) Typ Max Units Conditions CIN 58 p F V IN = 0V CI/O 68 p F V OUT = 0V
0779L–PLD–12/05 ATF22LV10C(Q)Z with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done auto- matically by most of the approved programmers after the programming. 5. Electronic Signature Word There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. 6. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF22LV10CZ/CQZ fuse pat- terns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. 7. Programming/Erasing Programming/erasing is performed using standard PLD programmers. See CMOS PLD Pro- gramming Hardware & Software Support for information on software/ programming. 8. Input and I/O Pin Keepers All ATF22LV10CZ/CQZ family members have inte rnal input and I/O pin-keeper circuits. There- fore, whenever inputs or I/Os are not being driven ex ternally, they will maintain their last driven state. This ensures that all logic array inputs and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below). Figure 8-1. Input Diagram Table 7-1. Programming/Erasing Parameter Description Typ Max Units TPR Power-up Reset Time 600 1000 ns VRST Power-up Reset Voltage 2.3 2.7 V 100K VCC ESD PROTECTION CIRCUIT INPUT
0779L–PLD–12/05 ATF22LV10C(Q)Z Figure 8-2. I/O Diagram 9. Functional Logic Diagram Description The Functional Logic Diagram describes the ATF22LV10CZ/CQZ architecture. The ATF22LV10CZ/CQZ has 12 inputs and 10 I/O ma crocells. Each macrocell can be config- ured into one of four output configurations: active high/low or registered/combinatorial. The universal architecture of the ATF22LV10CZ/CQZ can be programmed to emulate most 24-pin PAL devices. Unused product terms are automatically disabled by the compiler to decrease power consump- tion. A security fuse, when programmed, protects the contents of the ATF22LV10CZ/CQZ. Eight bytes (64 fuses) of User Signature are accessib le to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. 100K VCC VCC DATA OE I/O INPUT
0779L–PLD–12/05 ATF22LV10C(Q)Z Figure 9-1. Functional Logic Diagram ATF22LV10CZ/CQZ
0779L–PLD–12/05 ATF22LV10C(Q)Z ATF22LV10CZ/CQZ STANDBY CURRENT VS. SUPPLY VOLTAGE (T A = 25°C) 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 3.00 3.30 3.60 V CC (V) ICC (uA) NORMALIZED I CC VS. TEMP 0.8 0.9 1.0 1.1 1.2 TEMPERATURE (C) NORMALIZED ICC ATF22LV10CZ SUPPLY CURRENT VS. INPUT FREQUENCY (V CC = 3.3V, T A = 25°C) 0.000 10.000 20.000 30.000 40.000 50.000 60.000 0 0.5 2.5 5 7.5 10 25 37.5 50 Frequency (MHz) ICC (mA) ATF22LV10CQZ SUPPLY CURRENT VS. INPUT FREQUENCY (V CC = 3.3V, T A = 25°C) 0.000 5.000 10.000 15.000 20.000 25.000 Frequency (MHz) ICC (mA) ATF22LV10CZ/CQZ SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V) -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 SUPPLY VOLTAGE (V) Ioh (mA) ATF22LV10C/CZ OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) -14.0 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 VOH (V) IOH (mA) ATF22LV10CZ/CQZ OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V) 32.0 33.0 34.0 35.0 36.0 37.0 38.0 39.0 40.0 SUPPLY VOLTAGE (V) IOL (mA) ATF22LV10CZ/CQZ OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (V CC = 3.3V, T A = 25°C) 0.0 20.0 40.0 60.0 80.0 100.0 VOL (V) IOL (mA)
0779L–PLD–12/05 ATF22LV10C(Q)Z ATF22LV10CZ/CQZ INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V CC = 3.3V, T A = 25°C) -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0 INPUT VOLTAGE (V) INPUT CURRENT (mA) ATF22LV10CZ/CQZ INPUT CURRENT VS. INPUT VOLTAGE (V CC = 3.3V, T A = 25°C) -5.0 0.0 5.0 10.0 15.0 INPUT VOLTAGE (V) INPUT CURRENT (µA) NORMALIZED T PD VS. VCC 0.8 0.9 1.0 1.1 1.2 SUPPLY VOLTAGE (V) NORMALIZED TPD NORMALIZED T PD VS. TEMP 0.8 0.9 1.0 1.1 1.2 TEMPERATURE (C) NORMALIZED TPD NORMALIZED T CO VS. VCC 0.8 0.9 1.0 1.1 1.2 SUPPLY VOLTAGE (V) NORMALIZED TCO NORMALIZED T CO VS. TEMP 0.8 0.9 1.0 1.1 1.2 TEMPERATURE (C) NORMALIZED TCO NORMALIZED T SU VS. VCC 0.8 0.9 1.0 1.1 1.2 SUPPLY VOLTAGE (V) NORMALIZED TSU NORMALIZED T SU VS. TEMP 0.8 0.9 1.0 1.1 1.2 TEMPERATURE (C) NORMALIZED TSU
0779L–PLD–12/05 ATF22LV10C(Q)Z 22LV10CZ/CQZ DELTA T PD VS. OUTPUT LOADING -5.0 0.0 5.0 10.0 15.0 OUTPUT LOADING (PF) DELTA TPD (ns) 22LV10CZ/CQZ DELTA T CO VS. OUTPUT LOADING -5.0 0.0 5.0 10.0 15.0 OUTPUT LOADING (PF) DELTA TCO (ns) DELTA TPD VS. # OF OUTPUT SWITCHING -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 NUMBER OF OUTPUTS SWITCHING DELTA TPD (ns) DELTA TCO VS. # OF OUTPUT SWITCHING -0.3 -0.2 -0.2 -0.1 -0.1 0.0 NUMBER OF OUTPUTS SWITCHING DELTA TCO (ns)
0779L–PLD–12/05 ATF22LV10C(Q)Z 10. Ordering Information
10.3 Using “C” Product for Industrial
To use commercial product for industrial temperature ranges, simply de-rate I CC by 15% on the “C” device. No speed de-rating is necessary.
10.1 Standard Package Options
tPD (ns) t S (ns) t CO (ns) Ordering Code Package Operation Range 25 15 15 ATF22LV10CZ-25JC ATF22LV10CZ-25PC ATF22LV10CZ-25SC ATF22LV10CZ-25XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF22LV10CZ-25JI ATF22LV10CZ-25PI ATF22LV10CZ-25SI ATF22LV10CZ-25XI 28J 24P3 24S 24X Industrial (-40°C to +85°C) ATF22LV10CQZ-30JC ATF22LV10CQZ-30PC ATF22LV10CQZ-30SC ATF22LV10CQZ-30XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF22LV10CQZ-30JI ATF22LV10CQZ-30PI ATF22LV10CQZ-30SI ATF22LV10CQZ-30XI 28J 24P3 24S 24X Industrial (-40°C to +85°C)
10.2 ATF22LV10CQZ Green Package Opti ons (Pb/Halide-free/RoHS Compliant)
tPD (ns) t S (ns) t CO (ns) Ordering Code Package Operating Range 30 15 15 ATF22LV10CQZ-30JU ATF22LV10CQZ-30PU ATF22LV10CQZ-30SU ATF22LV10CQZ-30XU 28J 24P3 24S 24X Industrial (-40°C to +85°C) Package Type 28J 28-lead, Plastic J-leaded Chip Carrier (PLCC) 24P3 24-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24S 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24X 24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
0779L–PLD–12/05 ATF22LV10C(Q)Z 11. Packaging Information 11.1 28J – PLCC
2325 Orchard Parkway
San Jose, CA 95131R TITLE DRAWING NO. REV. B28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) 28J 10/04/01 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A B1 D2/E2 B e E1 E D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 12.319 – 12.573 D1 11.430 – 11.582 Note 2 E 12.319 – 12.573 E1 11.430 – 11.582 Note 2 D2/E2 9.906 – 10.922 B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP
0779L–PLD–12/05 ATF22LV10C(Q)Z 11.2 24P3 – PDIP San Jose, CA 95131 TITLE DRAWING NO. R REV. 24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) D24P3 6/1/04 PIN B E C L SEATING PLANE A D e eB eC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 5. 334 A1 0. 381 – – D 31.623 – 32.131 Note 2 E 7.620 – 8.255 E1 6.096 – 7.112 Note 2 B 0. 356 – 0.559 B1 1.270 – 1.651 L 2.921 – 3.810 C 0.20 3 – 0. 356 eB – – 10.922 eC 0.000 – 1.524 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference M S-001, Variation AF . 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
0779L–PLD–12/05 ATF22LV10C(Q)Z 11.3 24S – SOIC 0º ~ 8º PIN 1 ID PIN 1 06/17/2002 San Jose, CA 95131 TITLE DRAWING NO. REV. 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) B24S R COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 2.65 A1 0.10 – 0.30 D 10.00 – 10.65 D1 7.40 – 7.60 E 15.20 – 15.60 B 0.33 – 0.51 L 0.40 – 1.27 L1 0.23 – 0.32 e 1.27 BSC B DD1 e E A L
0779L–PLD–12/05 ATF22LV10C(Q)Z 11.4 24X – TSSOP 0.30(0.012) 0.19(0.007) 4.48(0.176) 4.30(0.169) 6.50(0.256) 6.25(0.246) 0.65(0.0256)BSC 7.90(0.311) 7.70(0.303) 0.15(0.006) 0.05(0.002) 0.20(0.008) 0.09(0.004) 0.75(0.030) 0.45(0.018) 0º ~ 8º 1.20(0.047)MAX Dimensions in Millimeter and (Inches)* JEDEC STANDARD MO-153 AD Controlling dimension: millimeters PIN 1 04/11/2001 San Jose, CA 95131 TITLE DRAWING NO. R REV. 24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline Package (TSSOP) A24X
0779L–PLD–12/05 ATF22LV10C(Q)Z 12. Revision History Version No./Release Date History Revision L – November 2005 1. Added Green Package options
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