ATF20V8BQL-15JC

ATF20V8B ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Industry Standard Architecture – Emulates Many 24-Pin PALs® – Low Cost Easy-to-Use Software Tools
• High-Speed Electrically Erasable Programmable Logic Devices – 7.5 ns Maximum Pin-to-Pin Delay
• Several Power Saving Options
• CMOS and TTL Compatible Inputs and Outputs
• Input and I/O Pull-Up Resistors
• Advanced Flash Technology – Reprogrammable – 100% Tested
• High Reliability CMOS Process – 20 Year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-Line and Surface Mount Packages in Standard Pinouts Block Diagram Device I CC , Stand-By I CC , Active A TF20V8B 50 mA 55 mA A TF20V8BQ 35 mA 40 mA A TF20V8BQL 5 mA 20 mA High- Performance EE PLD ATF20V8B Rev. 0407E–05/98 Pin Configurations Pin Name Function CLK Clock I Logic Inputs I/O Bidirectional Buffers OE Output Enable * No Internal Connection V CC +5V Supply TSSOP Top View CLK/IN IN IN IN IN IN IN IN IN IN IN GND VCC IN I/O I/O I/O I/O I/O I/O I/O I/O IN OE/IN DIP/SOIC PLCC T op View

Description

The ATF20V8B is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash memory technol- ogy. Speeds down to 7.5 ns and power dissipation as low as 10 mA are offered. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges, and 5V ± 5% for commercial temperature ranges. Several low power options allow selection of the best solu- tion for various types of power-limited applications. Each of these options significantly reduces total system power and enhances system reliability. The ATF20V8Bs incorporate a superset of the generic architectures, which allows direct replacement of the 20R8 family and most 24-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with soft- ware, allow highly complex logic functions to be realized. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V DC which may under- shoot to -2.0V for pulses of less than 20 ns.Maxi- mum output pin voltage is V CC + 0.75V DC which may overshoot to 7.0V for pulses of less than 20 ns. Voltage on Any Pin with (1) Voltage on Input Pins with Respect to Ground (1) Programming Voltage with (1) DC and AC Operating Conditions Commercial Industrial Operating T emperature (Case) 0°C - 70°C -40°C - 85°C VCC Power Supply 5V ± 5% 5V ± 10%

Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. DC Characteristics Symbol Parameter Condition Min Typ Max Units IIL Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL(MAX) -35 -100 µA IIH Input or I/O High Leakage Current 3.5 ≤ VIN ≤ VCC 10 µA ICC Power Supply Current, Standby VCC = MAX, VIN = MAX, Outputs Open B-7, -10 Com. 60 90 mA Ind. 60 100 mA B-15, -25 Com. 60 80 mA Ind. 60 90 mA BQ-10 Com. 35 55 mA BQL-15, -25 Com. 5 10 mA Ind. 5 15 mA ICC2 Clocked Power Supply Current VCC = MAX, Outputs Open, f = 15 MHz B-7, -10 Com. 80 110 mA Ind. 80 125 mA B-15, -25 Com. 60 90 mA Ind. 60 105 mA BQ-10 Com. 40 55 mA BQL-15, -25 Com. 20 35 mA Ind. 20 40 mA IOS (1) Output Short Circuit Current VOUT = 0.5V -130 mA VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 V CC + 0.75 V VOL Output Low Voltage VIN = VIH or VIL, VCC = MIN IOL = 24 mA Com., Ind. 0.5 V IOL = 16 mA 0.5 V VOH Output High VoltageVIN = VIH or VIL, VCC = MIN IOH = -4.0 mA 2.4 V

AC Waveforms (1) Note: 1. See ordering information for valid part numbers and speed grades. AC Characteristics(1) Symbol Parameter -7 -10 -15 -25 UnitsMin Max Min Max Min Max Min Max tPD Input or Feedback to Non-Registered Output 8 outputs switching 3 7.5 3 10 3 15 3 25 ns 1 output switching 7 ns tCF Clock to Feedback 3 6 8 10 ns tCO C l o c k t o O u t p u t 25272 1 0 2 1 2n s tS Input or Feedback Setup Time 5 7.5 12 15 ns tH H o l d T i m e 0000 n s tP C l o c k P e r i o d 8 1 21 62 4 n s tW Clock Width 4 6 8 12 ns FMAX External Feedback 1/(tS + tCO ) 100 68 45 37 MHz Internal Feedback 1/(tS + tCF ) 125 74 50 40 MHz No Feedback 1/(tP) 125 83 62 41 MHz tEA Input to Output Enable — Product T erm 3 9 3 10 3 15 3 20 ns tER Input to Output Disable —Product T erm 2 9 2 10 2 15 2 20 ns tPZX OE pin to Output Enable 2 6 2 10 2 15 2 20 ns tPXZ OE pin to Output Disable 1.5 6 1.5 10 1.5 15 1.5 20 ns

tR , tF < 5 ns (10% to 90%) Output Test Loads Commercial Note: 1. T ypical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power Up Reset The registers in the ATF20V8Bs are designed to reset dur- ing power up. At a point delayed slightly from VCC crossing VRST , all registers will be reset to the low state. As a result, the registered output state will always be high on power-up. This feature is critical for state machine initialization. How- ever, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the fol- lowing conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during tPR . Preload of Registered Outputs The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. Electronic Signature Word There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF20V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. Programming/Erasing Programming/erasing is performed using standard PLD programmers. For further information, see the Configurable Logic Databook, section titled, “CMOS PLD Programming Hardware and Software Support.” Pin Capacitance f = 1 MHz, T = 25°C(1) Typ Max Units Conditions C IN 58 p F V IN = 0V C OUT 68 p F V OUT = 0V Parameter Description Typ Max Units tPR Power-Up Reset Time 600 1,000 ns VRST Power-Up Reset Voltage 3.8 4.5 V

All ATF20V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to V CC . This ensures that all logic array inputs are at known states. These are relatively weak active pull-ups that can easily be overdriven by TTL-compatible drivers (see input and I/O diagrams below). Input Diagram I/O Diagram Functional Logic Diagram Description The Logic Option and Functional Diagrams describe the ATF20V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input. The ATF20V8B can be configured in one of three different modes. Each mode makes the ATF20V8B look like a dif- ferent device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The deter- mining factors would be the usage of register versus com- binatorial outputs and dedicated outputs versus outputs with output enable control. The ATF20V8B universal architecture can be programmed to emulate many 24-pin PAL devices. These architectural subsets can be found in each of the configuration modes described in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF20V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability. Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the content of the ATF20V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the Security Fuse.

Note: 1. Only applicable for version 3.4 or lower. ATF20V8B Registered Mode PAL Device Emulation / PAL Replacement The registered mode is used if one or more registers are required. Each macrocell can be configured as either a reg- istered or combinatorial output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight prod- uct terms are allocated to the sum term. For a combinato- rial output or I/O, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an input, the output enable is permanently disabled. Any register usage will make the compiler select this mode. The following registered devices can be emulated using this mode: 20R8 20RP8 20R6 20RP6 20R4 20RP4 Registered Mode Operation Compiler Mode Selection Registered Complex Simple Auto Select ABEL, Atmel-ABEL P20V8R P20V8C P20V8 P20V8 CUPL G20V8MS G20V8MA G20V8 G20V8A LOG/iC GAL20V8_R (1) GAL20V8_C7 (1) GAL20V8_C8 (1) GAL20V8 OrCAD-PLD “Registered” “Complex” “Simple” GAL20V8 PLDesigner P20V8 P20V8 P20V8 P20V8 Tango-PLD G20V8 G20V8 G20V8 G20V8

Registered Mode Logic Diagram

PAL Device Emulation/PAL Replacement In the Complex Mode, combinatorial output and I/O func- tions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are outputs only. They do not have input capability. In this mode, each mac- rocell has seven product terms going to the sum term and one product term enabling the output. Combinatorial applications with an OE requirement will make the compiler select this mode. The following devices can be emulated using this mode: 20L8 20H8 20P8 Complex Mode Operation ATF20V8B Simple Mode PAL Device Emulation / PAL Replacement In the Simple Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are perma- nently configured as combinatorial outputs. Other macro- cells can be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular inputs. The compiler selects this mode when all outputs are combi- natorial without OE control. The following simple PALs can be emulated using this mode: 14L8 14H8 14P8 16L6 18H6 16P6 18L4 18H4 18P4 20L2 20H2 20P2 Simple Mode Option

Complex Mode Logic Diagram

Ordering Information

tPD (ns) t S (ns) t CO (ns) Ordering Code Package Operation Range 7.5 5 5 A TF20V8B-7JC A TF20V8B-7PC A TF20V8B-7SC A TF20V8B-7XC 28J 24P3 24S 24X Commercial (0°C to 70°C) 10 7.5 7 A TF20V8B-10JC ATF20V8B-10PC ATF20V8B-10SC ATF20V8B-10XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF20V8B-10JI ATF20V8B-10PI ATF20V8B-10SI ATF20V8B-10XI 28J 24P3 24S 24X Industrial (-40°C to 85°C) 15 12 10 ATF20V8B-15JC ATF20V8B-15PC ATF20V8B-15SC ATF20V8B-15XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF20V8B-15JI ATF20V8B-15PI ATF20V8B-15SI ATF20V8B-15XI 28J 24P3 24S 24X Industrial (-40°C to 85°C) 25 15 12 ATF20V8B-25JC ATF20V8B-25PC ATF20V8B-25SC ATF20V8B-25XC 28J 24P3 24S 24X Commercial (0°C to 70°C) ATF20V8B-25JI ATF20V8B-25PI ATF20V8B-25SI ATF20V8B-25XI 28J 24P3 24S 24X Industrial (-40°C to 85°C) Package Type 28J 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) 24P3 24-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24S 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24X 24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) (continued)

10 7.5 7 A TF20V8BQ-10JC A TF20V8BQ-10PC A TF20V8BQ-10XC 28J 24P3 24X Commercial (0°C to 70°C) 15 12 10 A TF20V8BQL-15JC A TF20V8BQL-15PC A TF20V8BQL-15SC A TF20V8BQL-15XC 28J 24P3 24S 24X Commercial (0°C to 70°C) 25 15 12 A TF20V8BQL-25JC A TF20V8BQL-25PC A TF20V8BQL-25SC A TF20V8BQL-25XC 28J 24P3 24S 24X Commercial (0°C to 70°C) A TF20V8BQL-25JI A TF20V8BQL-25PI A TF20V8BQL-25SI A TF20V8BQL-25XI 28J 24P3 24S 24X Industrial (-40°C to 85°C) tPD (ns) t S (ns) t CO (ns) Ordering Code Package Operation Range Package Type 28J 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) 24P3 24-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 24S 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24X 24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)

.045(1.14) X 45°PIN NO. 1 IDENTIFY .032(.813) .026(.660) .050(1.27) TYP .300(7.62) REF SQ .012(.305) .008(.203) .021(.533) .013(.330) .430(10.9) .390(9.91)SQ .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .456(11.6) .450(11.4) .495(12.6) .485(12.3) SQ SQ 1.27(32.3) 1.25(31.7) PIN .266(6.76) .250(6.35) .090(2.29) MAX .005(.127) MIN .070(1.78) .020(.508) .023(.584) .014(.356) .065(1.65) .040(1.02) .325(8.26) .300(7.62)

15 REF

.400(10.2) MAX .012(.305) .008(.203) .110(2.79) .090(2.29) .151(3.84) .125(3.18) SEATING PLANE .200(5.06) MAX 1.100(27.94) REF .020(.508) .013(.330) .299(7.60) .291(7.39) .420(10.7) .393(9.98) .105(2.67) .092(2.34) .050(1.27) BSC .616(15.6) .598(15.2) .012(.305) .003(.076) .013(.330) .009(.229) .050(1.27) .015(.381)8

0 REF

28J, 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AB 24P3, 24-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 AF 24S, 24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) 24X, 24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) Dimensions in Millimeters and (Inches)