ATF1502ASL-25QI44

ATF1502AS ATMEL | Alldatasheet

Document overview

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Technical content

Features

• High Density, High Performance Electrically Erasable Complex Programmable Logic Device – 32 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 44 pin – 7.5 ns Maximum Pin-to-Pin Delay – Registered Operation Up To 125 MHz – Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell – D/T/Latch Configurable Flip Flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Programmable Output Open Collector Option – Maximum Logic utilization by burying a register with a COM output
• Advanced Power Management Features – Automatic 3 mA Stand-By for “L” Version – Pin-Controlled 4 mA Stand-By Mode (Typical) – Programmable Pin-Keeper Inputs and I/Os – Reduced-Power Feature Per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-pin PLCC; TQFP; and PQFP
• Advanced EEPROM Technology – 100% Tested – Completely Reprogrammable – 100 Program/Erase Cycles – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-Up Immunity
• JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• PCI-compliant
• 3.3 or 5.0V I/O pins
• Security Fuse Feature Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• D - Latch Mode
• Combinatorial Output with Registered Feedback within any Macrocell
• Three Global Clock Pins
• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
• Fast Registered Input from Product Term
• Programmable “Pin-Keeper” Option
• VCC Power-Up Reset Option
• Pull-Up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features – Edge Controlled Power Down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O High Performance E2PROM CPLD ATF1502AS Preliminary Rev. 0995A–04/98

Description

The ATF1502AS is a high performance, high density Com- plex Programmable Logic Device (CPLD) which utilizes Atmel’s proven electrically erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI,MSI, LSI and classic PLDs. The ATF1502AS’s enhanced routing switch matrices increase usable gate count, and the odds of successful pin- locked design modifications. The ATF1502AS has up to 32 bi-directional I/O pins and 4 dedicated input pins, depending on the type of device pack- age selected. Each dedicated pin can also serve as a glo- bal control signal; register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Block Diagram Each of the 32 macrocells generates a buried feedback, which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. I/O/TDI I/O I/O GND PD1/I/O I/O TMS/I/O I/O VCC I/O I/O I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O/PD1 VCC/PD2 I/OE2/GCK2 GCLR/I I/OE1 GCK1/I GND GCK3 I/O TDI/I/O I/O I/O GND PD1/I/O I/O I/O/TMS I/O VCC I/O I/O I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O I/O I/O I/O/PD1 VCC/PD2 GCK2/OE2/I GCLR/I OE1/I GCK1/I GND I/O/GCLK3 I/O B

fan in of up to 40 product terms. enable; and logic array inputs. accessible regardless of the state of the Security Fuse. be made in the field via software. Figure 1. ATF1502AS Macrocell global bus and regional bus. rial outputs, the fixed level input allows polarity selection. to emulate T- and JK-type flip-flops.

macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR opera- tion, the flip flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. The clock itself can either be one of the Global CLK Signal GCK[0 : 2] or an individual product term. The flip flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off. Output Select and Enable The ATF1502AS macrocell output can be selected as reg- istered or combinatorial. The buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered. The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be permanently enabled for simple output operation. Buffers can also be permanently disabled to allow use of the pin as an input. In this configu- ration all the macrocell resources are still available, includ- ing the buried feedback, expander and CASCADE logic. The output enable for each macrocell can be selected as either of the two dedicated OE input pins as an I/O pin con- figured as an input, or as an individual product term. Global Bus/Switch Matrix The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 32 macrocells. The Switch Matrix in each Logic Block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the Logic Block. Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to 4 macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The 4 foldback terms in each region allows generation of high fan-in sum terms (up to 9 product terms) with a small additional delay. Programmable Pin-Keeper Option for Inputs and I/Os The ATF1502AS offers the option of programming all input and I/O pins so that pin keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which cause unnec- essary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Input Diagram I/O Diagram Speed/Power Management The ATF1502AS has several built-in speed and power management features. The ATF1502AS contains circuitry that automatically puts the device into a low power stand- by mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides a proportional power savings for most applications running at system speeds below 50 MHz. This feature may be selected as a design option. To further reduce power, each ATF1502AS macrocell has a Reduced Power bit feature. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option. The ATF1502ASs also has an optional power down mode. In this mode, current drops to below 10 mA. When the power down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power down

option is selected in the design source file. When enabled, the device goes into power down when either PD1 or PD2 is high. In the power down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD pin is brought low. When the power down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. How- ever, the pin’s macrocell may still be used to generate bur- ied foldback and cascade logic signals. All Power-Down AC Characteristic parameters are com- puted from external input or I/O pins, with Reduced Power Bit turned on. For macrocells in reduced-power mode (Reduced power bit turned on), the reduced power adder, tRPA, must be added to the AC parameters, which include the data paths t LAD , tLAC , tIC, tACL , tACH and tSEXP . The ATF1502AS macrocell also has an option whereby the power can be reduced on a per macrocell basis. By enabling this power down option, macrocells that are not used in an application can be turned down thereby reduc- ing the overall power consumption of the device. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file. Design Software Support ATF1502AS designs are supported by several third party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats. Power Up Reset The ATF1502AS has a power-up reset option at two differ- ent voltage trip levels when the device is being powered down. Within the fitter, or during a conversion, if the “power-reset” option is turned “on” (which is the default option), the trip levels during power up or power down is at 2.8V. The user can change this default option from “on” to “off” (within the fitter or specify it as a switch during conver- sion). When this is done, the voltage trip level during power-down changes from 2.8V to 0.7V. This is to ensure a robust operating environment. The registers in the ATF1502AS are designed to reset dur- ing power up. At a point delayed slightly from V CC crossing Vrst, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. How- ever, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the fol- lowing conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin- high, and, 3. The clock must remain stable during T Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1502AS fuse patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains accessible. Programming ATF1502AS devices are In-System Programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for program and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow pro- gramming of the ATF1502AS via the PC. ISP is performed by using either a download cable, or a comparable board tester or a simple microprocessor interface. When using the ISP hardware or S/W to program the ATF1502AS devices, four I/0 pins must be reserved for the JTAG interface. However, the logic features the macrocells associated with these I/0 pins are still available to the design for burned logic functions. To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial Vector Format (SVF) files can be created by Atmel provided Software utilities. ATF1502AS devices can also be programmed using stan- dard 3rd party programmers. With 3rd party programmer the JTAG ISP port can be disabled thereby allowing 4 addi- tional I/O pins to be used for logic. Contact your local Atmel representatives or Atmel PLD applications for details. ISP Programming Protection The ATF1502AS has a special feature which locks the device and prevents the inputs and I/O from driving if the programming process is interrupted due to any reason. The inputs and I/O default to high-Z state during such a condi- tion. In addition, the pin keeper option preserves the previ- ous state of the input and I/0 PMS during programming. All ATF1502AS devices are initially shipped in the erased state thereby making them ready to use for ISP. Note: For more information refer to the “Designing for In-Sys- tem Programmability with Atmel CPLDs” application note.

The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1502AS. The boundary-scan technique involves the inclusion of a shift- register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component bound- aries can be controlled and observed using scan testing methods. Each input pin and I/O pin has its own boundary scan cell (BSC) to support boundary scan testing. The ATF1502AS does not include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power up. The five JTAG modes supported include: SAM- PLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502AS’s ISP can be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows ATF1502AS programming to be described and imple- mented using any one of the 3rd party development tools supporting this standard. The ATF1502AS has the option of using four JTAG-stan- dard I/O pins for boundary scan testing (BST) and in-sys- tem programming (ISP) purposes. The ATF1502AS is programmable through the four JTAG pins using the IEEE standard JTAG programming protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins. JTAG Boundary Scan Cell (BSC) Testing The ATF1502AS contains up to 32 I/O pins and 4 input pins, depending on the and package type selected. Each input pin and I/O pin has its own boundary scan cell (BSC) in order to support boundary scan testing as described in detail by IEEE Standard 1149.1. Typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the capture regis- ters. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are shown below. BSC Configuration for Input and I/O Pins (except JTAG TAP Pins) Note: The A TF1502AS has pull-up option on TMS and TDI pins. This feature is selected as a design option. DC and AC Operating Conditions Commercial Industrial Operating Temperature (Case) 0°C - 70°C- 4 0 °C - 85°C VCCINT or VCCIO (5V) Power Supply 5V ± 5% 5V ± 10%

Note: Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. Note: T ypical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pf. DC Characteristics Symbol Parameter Condition Min Typ Max Units IIL Input or I/O Low Leakage Current VIN = VCC -2 -10 µA IIH Input or I/O High Leakage Current 21 0 IOZ T ri-State Output Off-State Current VO = VCC or GND -40 40 µA ICC1 Power Supply Current, Stand-by VCC = Max VIN = 0, VCC Std Mode Com. 60 mA Ind. 75 mA “Z” Mode Com. 40 µA Ind. 40 µA ICC2 Power Supply Current, Power Down Mode VCC = Max VIN = 0, VCC “PD” Mode 1 mA ICC3 Clocked Power Supply Current VCC = Max VIN = 0, VCC “Z” Mode 2 mA/ MHz IOS Output Short Circuit Current VOUT = 0.5V -150 mA VCCIO Supply Voltage 5.0V Device Output Com. 4.75 5.25 V Ind. 4.5 5.5 V VCCIO Supply Voltage 3.3V Device Output 3.0 3.6 V VIL Input Low Voltage -0.3 0.8 V VIH Input High Voltage 2.0 VCCINT + 0.3 V VOL Output Low Voltage VIN = VIH or VIL VCCIO = MIN, IOL = 12 mA Com. 0.45 V Ind. VOH Output High Voltage VIN = VIH or VIL VCCIO = MIN, IOH = -4.0 mA 2.4 V Pin Capacitance Typ Max Units Conditions C IN 81 0 p F V IN = 0V; f = 1.0 MHz C I/O 81 0 p F V OUT = 0V; f = 1.0 MHz

Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V DC, which may under- shoot to -2.0V for pulses of less than 20 ns. Max- imum output pin voltage is V CC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. Voltage on Any Pin with (1) Voltage on Input Pins with Respect to Ground (1) Programming Voltage with (1) AC Characteristics Symbol Parameter -7 -10 -15 -20 -25 UnitsMin Max Min Max Min Max Min Max Min Max tPD1 Input or Feedback to Non-Registered Output 7.5 10 3 15 20 25 ns tPD2 I/O Input or Feedback to Non-Registered Feedback 79 3 1 2 1 6 2 5 n s tSU Global Clock Setup Time 6 7 11 16 20 ns tH Global Clock Hold Time 0 0 0 0 0 ns tFSU Global Clock Setup Time of Fast Input 3 3335n s tFH Global Clock Hold Time of Fast Input 0.5 0.5 1 1.5 2 MHz tCOP Global Clock to Output Delay 4.5 5 8 10 13 ns tCH Global Clock High Time 3 4 5 6 7 ns tCL Global Clock Low Time 3 4 5 6 7 ns tASU Array Clock Setup Time 3 3 4 4 5 ns tAH Array Clock Hold Time 2 3 4 5 6 ns tACOP Array Clock Output Delay 7.5 10 15 20 25 ns tACH Array Clock High Time 3 4 6 8 10 ns tACL Array Clock Low Time 3 4 6 8 10 ns tCNT Minimum Clock Global Period 8 10 13 17 22 ns fCNT Maximum Internal Global Clock Frequency 125 100 76.9 66 50 MHz tACNT Minimum Array Clock Period 8 10 13 17 22 ns fACNT Maximum Internal Array Clock Frequency 125 100 76.9 66 50 MHz

Note: See ordering information for valid part numbers. (continued) Timing Model FMAX Maximum Clock Frequency 166.7 125 100 83.3 60 MHz tIN Input Pad and Buffer Delay 0.5 0.5 2 2 2 ns tIO I/O Input Pad and Buffer Delay 0.5 0.5 2 2 2 ns tFIN Fast Input Delay 1 1 2 2 2 ns tSEXP Foldback T erm Delay 4 5 8 10 12 ns tPEXP Cascade Logic Delay 0.8 0.8 1 1 1.2 ns tLAD Logic Array Delay 3 5 6 7 8 ns tLAC Logic Control Delay 3 5 6 7 8 ns tIOE Internal Output Enable Delay 2 2 3 3 4 ns tOD1 Output Buffer and Pad Delay (Slow slew rate = OFF; V CCIO = 5V; CL = 35 pF) 21 . 5 4 5 6 n s tOD2 Output Buffer and Pad Delay (Slow slew rate = OFF; V CCIO = 3.3V; CL = 35 pF) 2.5 2.0 5 6 7 ns AC Characteristics (Continued) Symbol Parameter -7 -10 -15 -20 -25 UnitsMin Max Min Max Min Max Min Max Min Max

Notes: 1. See ordering information for valid part numbers. 2. The tRP A parameter must be added to the tLAD , tLAC ,tTIC, tACL , and tSEXP parameters for macrocells running in the reduced- power mode. Input Test Waveforms and Measurement Levels tR , tF = 1.5 ns typical Output AC Test Loads Note: *Numbers in parenthesis refer to 3.0V operating condi- tions (preliminary) AC Characteristics (Continued) Symbol Parameter -7 -10 -15 -20 -25 UnitsM i nM a xM i nM a xM i nM a xM i nM a xM i nM a x tZX1 Output Buffer Enable Delay (Slow slew rate = OFF; V CCIO = 5.0V; CL = 35 pF) 4.0 5.0 7 9 10 ns tZX2 Output Buffer Enable Delay (Slow slew rate = OFF; V CCIO = 3.3V; CL = 35 pF) 4.5 5.5 7 9 10 ns tZX3 Output Buffer Enable Delay (Slow slew rate = ON; V CCIO = 5.0V/3.3V; CL = 35 pF) 9 9 10 11 12 ns tXZ Output Buffer Disable Delay (CL = 5 pF) 45678 n s tSU Register Setup Time 3 3 4 5 6 ns tH Register Hold Time 2 3 4 5 6 ns tFSU Register Setup Time of Fast Input 3 3 2 2 3 ns tFH Register Hold Time of Fast Input 0.5 0.5 2 2 2.5 ns tRD Register Delay 1 2 1 2 2 ns tCOMB Combinatorial Delay 1 2 1 2 2 ns tIC A r r a y C l o c k D e l a y 35678 n s tEN Register Enable Time 3 5 6 7 8 ns tGLOB Global Control Delay 1 1 1 1 1 ns tPRE R e g i s t e r P r e s e t T i m e 23456 n s tCLR Register Clear Time 2 3 4 5 6 ns tUIM S w i t c h M a t r i x D e l a y 11222 n s tRPA Reduced-Power Adder(2) 10 11 13 14 15 ns (3.0V)* (703 )* (8060 )*

The ATF1502AS includes an optional pin controlled power down feature.When this mode is enabled, the PD pin acts as the power down pin. When the PD pin is high, the device supply current is reduced to less than 3 mA. During power down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs which were in a Hi-Z state at the onset will remain at Hi-Z. During power down, all input signals except the power down pin are blocked. Input and I/O hold latches remain active to insure that pins do not float to indeterminate levels, further reducing system power. The power down pin feature is enabled in the logic design file. Designs using the power down pin may not use the PD pin logic array input. However, all other PD pin mac- rocell resources may still be used, including the buried feedback and foldback product term array inputs. Notes: 1. For slow slew outputs, add tSSO . 2. Pin or Product T erm. Power Down AC Characteristics(1)(2) Symbol Parameter -7 -10 -15 -20 -25 UnitsM i nM a xM i nM a xM i nM a xM i nM a xM i nM a x tIVDH Valid I, I/O Before PD High 7 10 15 20 25 ns tGVDH Valid OE(2) Before PD High 7 10 15 20 25 ns tCVDH Valid Clock(2) Before PD High 7 10 15 20 25 ns tDHIX I, I/O Don’t Care After PD High 12 15 25 30 35 ns tDHGX OE (2) Don’t Care After PD High 12 15 25 30 35 ns tDHCX Clock(2) Don’t Care After PD High 12 15 25 30 35 ns tDLIV PD Low to Valid I, I/O 1 1 1 1 1 µs tDLGV PD Low to Valid OE (Pin or T erm) 1 1 1 1 1 µs tDLCV PD Low to Valid Clock (Pin or T erm) 1 1 1 1 1 µs tDLOV PD Low to Valid Output 1 1 1 1 1 µs

BSC for I/O Pins and Macrocells DQ TDICLOCK TDO Pin Pin

The ATF1502AS also supports the growing need in the industry to support the new Peripheral Component Inter- connect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current driv- ers which are much larger than the traditional TTL drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required by the PCI interface. The ATF1502AS allows this without contributing to system noise while delivering low output to output skew. Having a programmable high drive option is also possible without increasing output delay or pin capacitance. The PCI electri- cal characteristics appear on the next page. PCI Voltage-to-Current Curves for +5V Signaling in Pull-Up Mode PCI Voltage-to-Current Curves for +5V Signaling in Pull-Down Mode 2.4 VCC 1.4 -2 -44 -178Current (mA) AC drive point DC drive point Voltage Pull Up Test Point 2.2 VCC 0.55 3.6 95 380Current (mA) AC drive point DC drive point Voltage Pull Down Test Point

Note: Leakage Current is with Pin-Keeper off. PCI DC Characteristics (Preliminary) Symbol Parameter Conditions Min Max Units VCC Supply Voltage 4.75 5.25 V VIH Input High Voltage 2.0 V CC + 0.5 V VIL Input Low Voltage -0.5 0.8 V IIH Input High Leakage Current V IN = 2.7V 70 µA IIL Input Low Leakage Current V IN = 0.5V -70 µA VOH Output High Voltage I OUT = -2 mA 2.4 V VOL Output Low Voltage I OUT = 3 mA, 6 mA 0.55 V C IN Input Pin Capacitance 10 pF C CLK CLK Pin Capacitance 12 pF C IDSEL IDSEL Pin Capacitance 8 pF LPIN Pin Inductance 20 nH PCI AC Characteristics (Preliminary) Symbol Parameter Conditions Min Max Units IOH(AC) Switching 0 < V OUT ≤ 1.4 -44 mA Current High 1.4 < V OUT < 2.4 -44+(VOUT - 1.4) /0.024 mA 3.1 < VOUT < VCC Equation A mA (T est High) V OUT = 3.1V -142 µA IOL(AC) Switching V OUT > 2.2V 95 mA Current Low 2.2 > V OUT > 0 V OUT /0.023 mA 0.1 > VOUT > 0 Equation B mA (T est Point) V OUT = 0.71 206 mA ICL Low Clamp Current -5 < V IN ≤ -1 -25+(VIN + 1) /0.015 mA SLEW R Output Rise Slew Rate 0.4V to 2.4V load 1 5 V/ns SLEW F Output Fall Slew Rate 2.4V to 0.4V load 1 5 V/ns

OE (1, 2) Global OE Pins GCLR Global Clear Pin GCLK (1, 2, 3) Global Clock Pins PD (1, 2) Power down pins TDI, TMS, TCK, TDO JTAG pins used for Boundary Scan Testing or In-System Programming GND Ground Pins V CCINT VCC pins for the device (+5V - Internal) VCCIO VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os) ATF1502AS Dedicated Pinouts Dedicated Pin 44-Pin TQFP 44-Pin J-Lead 44-Pin PQFP INPUT/OE2/GCLK2 40 2 40 INPUT/GCLR 39 1 39 INPUT/OE1 38 44 38 INPUT/GCLK1 37 43 37 I/O /GCLK3 35 41 35 I/O / PD (1,2) 5, 19 11, 25 5, 19 I/O / TDI (JT AG) 1 7 1 I/O / TMS (JT AG) 7 13 7 I/O / TCK (JT AG) 26 32 26 I/O / TDO (JT AG) 32 38 32 GND 4, 16, 24, 36 10, 22, 30, 42 4, 16, 24, 36 V CCINT 9, 17, 29, 41 3, 15, 23, 35 9, 17, 29, 41 VCCIO --- N / C --- # of Signal Pins 36 36 36 # User I/O Pins 32 32 32

MC PLC 44-Pin PLCC 44-Pin TQFP 44-Pin PQFP 1A 4 4 24 2 2A 5 4 34 3 3A / PD1 64 1 4 1 4A 7 1 1 5A 8 2 2 6A 9 3 3 7A1 1 5 5 8/TDI A1 2 6 6 9A1 3 7 7

10 A 14 8 8

Ordering Information

(ns) tCO1 (ns) fMAX (MHz) Ordering Code Package Operation Range 7.5 4.5 166.7 A TF1502AS-7 AC44 A TF1502AS-7 JC44 A TF1502AS-7 QC44 44A 44J 44Q Commercial (0°C to 70°C) 10 5 125 A TF1502AS-10 AC44 A TF1502AS-10 JC44 A TF1502AS-10 QC44 44A 44J 44Q Commercial (0°C to 70°C) 10 5 125 A TF1502AS-10 AI44 A TF1502AS-10 JI44 A TF1502AS-10 QI44 44A 44J 44Q Industrial (-40°C to +85°C) 15 8 100 A TF1502AS-15 AC44 A TF1502AS-15 JC44 A TF1502AS-15 QC44 44A 44J 44Q Commercial (0°C to 70°C) 15 8 100 A TF1502AS-15 AI44 A TF1502AS-15 JI44 A TF1502AS-15 QI44 44A 44J 44Q Industrial (-40°C to +85°C) 20 12 83.3 A TF1502ASL-20 AC44 A TF1502ASL-20 JC44 A TF1502ASL-20 QC44 44A 44J 44Q Commercial (0°C to 70°C) 20 12 83.3 A TF1502ASL-20 AI44 A TF1502ASL-20 JI44 A TF1502ASL-20 QI44 44A 44J 44Q Industrial (-40°C to +85°C) 25 15 70 ATF1502ASL-25 AC44 A TF1502ASL-25 JC84 A TF1502ASL-25 QC44 44A 44J 44Q Commercial (0°C to 70°C) 25 15 70 A TF1502ASL-25 AI44 A TF1502ASL-25 JI84 A TF1502ASL-25 QI44 44A 44J 44Q Industrial (-40°C to +85°C) Package Type 44A 44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 44Q 44-Lead, Plastic Gull Wing Quad Flatpack (PQFP)

• Controlling dimension: millimeters .045(1.14) X 45° PIN NO. 1 IDENTIFY .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) REF SQ .032(.813) .026(.660) .050(1.27) TYP .656(16.7) .650(16.5) .695(17.7) .685(17.4)SQ SQ * Controlling dimension: millimeters 44A , 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AC 44Q, 44 Lead, Plastic Gull Wing Quad Flat Package (PQFP) Dimensions in Inches and (Millimeters)