ATF1500ABV ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Operates Between 2.7V to 5.5V
- High Density, High-Performance Electrically Erasable Complex Programmable Logic Device – 44-Pin, 32 I/O CPLD – 12 ns Maximum Pin-to-Pin Delay – Registered Operation Up To 90.9 MHz – Fully Connected Input and Feedback Logic Array
- Flexible Logic Macrocell – D/T/Latch Configurable Flip Flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate
- Advanced Power Management Features – Automatic 3 mA Stand-By (ATF1500ABVL) – Pin-Controlled 5 µµµµA Stand-By Mode (Typical) – Programmable Pin-Keeper Inputs and I/Os
- Available in Commercial and Industrial Temperature Ranges
- Available in 44-Pin PLCC and TQFP Packages
- Advanced Flash Technology – 100% Tested – Completely Reprogrammable – 100 Program/Erase Cycles – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-Up Immunity
- Supported By Popular 3rd Party Tools
- Security Fuse Feature
Description
The ATF1500ABV is a high performance, high density Complex PLD. Built on an advanced Flash technology, it has maximum pin to pin delays of 12 ns and supports sequential logic operation at speeds up to 90.9 MHz. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic PLDs. The ATF1500ABV’s global input and feedback architecture simplifies logic placement and eliminates pinout changes due to design changes. High- Performance EE PLD ATF1500ABV ATF1500ABVL ATF1500ABV/L Rev. 0723D–6/98 (continued)
Functional Logic Diagram(1) Note: 1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.
The ATF1500ABV has 32 bi-directional I/O pins and 4 ded- icated input pins. Each dedicated input pin can also serve as a global control signal: register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 32 logic macrocells generates a buried feed- back, which goes to the global bus. Each input and I/O pin also feeds into the global bus. Because of this global bus- sing, each of these signals is always available to all 32 macrocells in the device. Each macrocell also generates a foldback logic term, which goes to a regional bus. All signals within a regional bus are connected to all 16 macrocells within the region. Cascade logic between macrocells in the ATF1500ABV allows fast, efficient generation of complex logic functions. The ATF1500ABV contains 4 such logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms. Bus Friendly Pin-Keeper Input and I/O’S All Input and I/O pins on the ATF1500ABV have program- mable “data keeper” circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused Input and I/O lines from floating to intermediate voltage levels, which cause unnec- essary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Pin-keeper circuits can be disabled. Programming is con- trolled in the logic design file. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os. Speed/Power Management The ATF1500ABV has several built-in speed and power management features. The ATF1500ABV contains circuitry that automatically puts the device into a low power stand- by mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides a proportional power savings for most applications running at system speeds below 10 MHz. All ATF1500ABVs also have an optional pin-controlled power down mode. In this mode, current drops to below 10 µA. When the power down option is selected, the PD pin is used to power down the part. The power down option is selected in the design source file. When enabled, the device goes into power down when the PD pin is high. In the power down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD is brought low. When the power down feature is enabled, the PD cannot be used as a logic input or output. However, the PD pin's macrocell may still be used to generate buried foldback and cascade logic sig- nals. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file. Design Software Support ATF1500ABV designs are supported by several 3rd party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats. Input Diagram 100K VCC ESD PROTECTION CIRCUIT INPUT PROGRAMMABLE OPTION
The ATF1500ABV macrocell is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and prod- uct term select multiplexer; OR/XOR/CASCADE logic; a flip flop; output select and enable; and logic array inputs. Product Terms and Select Mux Each ATF1500ABV macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is deter- mined by the design compiler, which selects the optimum macrocell configuration. OR/XOR/CASCADE Logic The ATF1500ABV macrocell's OR/XOR/CASCADE logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a five input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay. The macrocell's XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinato- rial outputs, the fixed level input allows output polarity selection. For registered functions, the fixed levels allow De Morgan minimization of the product terms. The XOR gate is also used to emulate JK type flip flops. Flip Flop The ATF1500ABV’s flip flop has very flexible data and con- trol functions. The data input can come from either the XOR gate or from a separate product term. Selecting the sepa- rate product term allows creation of a buried registered feedback within a combinatorial output macrocell. In addition to D, T, JK and SR operation, the flip flop can also be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched when the clock is low. The clock itself can be either the global CLK pin or an indi- vidual product term. The flip flop changes state on the clock's rising edge. When the CLK pin is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip flop's asynchronous reset signal (AR) can be either the pin global clear (GCLR), a product term, or always off. AR can also be a logic OR of GCLR with a product term. The asynchronous preset (AP) can be a product term or always off. Output Select and Enable The ATF1500ABV macrocell output can be selected as registered or combinatorial. When the output is registered, the same registered signal is fed back internally to the glo- bal bus. When the output is combinatorial, the buried feed- back can be either the same combinatorial signal or it can be the register output if the separate product term is cho- sen as the flip flop input. The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be permanently enabled for simple output operation. Buffers can also be permanently disabled to allow use of the pin as an input. In this configu- ration all the macrocell resources are still available, includ- ing the buried feedback, expander and CASCADE logic. The output enable for each macrocell can also be selected as either of the two OE pins or as an individual product term. Global/Regional Busses The global bus contains all Input and I/O pin signals as well as the buried feedback signal from all 32 macrocells. Together with the complement of each signal, this provides a 68-bit bus as input to every product term. Having the entire global bus available to each macrocell eliminates any potential routing problems. With this architecture designs can be modified without requiring pinout changes. Each macrocell also generates a foldback product term. This signal goes to the regional bus, and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell's product terms. The 16 foldback terms in each region allow generation of high fan-in sum terms (up to 21 product terms) with a small additional delay.
Note: 1. All ICC parameters measured with outputs open, and a 16 bit loadable, up/down counter programmed into each region. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V dc, which may under- shoot to -2.0V for pulses of less than 20 ns. Max- imum out put pin voltage is V CC + 0.75V dc, which may overshoot to 5.25V for pulses of less than 20 ns. Voltage on Any Pin with (1) Voltage on Input Pins with Respect to Ground (1) Programming Voltage with (1) DC and AC Operating Conditions Commercial Industrial Operating T emperature (Case) 0°C - 70°C -40°C - 85°C V CC Power Supply 2.7V - 5.5V 2.7V - 5.5V DC Characteristics Symbol Parameter Condition Min Typ Max Units IIL Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL(max) -10 µA IIH Input or I/O High Leakage Current VIH,min < VIN ≤ VCC 10 µA ICC1 (1) Power Supply Current, Standby VCC = MAX, VIN = 0, VCC A TF1500ABV Com. 35 mA Ind. 40 mA A TF1500ABVL Com. 3 mA Ind. 5 mA ICC2 Power Supply Current, Power Down Mode VCC = MAX, VIN = 0, VCC 2m A IOS Output Short Circuit Current VOUT = 0.5V -130 mA VIL Input Low Voltage VCC , min < VCC < VCC , max -0.5 0.8 V VIH Input High Voltage 2.0 V CC + 1 V VOL Output Low Voltage V CC = MIN I OL = 4 mA 0.45 V VOH Output High Voltage V CC = MIN I OH = -0.1 mA V CC - .2 V
- For slow slew outputs, add tSSO . Register AC Characteristics, Input Pin Clock(1) Symbol Parameter 2.7-volt Adder -12 -15 UnitsM i nM a xM i nM a x tCOS (2) Clock to Output . 5 2728 n s tCFS Clock to Feedback 03 3 n s tSIS I, I/O Setup Time 11 0 1 1 n s tSFS Feedback Setup Time 11 0 1 1 n s tHS Input, I/O, Feedback Hold Time 00 0 n s tPS Clock Period 11 3 1 4 n s tWS Clock Width .5 6.5 7 ns FMAXS External Feedback 1/(tSIS + tCOS ) -5 58.8 52.6 MHz Internal Feedback 1/(tSFS + tCFS ) -5.5 76.9 71.4 MHz No Feedback 1/(tPS ) -5.5 76.9 71.4 MHz tRPRS Reset Pin Recovery Time 13 4 n s tRTRS Reset T erm Recovery Time 11 0 1 2 n s = Preliminary Information
- For slow slew outputs, add tSSO . 2. For slow slew outputs, add tSSO . Register AC Characteristics, Product Term Clock(1) Symbol Parameter 2.7-volt Adder -12 -15 UnitsMin Max Min Max tCOA (2) Clock to Output 21 2 1 5 n s tCFA Clock to Feedback 1 8 10 ns tSIA I, I/O Setup Time 04 4 n s tSFA Feedback Setup Time 04 4 n s tHA Input, I/O, Feedback Hold Time 04 4 n s tPA Clock Period 11 2 1 4 n s tWA Clock Width .5 6 7 ns FMAXA External Feedback 1/(tSIA + tCOA ) -7 62.5 52.6 MHz Internal Feedback 1/(tSFA + tCFA ) -6.4 83.3 71.4 MHz No Feedback 1/(tPA) -6.4 83.3 71.4 MHz tRPRA Reset Pin Recovery Time 00 0 n s tRTRA Reset/Preset T erm Recovery Time 06 6 n s AC Characteristic Symbol Parameter 2.7-volt Adder -12 -15 UnitsMin Max Min Max tPD (2) I, I/O or FB to Non-Registered Output 23 1 2 3 1 5 n s tPD2 I, I/O to Feedback 18 9 n s tPD3 (2) Feedback to Non-Registered Output 23 1 2 3 1 5 n s tPD4 Feedback to Feedback 18 9 n s tEA (2) OE T erm to Output Enable 13 1 2 3 1 5 n s tER OE T erm to Output Disable 12 1 2 2 1 5 n s tPZX (2) OE Pin to Output Enable 12 8 2 9 n s tPXZ OE Pin to Output Disable 1 1 . 581 . 59 n s tPF Preset T o Feedback 19 1 2 n s tPO (2) Preset to Registered Output 21 4 2 0 n s tRPF Reset Pin to Feedback 13 5 n s tRPO (2) Reset Pin to Registered Output 18 1 1 n s tRTF Reset T erm to Feedback 19 1 2 n s tRTO (2) Reset T erm to Registered Output 21 4 2 0 n s tCAS Cascade Logic Delay 01 1 n s tSSO Slow Slew Output Adder 03 4 n s tFLD Foldback T erm Delay 17 8 n s = Preliminary Information
- For slow slew outputs, add tSSO . 3. Pin or Product T erm. Input Test Waveforms and Measurement Levels Output Test Load Note: 1. T ypical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power Down AC Characteristics(1) Symbol Parameter 2.7-volt Adder -12 -15 UnitsM i nM a xM i nM a x tIVDH Valid I, I/O Before PD High 11 2 1 5 n s tGVDH Valid OE(3) Before PD High 11 2 1 5 n s tCVDH Valid Clock(3) Before PD High 11 2 1 5 n s tDHIX Input Don't Care After PD High 12 2 2 5 n s tDHGX OE Don't Care After PD High 12 2 2 5 n s tDHCX Clock Don't Care After PD High 12 2 2 5 n s tDLIV PD Low to Valid I, I/O 01 1 µs tDLGV PD Low to Valid OE(3) 01 1 µs tDLCV PD Low to Valid Clock(3) 01 1 µs tDLOV (1) PD Low to Valid Output 01 1 µs Pin Capacitance (f = 1 MHz, T = 25°C)(1) Typ Max Units Conditions C IN 4.5 5.5 pF V IN = 0V C OUT 3.5 4.5 pF V OUT = 0V = Preliminary Information
The ATF1500ABV’s registers are designed to reset during power up. At a point delayed slightly from VCC crossing VRST , all registers will be reset to the low state. As a result, the registered output state will always be low on power-up. This feature is critical for state machine initialization. How- ever, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the fol- lowing conditions are required: 1. The VCC rise must be monotonic, from below .7 volts. 2. Signals from which clocks are derived must remain stable during TPR . 3. After TPR occurs, all input and feedback setup times must be met before driving the clock signal high. Power Down Mode The ATF1500ABV includes an optional pin controlled power down feature. When this mode is enabled, the PD pin acts as the power down pin. When the PD pin is high, the device supply current is reduced to less than 10 µA. During power down, all output data and internal logic states are latched and held. Therefore, all registered and combi- natorial output data remain valid. Any outputs which were in a HI-Z state at the onset of power down will remain at HI- Z. During power down, all input signals except the power down pin are blocked. Input and I/O hold latches remain active to insure that pins do not float to indeterminate lev- els, further reducing system power. The power down pin feature is enabled in the logic design file. Designs using the power down pin may not use the PD pin logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. Register Preload The ATF1500ABV’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with preload vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically when vectors are run by any approved programmers. The preload mode is enabled by raising an input pin to a high voltage level. Contact Atmel PLD Applications for PRE- LOAD pin assignments, timing and voltage requirements. Output Slew Rate Control Each ATF1500ABV macrocell contains a configuration bit for each I/O to control its output slew rate. This allows selected data paths to operate at maximum throughput while reducing system noise from outputs that are not speed-critical. Outputs default to slow edges, and may be individually set to fast in the design file. Output transition times for outputs configured as “slow” have a t SSO delay adder. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1500ABV fuse patterns. Once programmed, fuse verify and preload are prohibited. However, the 160-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. Parameter Description Typ Max Units TPR Power-Up Reset Time 21 0 µs VRST Power-Up Reset Voltage 2.2 2.7 V
Ordering Information
(ns) tCOS (ns) FMAXS (MHz) Ordering Code Package Operation Range 12 6 62.5 A TF1500ABV-12AC A TF1500ABV-12JC 44A 44J Commercial (0°C to 70°C) 15 8 52.6 A TF1500ABV-15AC A TF1500ABV-15JC 44A 44J Commercial (0°C to 70°C) A TF1500ABV-15AI A TF1500ABV-15JI 44A 44J Industrial (-40°C to 85°C)
25 TBD TBD A TF1500ABVL-25AC
(0°C to 70°C) Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC)
*Controlling dimension: millimeters .045(1.14) X 45° PIN NO. 1 IDENTIFY .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) REF SQ .032(.813) .026(.660) .050(1.27) TYP .656(16.7) .650(16.5) .695(17.7) .685(17.4)SQ SQ 44A , 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) © Atmel Corporation 1998. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s T erms and Conditions located on the Company’s website. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel Headquarters, 2325 Orchard Parkway, San Jose, CA 95131, TEL (408) 441-0311, FAX (408) 487-2600 Atmel Colorado Springs, 1150 E. Cheyenne Mtn. Blvd., Colorado Springs, CO 80906, TEL (719) 576-3300, FAX (719) 540-1759 Atmel Rousset, Zone Industrielle, 13106 Rousset Cedex, France, TEL (33) 4 42 53 60 00, FAX (33) 4 42 53 60 01 T erms and product names in this document may be trademarks of others. Printed on recycled paper. 0723D–6/98/XM