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Document overview
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Technical content
Features
Lead-free Option Available Low Noise Figure Excellent Uniformity in Product Specifi cations Low Cost Surface Mount Small Plastic Package SOT-343 (4 lead SC-70) Tape-and-Reel Packaging Option Available Specifi cations 1.9 GHz; 2 V, 10 mA (Typ.) 0.4 dB Noise Figure 16 dB Associated Gain 12.0 dBm Output Power at 1 dB Gain Compression 22.0 dBm Output 3rd Order Intercept
Applications
Low Noise Amplifi er for Cellular/PCS Handsets LNA for WLAN, WLL/RLL, LEO, and MMDS General Purpose Discrete PHEMT for Other Ultra Low Noise Applications
Description
Avago Technologies’s ATF-38143 is a high dynamic range, low noise, PHEMT housed in a 4-lead SC-70 (SOT- 343) surface mount plastic package. Based on its featured performance, ATF-38143 is suitable for applications in cellular and PCS handsets, LEO systems, MMDS, and other systems requiring super low noise fi gure with good intercept in the 450 MHz to 10 GHz frequency range. Surface Mount Package SOT-343 Pin Connections and Package Marking SOURCE DRAIN GATE SOURCE 8Px Note: Top View. Package marking provides orientation and identifi cation. “8P” = Device code “x” = Date code character. A new character is assigned for each month, year. Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) ESD Human Body Model (Class 1) Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control.
- Operation of this device above any one of
- Source lead temperature is 25°C. Derate
- Thermal resistance measured using 150°C
Liquid Crystal Measurement method. Figure 2. OIP3 @ 2 GHz, 2 V, 10 mA.
6 Wafers
Figure 3. NF @ 2 GHz, 2 V, 10 mA. Figure 4. Gain @ 2 GHz, 2 V, 10 mA. anywhere within the upper and lower spec limits. Figure 1. Typical I-V Curves. (VGS = -0.2 V per step)
Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, and OIP3 measurements. This circuit represents a trade-
50 Ohm
Symbol Parameters and Test Conditions Units Min. Typ. [2] Max.
- Guaranteed at wafer probe level.
- Typical value determined from a sample size of 450 parts from 6 wafers.
- Measurements obtained using production test board described in Figure 5.
Figure 18. MSG/MAG and |S21|2 vs. Frequency at 2 V, 5 mA.
- F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATN NP5 test system. From these
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end
diameter via holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point.
Figure 19. MSG/MAG and |S21|2 vs. Frequency at 2 V, 10 mA.
- F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATN NP5 test system. From these
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end
diameter via holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point.
Figure 20. MSG/MAG and |S21|2 vs. Frequency at 2 V, 20 mA.
- F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATN NP5 test system. From these
measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end
diameter via holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point.
Noise Parameter Applications Information Fmin values at 2 GHz and higher are based on measurements while the F mins below 2 GHz have been extrapolated. The F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATN NP5 test system. From these measurements, a true F min is calculated. F min represents the true minimum noise fi gure of the device when the device is presented with an impedance matching network that transforms the source impedance, typically 50Ω, to an impedance represented by the refl ection coeffi cient o. The designer must design a matching network that will present o to the device with minimal associated circuit losses. The noise fi gure of the completed amplifi er is equal to the noise fi gure of the device plus the losses of the matching network preceding the device. The noise fi gure of the device is equal to F min only when the device is presented with o. If the refl ection coeffi cient of the matching network is other than o, then the noise fi gure of the device will be greater than Fmin based on the following equation. NF = Fmin + 4 Rn |s – o | 2 Where R n /Zo is the normalized noise resistance, o is the optimum refl ection coeffi cient required to produce Fmin and s is the refl ection coeffi cient of the source impedance actually presented to the device. The losses of the matching networks are non-zero and they will also add to the noise fi gure of the device creating a higher amplifi er noise fi gure. The losses of the matching networks are related to the Q of the components and associated printed circuit board loss. o is typically fairly low at higher frequencies and increases as frequency is lowered. Larger gate width devices will typically have a lower o as compared to narrower gate width devices. Typically for FETs, the higher o usually infers that an impedance much higher than 50Ω is required for the device to produce F min. At VHF frequencies and even lower L Band frequencies, the required impedance can be in the vicinity of several thousand ohms. Matching to such a high impedance requires very hi-Q components in order to minimize circuit losses. As an example at 900 MHz, when air-wound coils (Q > 100) are used for matching networks, the loss can still be up to 0.25 dB which will add directly to the noise fi gure of the device. Using muilti-layer molded inductors with Qs in the 30 to 50 range results in additional loss over the air-wound coil. Losses as high as 0.5 dB or greater add to the typical 0.15 dB F min of the device creating an amplifi er noise fi gure of nearly 0.65 dB. A discussion concerning calculated and measured circuit losses and their eff ect on amplifi er noise fi gure is covered in Avago Application 1085.
ATF-38143 SC70 4 Lead, High Frequency Nonlinear Model NFET=yes PFET=no Vto=–0.75 Beta=0.3 Lambda=0.07 Alpha=4 B=0.8 Tnom=27 Idstc= Vbi=0.7 Tau= Betatce= Delta1= Delta2= Gscap=3 Cgs=0.997 pF Gdcap=3 Cgd=0.176 pF Rgd=0.195 Tqm= Vmax= Fc= Rd=0.084 Rg=0.264 Rs=0.054 Ld=0.0014 nH Lg-0.0883 nH Ls=0.001 nH Cds=0.0911 pF Crf=0.0936 Rc=137 Gsfwd=1 Gsrev=0 Gdfwd=1 Gdrev=0 Vjr=1 Is=1 nA Ir=1 nA Imax=0.1 Xti= Eg= Vbr= Vtotc= Rin= Taumd1=no Fnc=1E6 R=0.17 C=0.2 P=1 wVgfwd= wBvgs= wBvgd= wBvds= wldsmax= wPmax= All Params= Statz Model MESFETM1 GATE SOURCE Port G Num=1 Port Num=2 SOURCE DRAIN Port Num=4 Port D Num=3 L L=0.2 nH R=0.001 C C=0.11 pF L C=0.6 nH R=0.001MSub TLINP TL4 Z=Z1 Ohm L=15 mil K=1 A=0.000 F=1 GHz TanD=0.001 TLINP TL10 Z=Z1 Ohm L=15 mil K=1 A=0.000 F=1 GHz TanD=0.001 VIA2 D=20 mil H=25.0 mil T=0.15 mil Rho=1.0 W=40 mil VIA2 D=20.0 mil H=25.0 mil T=0.15 mil Rho=1.0 W=40.0 mil TLINP TL3 Z=Z2 Ohm L=25 mil K=K A=0.000 F=1 GHz TanD=0.001 TLINP TL9 Z=Z2 Ohm L=10.0 mil K=K A=0.000 F=1 GHz TanD=0.001 VAR VAR1 K=5 Z2=85 Z1=30 Var Ean TLINP TL1 Z=Z2/2 Ohm L=20 0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL2 Z=Z2/2 Ohm L=20 0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL8 Z=Z1 Ohm L=15 mil K=1 A=0.0000 F=1 GHz TanD=0.001 TLINP TL7 Z=Z2/2 Ohm L=5.0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL5 Z=Z2 Ohm L=26.0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL6 Z=Z1 Ohm L=15 mil K=1 A=0.0000 F=1 GHz TanD=0.001 VIA2 D=20.0 mil H=25.0 mil T=0.15 mil Rho=1.0 W=40.0 mil VIA2 D=20.0 mil H=25.0 mil T=0.15 mil Rho=1.0 W=40.0 mil L L=0.6 nH R=0.001 L L=0.2 nH R=0.001 GaAsFET FET1 Model= MESFETN1 Mode= nonlinear MSUB MSub1 H=25.0 mil Er=9.6 Mur=1 Cond=1.0E+50 Hu=3.9e+0.34 mil T=0.15 mil TanD=0 Rough=0 mil The vias are not part of the model as such. They are only included to account for the source vias in the test fi xture.
Part Number Ordering Information No. of Part Number Devices Container ATF-38143-TR1G 3000 7” Reel ATF-38143-TR2G 10000 13” Reel ATF-38143-BLKG 100 antisatic bag HE D A1b E 1.30 (.051) BSC 1.15 (.045) BSC CL A DIMENSIONS (mm) MIN. 1.15 1.85 1.80 0.80 0.80 0.00 0.15 0.55 0.10 0.10 MAX. 1.35 2.25 2.40 1.10 1.00 0.10 0.40 0.70 0.20 0.46 SYMBOL E D HE A b c L NOTES: 1. All dimensions are in mm. 2. Dimensions are inclusive of plating. 3. Dimensions are exclusive of mold flash & metal burr. 4. All specifications comply to EIAJ SC70. 5. Die is facing up for mold and facing down for trim/form, ie: reverse trim/form. 6. Package surface to be mirror finish. 1.30 (0.051) 0.60 (0.024) 0.9 (0.035) Dimensions in mm (inches) 1.15 (0.045) 2.00 (0.079) 1.00 (0.039) Recommended PCB Pad Layout for Avago’ s SC70 4L/SOT-343 Products
Tape Dimensions for Outline 4T P F W C D E 10° MAX. t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) 10° MAX. DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A P 2.40 ± 0.10 2.40 ± 0.10 1.20 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.094 ± 0.004 0.094 ± 0.004 0.047 ± 0.004 0.157 ± 0.004 0.039 + 0.010 CAVITY DIAMETER PITCH POSITION D P E 1.55 ± 0.10 4.00 ± 0.10 1.75 ± 0.10 0.061 + 0.002 0.157 ± 0.004 0.069 ± 0.004 PERFORATION WIDTH THICKNESS W 8.00 + 0.30 - 0.10 0.254 ± 0.02 0.315 + 0.012 0.0100 ± 0.0008 CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) F P 3.50 ± 0.05 2.00 ± 0.05 0.138 ± 0.002 0.079 ± 0.002 DISTANCE WIDTH TAPE THICKNESS C Tt 5.40 ± 0.10 0.062 ± 0.001 0.205 + 0.004 0.0025 ± 0.0004 COVER TAPE For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-3745EN AV02-1443EN - June 8, 2012 Device Orientation USER FEED DIRECTION COVER TAPE CARRIER TAPE REEL END VIEW 8 mm 4 mm TOP VIEW 8Px 8Px 8Px 8Px