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Document overview
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Technical content
Features
Lead-free Option Available Low Noise Figure Excellent Uniformity in Product Specifi cations 800 micron Gate Width Low Cost Surface Mount Small Plastic Package SOT-343 (4 lead SC-70) Tape-and-Reel Packaging Option Available Specifi cations 1.9 GHz; 4V, 60 mA (Typ.) 0.5 dB Noise Figure 17.5 dB Associated Gain 20 dBm Output Power at 1 dB Gain Compression 31.5 dBm Output 3 rd Order Intercept
Applications
Tower Mounted Amplifi er and Low Noise Amplifi er for GSM/TDMA/CDMA Base Stations LNA for Wireless LAN, WLL/RLL and MMDS General Purpose Discrete PHEMT for other Ultra Low Noise Applications Surface Mount Package - SOT-343
Description
Avago’s ATF-34143 is a high dynamic range, low noise PHEMT housed in a 4-lead SC-70 (SOT-343) surface mount plastic package. Based on its featured performance, ATF-34143 is ideal for the fi rst stage of base station LNA due to the excellent combination of low noise fi gure and high linearity [1]. The device is also suitable for applications in Wireless LAN, WLL/RLL, MMDS, and other systems requiring super low noise fi gure with good intercept in the 450 MHz to 10 GHz frequency range. Note: 1. From the same PHEMT FET family, the larger geometry ATF-33143 may also be considered either for the higher linearity performance or easier circuit design for stability in the lower frequency bands (800– 900 MHz).Pin Connections and Package Marking Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) ESD Human Body Model (Class 0) Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control. Note: Top View. Package marking provides orientation and identifi cation. “4P” = Device code “x” = Date code character. A new character is assigned for each month, year. GATE 4PxSOURCE DRAIN SOURCE
- Operation of this device above any one of
- Assumes DC quiescent conditions.
- Source lead temperature is 25°C. Derate
- Thermal resistance measured using 150°C
Liquid Crystal Measurement method.
- Under large signal conditions, V GS may
Figure 1. Typical/Pulsed I-V Curves[6]. Figure 2. OIP3 @ 2 GHz, 4†V, 60 mA.
9 Wafers
Figure 3. NF @ 2 GHz, 4†V, 60 mA. Figure 4. Gain @ 2 GHz, 4†V, 60 mA.
- Distribution data sample size is 450 samples taken from 9 diff erent wafers. Future wafers allocated to this product may have nominal values
anywhere within the upper and lower spec limits.
- Measurements made on production test board. This circuit represents a trade-off between an optimal noise match and a realizeable match based
on production test requirements. Circuit losses have been de-embedded from actual measurements.
TA = 25°C, RF parameters measured in a test circuit for a typical device Symbol Parameters and Test Conditions Units Min. Typ. [2] Max. I dss [1] Saturated Drain Current V DS = 1.5 V, VGS = 0 V mA 90 118 145 V P [1] Pinchoff Voltage V DS = 1.5 V, IDS = 10% of Idss V -0.65 -0.5 -0.35 I d Quiescent Bias Current V GS = -0.34 V, VDS = 4 V mA — 60 — g m[1] Transconductance V DS = 1.5 V, gm = Idss /VP mmho 180 230 — I GDO Gate to Drain Leakage Current V GD = 5 V μA 500 I gss Gate Leakage Current V GD = VGS = -4 V μA — 30 300 NF Noise Figure f = 2 GHz V DS = 4 V, IDS = 60 mA dB 0.5 0.8 V DS = 4 V, IDS = 30 mA 0.5 f = 900 MHz V DS = 4 V, IDS = 60 mA dB 0.4 G a Associated Gain f = 2 GHz V DS = 4 V, IDS = 60 mA dB 16 17.5 19 V DS = 4 V, IDS = 30 mA 17 f = 900 MHz V DS = 4 V, IDS = 60 mA dB 21.5 OIP3 Output 3 rd Order f = 2 GHz V DS = 4 V, IDS = 60 mA dBm 29 31.5 Intercept Point [3] +5 dBm P out /Tone V DS = 4 V, IDS = 30 mA 30 f = 900 MHz V DS = 4 V, IDS = 60 mA dBm 31 +5 dBm P out /Tone P 1dB 1 dB Compressed f = 2 GHz V DS = 4 V, IDS = 60 mA dBm 20 Intercept Point [3] V DS = 4 V, IDS = 30 mA 19 f = 900 MHz V DS = 4 V, IDS = 60 mA dBm 18.5 Notes: 1. Guaranteed at wafer probe level 2. Typical value determined from a sample size of 450 parts from 9 wafers. 3. Using production test board.Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, and OIP3 measurements. This circuit represents a trade-off between an optimal noise match and associated impedance matching circuit losses. Circuit losses have been de-embedded from actual measurements. Input 50 Ohm Transmission Line Including Gate Bias T (0.5 dB loss) Input Matching Circuit Γ_mag = 0.30 Γ_ang = 56° (0.4 dB loss) DUT
50 Ohm
(0.5 dB loss) Output
Figure 23. MSG/MAG and |S21|2 vs. Frequency
- Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin value s are based
is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the
holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point.
Figure 24. MSG/MAG and |S21|2 vs. Frequency
- Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin value s are based
is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the
holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point.
Figure 25. MSG/MAG and |S21|2 vs. Frequency
- Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin value s are based
is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the
holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point.
Figure 26. MSG/MAG and |S21|2 vs. Frequency
- Fmin values at 2 GHz and higher are based on measurements while the Fmins below 2 GHz have been extrapolated. The Fmin value s are based
is calculated. Refer to the noise parameter application section for more information.
- S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the
holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point.
Noise Parameter Applications Information Fmin values at 2 GHz and higher are based on measure- ments while the F mins below 2 GHz have been extrapo- lated. The Fmin values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATN NP5 test system. From these measurements, a true F min is calculated. Fmin represents the true minimum noise fi gure of the device when the device is presented with an impedance matching network that transforms the source impedance, typically 50Ω, to an impedance represented by the refl ection coeffi cient o. The designer must design a matching network that will present o to the device with minimal associated circuit losses. The noise fi gure of the completed amplifi er is equal to the noise fi gure of the device plus the losses of the matching network preceding the device. The noise fi gure of the device is equal to F min only when the device is presented with o. If the refl ection coeffi cient of the matching network is other than o, then the noise fi gure of the device will be greater than F min based on the following equation. NF = Fmin + 4 Rn |s – o | 2 Where Rn /Zo is the normalized noise resistance, o is the optimum refl ection coeffi cient required to produce F min and s is the refl ection coeffi cient of the source imped- ance actually presented to the device. The losses of the matching networks are non-zero and they will also add to the noise fi gure of the device creating a higher ampli- fi er noise fi gure. The losses of the matching networks are related to the Q of the components and associated printed circuit board loss. o is typically fairly low at higher frequencies and increases as frequency is lowered. Larger gate width devices will typically have a lower o as com- pared to narrower gate width devices. Typically for FETs, the higher o usually infers that an im- pedance much higher than 50Ω is required for the device to produce F min. At VHF frequencies and even lower L Band frequencies, the required impedance can be in the vicinity of several thousand ohms. Matching to such a high impedance requires very hi-Q components in order to minimize circuit losses. As an example at 900 MHz, when airwwound coils (Q > 100) are used for matching networks, the loss can still be up to 0.25 dB which will add directly to the noise fi gure of the device. Using muiltilayer molded inductors with Qs in the 30 to 50 range results in additional loss over the airwound coil. Losses as high as 0.5 dB or greater add to the typical 0.15 dB F min of the device creating an amplifi er noise fi gure of nearly 0.65 dB. A discussion concerning calculated and measured circuit losses and their eff ect on amplifi er noise fi gure is covered in Avago Application 1085.
L=Lc L=Lb R=Rb L=Lb R=Rb L C C=Ca CC=Cb LOSSYL L=Lb R=Rb L=La*.5 L=Ld L L LOSSYL GATE_IN SOURCE DRAIN_OUT REQUATION La=0.1 nH EQUATION Lb=0.1 nH EQUATION Lc=0.8 nH EQUATION Ld=0.6 nH EQUATION Rb=0.1 OH EQUATION Ca=0.15 pF EQUATION Cb=0.15 pF R=0.1 OH LOSSYL L=La L=Lb R=Rb L LOSSYL L=Lb R=Rb LOSSYL G S D SOURCE ATF-34143 SC-70 4 Lead, High Frequency Nonlinear Model Optimized for 0.1–6.0 GHz This model can be used as a design tool. It has been tested on MDS for various specifi cations. However, for more precise and accurate design, please refer to the measured data in this data sheet. For future improvements Avago reserves the right to change these models without prior notice. NFETMESFET G MODEL=FET W=800 μm XX D XX S SXX NFET=yes PFET= IDSMOD=3 VTO=–0.95 BETA= Beta LAMBDA=0.09 ALPHA=4.0 B=0.8 TNOM=27 IDSTC= VBI=.7 IDS model DELTA=.2 GSCAP=3 CGS=cgs pF GDCAP=3 GCD=Cgd pF Gate model RG=1 RD=Rd RS=Rs LG=Lg nH LD=Ld nH LS=Ls nH CDS=Cds pF CRF=.1 RC=Rc Parasitics GSFWD=1 GSREV=0 GDFWD=1 GDREV=0 VJR=1 IS=1 nA IR=1 nA IMAX=.1 XTI= EG= Breakdown FNC=01e+6 R=.17 P=.65 C=.2 Noise Model scal factors (W=FET width in microns) EQUATION Cds=0.01 *W/200 EQUATION Beta=0.06 *W/200 EQUATION Rd=200/W EQUATION Rs=.5 *200/W EQUATION Cgs=0.2 *W/200 EQUATION Cgd=0.04 *W/200 EQUATION Lg=0.03 *200/W EQUATION Ld=0.03 *200/W EQUATION Ls=0.01 *200/W EQUATION Rc=500 *200/W * STATZ MESFET MODEL *MODEL = FET ATF-34143 Die Model
Part Number Ordering Information No. of Part Number Devices Container ATF-34143-TR1G 3000 7” Reel ATF-34143-TR2G 10000 13” Reel ATF-34143-BLKG 100 antistatic bag HE D A1b E 1.30 (.051) BSC 1.15 (.045) BSC CL A DIMENSIONS (mm) MIN. 1.15 1.85 1.80 0.80 0.80 0.00 0.15 0.55 0.10 0.10 MAX. 1.35 2.25 2.40 1.10 1.00 0.10 0.40 0.70 0.20 0.46 SYMBOL E D HE A b c L NOTES: 1. All dimensions are in mm. 2. Dimensions are inclusive of plating. 3. Dimensions are exclusive of mold flash & metal burr. 4. All specifications comply to EIAJ SC70. 5. Die is facing up for mold and facing down for trim/form, ie: reverse trim/form. 6. Package surface to be mirror finish. Recommended PCB Pad Layout for Avago’ s SC70 4L/SOT-343 Products 1.30 (0.051) 0.60 (0.024) 0.9 (0.035) Dimensions in mm (inches) 1.15 (0.045) 2.00 (0.079) 1.00 (0.039)
Tape Dimensions for Outline 4T P F W C D E 10° MAX. t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) 10° MAX. DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A P 2.40 ± 0.10 2.40 ± 0.10 1.20 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.094 ± 0.004 0.094 ± 0.004 0.047 ± 0.004 0.157 ± 0.004 0.039 + 0.010 CAVITY DIAMETER PITCH POSITION D P E 1.55 ± 0.10 4.00 ± 0.10 1.75 ± 0.10 0.061 + 0.002 0.157 ± 0.004 0.069 ± 0.004 PERFORATION WIDTH THICKNESS W 8.00 + 0.30 - 0.10 0.254 ± 0.02 0.315 + 0.012 0.0100 ± 0.0008 CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) F P 3.50 ± 0.05 2.00 ± 0.05 0.138 ± 0.002 0.079 ± 0.002 DISTANCE WIDTH TAPE THICKNESS C Tt 5.40 ± 0.10 0.062 ± 0.001 0.205 + 0.004 0.0025 ± 0.0004 COVER TAPE For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-3746EN AV02-1283EN - June 8, 2012 Device Orientation USER FEED DIRECTION COVER TAPE CARRIER TAPE REEL END VIEW 8 mm 4 mm TOP VIEW 4PX 4PX 4PX 4PX