ATF-33143-TR1G

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Document overview

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Technical content

Features

 Lead-free Option Available  Low Noise Figure  Excellent Uniformity in Product Specifi cations  1600 micron Gate Width  Low Cost Surface Mount Small Plastic Package SOT-343 (4 lead SC-70)  Tape-and-Reel Packaging Option Available Specifi cations 1.9 GHz; 4V, 80 mA (Typ.)  0.5 dB Noise Figure  15 dB Associated Gain  22 dBm Output Power at 1 dB Gain Compression  33.5 dBm Output 3 rd Order Intercept

Applications

 Tower Mounted Amplifi er, Low Noise Amplifi er and Driver Amplifi er for GSM/TDMA/CDMA Base Stations  LNA for Wireless LAN, WLL/RLL and MMDS  General Purpose Discrete PHEMT for other Ultra Low Noise Applications

Description

Avago’s ATF-33143 is a high dynamic range, low noise PHEMT housed in a 4-lead SC-70 (SOT-343) surface mount plastic package. Based on its featured performance, ATF-33143 is ideal for the fi rst or second stage of base station LNA due to the excellent combination of low noise fi gure and enhanced linearity [1]. The device is also suitable for applications in Wireless LAN, WLL/RLL, MMDS, and other systems requiring super low noise fi gure with good intercept in the 450 MHz to 10 GHz frequency range. Note: 1. From the same PHEMT FET family, the smaller geometry ATF- 34143 may also be considered for the higher gain performance, particularly in the higher frequency band (1.8 GHz and up). Surface Mount Package SOT-343 Pin Connections and Package Marking Note: Top View. Package marking provides orientation and identifi cation. “3P” = Device code “x” = Date code character. A new character is assigned for each month, year. SOURCE DRAIN GATE SOURCE 3Px Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) ESD Human Body Model (Class 0) Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control.

Figure 5. Block diagram of 2 GHz production test board used for Noise Figure, Associated Gain, P1dB, and OIP3 measurements. This circuit represents a

50 Ohm

Symbol Parameters and Test Conditions Units Min. Typ. [2] Max.

1. Guaranteed at wafer probe level.
2. Typical value determined from a sample size of 450 parts from 9 wafers.
3. Measurements obtained using production test board described in Figure 5.

1. Measurements made on a fi xed tuned production test board that was tuned for optimal gain match with reasonable noise fi gure at 4V 80 mA

board requirements. Circuit losses have been de-embedded from actual measurements.

1. Quiescent drain current, I DSQ, is set with zero RF drive applied. As P1dB is approached, the drain current may increase or decrease depending on

Figure 6. OIP3, IIP3 vs. Bias[1] at 2 GHz.

4 V IDSQ (mA)

Figure 7. OIP3, IIP3 vs. Bias[1] at 900 MHz.

1. Measurements made on ATN LP1 power load pull system.
2. Quicescent drain current, I
3. Gamma out is the refl ection coeffi cient of the matching circuit presented to the output of the device.

Figure 20. Swept Power Tuned for Max P1dB

1. The F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATF NP5 test system. From these

measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end

diameter via holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point. Figure 21. MSG/MAG and |S21|2 vs. Frequency at 2V, 40 mA.

1. The F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATF NP5 test system. From these

measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end

diameter via holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point. Figure 22. MSG/MAG and |S21|2 vs. Frequency at 3V, 40 mA.

1. The F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATF NP5 test system. From these

measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end

diameter via holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point. Figure 23. MSG/MAG and |S21|2 vs. Frequency at 3V, 60 mA.

1. The F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATF NP5 test system. From these

measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end

diameter via holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point. Figure 24. MSG/MAG and |S21|2 vs. Frequency at 4V, 40 mA.

1. The F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATF NP5 test system. From these

measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end

diameter via holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point. Figure 25. MSG/MAG and |S21|2 vs. Frequency at 4V, 60 mA.

1. The F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATF NP5 test system. From these

measurements a true Fmin is calculated. Refer to the noise parameter application section for more information.

1. S and noise parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end

diameter via holes are placed within 0.010 inch from each source lead contact point, one via on each side of that point. Figure 26. MSG/MAG and |S21|2 vs. Frequency at 4V, 80 mA.

Noise Parameter Applications Information Fmin values at 2 GHz and higher are based on measurements while the F mins below 2 GHz have been extrapolated. The F min values are based on a set of 16 noise fi gure measurements made at 16 diff erent impedances using an ATN NP5 test system. From these measurements, a true F min is calculated. F min represents the true minimum noise fi gure of the device when the device is presented with an impedance matching network that transforms the source impedance, typically 50Ω, to an impedance represented by the refl ection coeffi cient o. The designer must design a matching network that will present o to the device with minimal associated circuit losses. The noise fi gure of the completed amplifi er is equal to the noise fi gure of the device plus the losses of the matching network preceding the device. The noise fi gure of the device is equal to F min only when the device is presented with o. If the refl ection coeffi cient of the matching network is other than o, then the noise fi gure of the device will be greater than F min based on the following equation. NF = Fmin + 4 Rn |s – o | 2 Where R n /Zo is the normalized noise resistance, o is the optimum refl ection coeffi cient required to produce Fmin and s is the refl ection coeffi cient of the source impedance actually presented to the device. The losses of the matching networks are non-zero and they will also add to the noise fi gure of the device creating a higher amplifi er noise fi gure. The losses of the matching networks are related to the Q of the components and associated printed circuit board loss.  o is typically fairly low at higher frequencies and increases as frequency is lowered. Larger gate width devices will typically have a lower  o as compared to narrower gate width devices. Typically for FETs, the higher o usually infers that an impedance much higher than 50Ω is required for the device to produce F min. At VHF frequencies and even lower L Band frequencies, the required impedance can be in the vicinity of several thousand ohms. Matching to such a high impedance requires very hi-Q components in order to minimize circuit losses. As an example at

900 MHz, when airwwound coils (Q > 100) are used for

matching networks, the loss can still be up to 0.25 dB which will add directly to the noise fi gure of the device. Using muiltilayer molded inductors with Qs in the 30 to 50 range results in additional loss over the airwound coil. Losses as high as 0.5 dB or greater add to the typical 0.15 dB F min of the device creating an amplifi er noise fi gure of nearly 0.65 dB. A discussion concerning calculated and measured circuit losses and their eff ect on amplifi er noise fi gure is covered in Avago Application 1085. Reliability Data Nominal Failures per million (FPM) 90% confi dence Failures per million (FPM) for diff erent durations for diff erent durations Channel (FITs) 1 year 5 year 10 year 30 year (FITs) 1 year 5 year 10 year 30 year Temperature 1000 1000 oC) hours hours 150 <0.1 <0.1 2 140 26K <0.1 0.3 780 8800 131K 160 <0.1 <0.1 920 21K 370K <0.1 67 24K 120K 520K 180 <0.1 4400 450K 830K 1000K 21 53K 590K 850K 1000K NOT recommended Predicted failures with temperature extrapolated from failure distribution and activation energy data of higher temperature operational life STRIFE of PHEMT process

This model can be used as a design tool. It has been tested on MDS for various specifi cations. However, for more precise and accurate design, please refer to the measured data in this data sheet. For future improvements Avago reserves the right to change these models without prior notice. ATF-33143 Model NFET=yes PFET=no Vto=–0.95 Beta=0.48 Lambda=0.09 Alpha=4 B=0.8 Tnom=27 Idstc= Vbi=0.7 Tau= Betatce= Delta1=0.2 Delta2= Gscap=3 Cgs=1.6 pF Gdcap=3 Cgd=0.32 pF Rgd= Tqm= Vmax= Fc= Rd=.125 Rg=1 Rs=0.0625 Ld=0.00375 nH Lg-0.00375 nH Ls=0.00125 nH Cds=0.08 pF Crf=0.1 Rc=62.5 Gsfwd=1 Gsrev=0 Gdfwd=1 Gdrev=0 Vjr=1 Is=1 nA Ir=1 nA Imax=0.1 Xti= Eg= Vbr= Vtotc= Rin= Taumd1=no Fnc=1E6 R=0.17 C=0.2 P=0.65 wVgfwd= wBvgs= wBvgd= wBvds= wldsmax= wPmax= Al lParams= Statz Model MESFETM1 GATE SOURCE Port G Num=1 C C=0.1 pF Port Num=2 SOURCE DRAIN Port Num=4 Port D Num=4 L L=0.2 nH R=0.001 C C=0.11 pF L C=0.6 nH R=0.001MSub TLINP TL4 Z=Z1 Ohm L=15 mil K=1 A=0.000 F=1 GHz TanD=0.001 TLINP TL10 Z=Z1 Ohm L=15 mil K=1 A=0.000 F=1 GHz TanD=0.001 VIA2 D=20 mil H=25.0 mil T=0.15 mil Rho=1.0 W=40 mil VIA2 D=20.0 mil H=25.0 mil T=0.15 mil Rho=1.0 W=40.0 mil TLINP TL3 Z=Z2 Ohm L=25 mil K=K A=0.000 F=1 GHz TanD=0.001 TLINPTL9 Z=Z2 Ohm L=10.0 mil K=K A=0.000 F=1 GHz TanD=0.001 VAR VAR1 K=5 Z2=85 Z1=30 Var Ean TLINP TL1 Z=Z2/2 Ohm L=20 0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL2 Z=Z2/2 Ohm L=20 0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL8 Z=Z1 Ohm L=15 mil K=1 A=0.0000 F=1 GHz TanD=0.001 TLINP TL7 Z=Z2/2 Ohm L=5.0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL5 Z=Z2 Ohm L=26.0 mil K=K A=0.0000 F=1 GHz TanD=0.001 TLINP TL6 Z=Z1 Ohm L=15 mil K=1 A=0.0000 F=1 GHz TanD=0.001 VIA2 D=20.0 mil H=25.0 mil T=0.15 mil Rho=1.0 W=40.0 mil VIA2 D=20.0 mil H=25.0 mil T=0.15 mil Rho=1.0 W=40.0 mil L L=0.6 nH R=0.001 L L=0.2 nH R=0.001 GaAsFET FET1 Model=MESFETN1 Mode=nonlinear MSUB MSub1 H=25.0 mil Er=9.6 Mur=1 Cond=1.0E+50 Hu=3.9e+0.34 mil T=0.15 mil TanD=D Rough=D mil

Part Number Ordering Information No. of Part Number Devices Container ATF-33143-TR1G 3000 7” Reel ATF-33143-TR2G 10000 13” Reel ATF-33143-BLKG 100 antistatic bag Package Dimensions SC-70 4L/SOT-343 HE D A1b E 1.30 (.051) BSC 1.15 (.045) BSC CL A DIMENSIONS (mm) MIN. 1.15 1.85 1.80 0.80 0.80 0.00 0.15 0.55 0.10 0.10 MAX. 1.35 2.25 2.40 1.10 1.00 0.10 0.40 0.70 0.20 0.46 SYMBOL E D HE A b c L NOTES: 1. All dimensions are in mm. 2. Dimensions are inclusive of plating. 3. Dimensions are exclusive of mold flash & metal burr. 4. All specifications comply to EIAJ SC70. 5. Die is facing up for mold and facing down for trim/form, ie: reverse trim/form. 6. Package surface to be mirror finish. 1.30 (0.051) 0.60 (0.024) 0.9 (0.035) Dimensions in mm (inches) 1.15 (0.045) 2.00 (0.079) 1.00 (0.039) Recommended PCB Pad Layout for Avago’ s SC70 4L/SOT-343 Products

Tape Dimensions and Product Orientation For Outline 4T For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-3747EN AV02-1442EN - June 8, 2012 Device Orientation USER FEED DIRECTION COVER TAPE CARRIER TAPE REEL END VIEW 8 mm 4 mm TOP VIEW 3Px 3Px 3Px 3Px P Po P2 F W C D E Ao 10 MAX. t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) 10 MAX. Bo Ko DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER Ao Bo Ko P 2.40 ± 0.10 2.40 ± 0.10 1.20 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.094 ± 0.004 0.094 ± 0.004 0.047 ± 0.004 0.157 ± 0.004 0.039 + 0.010 CAVITY DIAMETER PITCH POSITION D Po E 1.55 ± 0.10 4.00 ± 0.10 1.75 ± 0.10 0.061 + 0.002 0.157 ± 0.004 0.069 ± 0.004 PERFORATION WIDTH THICKNESS W 8.00 + 0.30 - 0.10 0.254 0.02 0.315 + 0.012 0.0100 ± 0.0008 CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) F 3.50 ± 0.05 2.00 ± 0.05 0.138 ± 0.002 0.079 ± 0.002 DISTANCE WIDTH TAPE THICKNESS C Tt 5.40 ± 0.10 0.062 ± 0.001 0.205 + 0.004 0.0025 ± 0.0004 COVER TAPE