ATC35

ATC35 ATMEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

Features

• Comprehensive Library of Standard Logic Cells  ATC35 I/O Cells Designed to Operate with V DD = 3.3V ± 0.3V as Main Target Operating Conditions  IO35 Pad Library Provides Interface to 5V Environment  Oscillators and Phase Locked Loops for Stable Clock Sources  Memory Cells Compiled to the Precise Requirements of the Design  Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard Interface and Application Specific Cells  High-Performance Analog Cells can be Developed on Request

Description

The Atmel ATC35 (AT56K) process is a proprietary 0.35 micron three-layer-metal CMOS process intended for use with a supply voltage of 3.3V ± 0.3V . The following table shows the range for which Atmel library cells have been characterized. The Atmel cell libraries and megacell compilers have been designed in order to be compatible with each other. Simulation representations exist for three types of operat- ing conditions. They correspond to three characterization conditions defined as follows:  MIN conditions: T J =- 5 5°C VDD (cell) = 3.60V Process = fast (industrial best case)  TYP conditions: TJ =+ 2 5°C VDD (cell) = 3.30V Process = typ (industrial typical case)  MAX conditions: TJ = +100°C VDD (cell) = 3.00V Process = slow (industrial worst case) Delays to tristate are defined as delay to turn off (VGS < VT) of the driving devices. Output pad drain current corresponds to the output current of the pad when the output voltage is V OL or V OH. The output resistor of the pad and the voltage drop due to access resistors (in and out of the die) are taken into account. In order to have accu- rate timing estimates, all characterization has been run on electrical netlists extracted from the layout database. Table 1. Recommended Operating Conditions

2 ATC35 Summary

cell. This indicates the range of standard cells available. Table 2. Cell Codes

library. Note that all storage elements feature buffered clock inputs and buffered output. Table 3. JK Flip-flops Table 4. D Flip-flops Table 5. Scan Flip-flops

4 ATC35 Summary

special set of I/O cells, IO35lib, for interfacing with external 5V devices. power to the core without affecting noise performance. Table 6. VSS Power Pad Combinations

• PV0I VSS
• PV0A VSS
• PV0D VSS
• • PV0E VSS
• • PV0B VSS
• •• PV0F VSS

Table 7. VDD Power Pad Combinations

• PVDI VDD
• PVDA VDD
• PVDD VDD
• • PVDE VDD
• • PVDB VDD
• •• PVDF VDD

Table 8. CMOS Pads Table 9. TTL Pads Table 10. CMOS/TTL Input Only Pad

6 ATC35 Summary

Table 11. Core-driven Clock Buffer Pads Table 12. IO35lib Pads Table 13. IO35lib Power Pads

may be necessary to add external capacitors on xin and xout to ground in special cases. Clock output is low at off state (onosc = 0). The oscillators provide a test mode (test = 1 and onosc = 1), clock = not (xin). Table 14 gives available oscillator and POR cells. – Multiplexers to minimize cross-talk (for use with high-impedance nodes). – Multiplexers to minimize ON resistance. Table 14. Oscillator and POR Cells dynamic reset with internal hysteresis. Table 15. Phase Locked Loop Cells

8 ATC35 Summary

1063CS–CBIC–01/03 Atmel Compiled Megacell Library The Atmel Compiled Megacell Library enables compilation of megacells for the func- tions ARAM (Advanced Random Access Memory), Dual-Port RAM, FIFO (First In First Out), ROM, and LROM (Large ROM) according to the user’s precise requirements. The Atmel megacells can be instanced as often as required in designs and can be used in parallel with cells from all other Atmel CBIC libraries. All the megacell representations required for schematic entry, simulation, layout generation, place and route, and verifi- cation are created automatically. The Built-In Self-Test (BIST) option, in terms of a netlist of standard cells surrounding the megacell, is supported for all megacells except the LROM (in this release). FIFO and FIFO with BIST are available through the Cgenerate as netlists of standard cells surrounding a Dual-Port RAM Megacell. Compiled ARAM Megacells The Atmel ARAM compiler builds Clocked Embedded Self-timed Static RAMs from a set of input parameters, for example, the number of words and the word width. The Atmel ARAM generator is capable of creating many different sizes of RAM. In addition, for any given size, many configurations are possible. The differences in these configurations can be found in the aspect ratio and in performances. The range of permitted ARAM megacell configurations is as follows: Max number of bits 256K bits Number of words 64, .. 32768 multiples of 32 Number of rows 32, .. 256 multiples of 16 Number of columns per bit 2, 4, 8 (words per row per block) Number of blocks 1, 2, 4, 8, 16 Number of bits in a word: if no. of blocks = 1 1, .. 128 increment of 1 if no. of blocks > 1 4, .. 32 if no. of columns per bit = 2 2, .. 16 if no. of columns per bit = 4 1, .. 8 if no. of columns per bit = 8 The following table lists all ARAM inputs and outputs and their pin capacitances. Pin Name Comment Capacitance (pF) ME Clock (T rigger) Input 0.014 WE_ (Read)(Write not) Input 0.086 ADD<i> Address Input 0.084 DI<j> Data Input 0.019 DO<j> Data Output 2.50 (max load) VDD Supply GND Ground

1063CS–CBIC–01/03 The following tables show the range of performances for particular ARAM configura- tions without BIST and without C Load.A c c e s st i m e( tACC) and cycle time (t CYC)r e f e rt o Max industrial conditions, whereas Dynamic Power dissipation refers to typical conditions. Compiled Dual-Port RAM Megacells The Atmel Dual-Port RAM is a read/write memory that allows access to and from its memory cells by two independent ports (identified as Port A and Port B). There are no constraints on the timing of the ports relative to each other except in the case of address contention. Although the ports are constructed from the same circuitry, the possible I/O configurations are different:  Port A may be selected with read/write or read-only capability  Port B can have read/write or write-only capability The two ports may have different wordlengths, provided that the ratio is an integral power of 2 (1, 2, 4, 8, 16, 32 or 64). The product (wordlength x address space) must be t h es a m ef o rt h et w op o r t s . The memory cell corresponds to a standard full CMOS six-transistor cell with the benefit of extremely low standby power dissipation. (There are actually eight or ten transistors per cell, according to the configuration of the port A). Dual-Port RAM operates in single-edge clock controlled mode during read operations, and a double-edge controlled mode during write operations. Addresses are clocked internally on the rising edge of the clock signal (ME). Any change of address without ris- ing edge of ME is not considered. In read mode, the rising clock edge triggers a data read without any significant con- straint on the length of the ME pulse. In write mode, data applied to the inputs is latched on the falling edge of ME or the rising edge of WE_, whichever comes earlier, and is then written in memory. Word Size = 8 W o r d D e p t h 2 5 6 5 1 2 1 K2 K4 K8 K1 6 K 3 2 K Access Time (t Word Size = 16 Word Depth 128 256 512 1K 2K 4K 8K 16K Access Time (t

10 ATC35 Summary

1063CS–CBIC–01/03 The range of permitted Dual-Port RAM Megacell configurations is as follows: Number of rows: 4, ...128 Number of cols: 2, ...128 Number of words: 8, ...16384 Bits per word: 1, ...64 Total size: 8, ...16384 Port A configuration: read/write, read-only Port B configuration: read/write, write-only The following table lists all DPR inputs and outputs and their pin capacitances. Pin names are suffixed with the port nature A or B: The following tables show the range of performances for particular Dual Port RAM con- figurations, without BIST and without output load. Access time (t ACC) and cycle time (tCYC) refer to Max industrial conditions, whereas Dynamic Power dissipation refers to typical conditions. All examples have the same configuration for both port A and port B, with Read/Write capability. Pin Name Comment Capacitance (pF) ME Clock Input 0.020 WE_ Write Enable Input 0.013 ADD<i> Address Input 0.018 DI<j> Data Input 0.012 DO<j> Data Output 3.55 (max load) VDD Supply GND Ground Word Size = 8 Word Depth 128 256 512 1K 2K R o w sxC o l u m n s 3 2x3 2 6 4x3 2 6 4x6 4 1 2 8x6 4 1 2 8x1 2 8 Access Time (t Word Size = 16 Word Depth 64 128 256 512 1K Rows x Columns 32 x 32 64 x 32 64 x 64 128 x 64 128 x 128 Access Time (t

1063CS–CBIC–01/03 Compiled FIFO Megacells A compiled FIFO (first-in first-out data flow) megacell is implemented as a soft macro built around a Dual-Port RAM. The compiled FIFO is a buffer memory that allows access to its memory cells by two independent ports. The read port is referred to as port A, the write port is labelled port B. Both ports are controlled by independent clock signals and contain address counters which are incremented during every clock cycle. The FIFO block makes use of a compiled Dual-Port RAM with the configuration port A read-only and port B write-only. Number of rows: 2, ...128 in increments of 2 Number of words: 8, 16, 32, ...16384 Bits per word: 1, ...64 Total size: 8, ...16384 The word lengths of both ports may be different, but their ratio must be one of (1, 2, 4, 8, 16, 32 or 64). The following is a list of pins which will be found on the symbol of a module:  CKOUT is the clock input for port A (read port).  CKIN is the clock input for port B (write port).  DIN<0:i-1> Data input lines.  DOUT<0:i-1> Data output lines.  RESETZ The clear signal.  EMPTY The empty flag.  FULL The full flag.  Supply (VDD) and ground (GND). The following table shows the estimated range of performance for particular FIFO con- figurations, without BIST, and without output load. Access time (t ACC) and cycle time (tCYC) refer to Max industrial conditions, whereas Dynamic Power dissipation refers to typical conditions. All examples have the same configuration for both port A and port B, with Read/Write capability. There is no additional flag. Word Size 4 8 16 32 64 W o r d D e p t h 1 6 3 26 41 2 8 2 5 6 Rows x Columns 8 x 8 16 x 16 32 x 32 64 x 64 128 x 128 Access Time (t

12 ATC35 Summary

1063CS–CBIC–01/03 Compiled ROM Megacells Compiled memories are diffusion-programmed ROMs with a synchronous access proto- col. The generated ROM Megacell is a single edge control ROM. Rising edge of the memory enable signal (ME) latches the addresses and starts the read operation. The internal idle state of the memory plane is the precharge state. The next clock cycle can start with the next ME rising edge, once the precharge is complete. The generator takes care of complementing the required address space to the nearest physical size possible in case of number of words being not equal to an integral power of two. The range of permitted ROM configurations is as follows : Number of words: 9...16384 Number of Address Bits: 4...14 Bits per words: 1...128 Total size: 9...131072 (128K) Number of Columns: 4...512 Number of Rows: 4...256 The memory plane is organized in multiples of 4 rows, and multiples of 4, 8, 16, 32 or 64 columns. The following table lists all ROM inputs and outputs and their pin capacitances: The following tables show the range of performances for particular ROM configurations. Access time (t ACC)a n dc y c l et i m e( tCYC) refer to Max industrial conditions, whereas Dynamic Power dissipation refers to typical conditions. Pin Name Comment Capacitance (pF) ME Clock Input 0.029 OE Output Enable Input 0.007 ADD<i> Address Input 0.010 DO<j> Data Output 0.016 (if tristate) 3.20 (max load) Word Size = 8 Word Depth 16 32 64 128 256 512 1K Access Time (t Word Size = 16 Word Depth 16 32 64 128 256 512 1K Access Time (t

1063CS–CBIC–01/03 Compiled LROM Megacells The LROM (Large ROM) compiler allows the system designer to acheive high-density and low-power applications. Multi-block megacells with total capacity up to 4M-bits can be generated by the LROM compiler. Compiled memories are diffusion-programmed ROMs with a synchronous access proto- col, as is for the ROM. The compiler expects a programming file: lrom<xyz>.prg that contains the LROM pattern. If the .prg file is not available, a random contents is auto- matically generated. Unlike the ROM compiler, only buffered outputs can be acheived using the LROM compiler. The range of permitted LROM configurations is as follows: Total size: 64K...4M Number of words: 2K...512K Bits per word: 8, 16 or 32 Number of address bits:11...19 The memory is organized in multiple blocks of 64K bits each. Number of blocks: 1...32 Number of rows per block: 256 Number of columns per block:256 I/O pins in compiled megacells are the following: me input: Memory Enable. add<i> inputs: Address. do<i> outputs: buffered output data. vdd and gnd: power and ground supplies. The following table shows the performances for some LROM configurations. Access time (t ACC), cycle time (t CYC) and Dynamic Power dissipation refer to Max industrial conditions. Word Size = 16 Word Depth 16K 32K 64K 128K Width (mm) 0.979 3.570 1.863 1.863 Height (mm) 0.858 0.539 1.716 3.078 Access Time (t ACC) (nsec) 11.37 11.84 12.53 15.19 C y c l eT i m e( tCYC) (nsec) 14.15 14.40 15.30 19.14 Dynamic Power (mW/MHz) 0.26 0.56 0.75 0.90

Printed on recycled paper. © Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel Headquarters Atmel Operations Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza

77 Mody Road Tsimhatsui

TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Memory San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 Microcontrollers San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602

44306 Nantes Cedex 3, France

13106 Rousset Cedex, France

1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 RF/Automotive Theresienstrasse 2 Postfach 3535

74025 Heilbronn, Germany

FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123

38521 Saint-Egreve Cedex, France

literature@atmel.com Web Site http://www.atmel.com 1063CS–CBIC–01/03 0M ATM EL® is the registered trademark of Atmel. Other terms and product names may be the trademarks of others.