ATC25 ATMEL | Alldatasheet

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Technical content

Features

  • Comprehensive Library of Standard Logic Cells  ATC25 I/O Cells Designed to Operate with VDD = 2.5V ± 0.25V as Main Target Operating Conditions  IO33 Pad Library Provides Interface to 3V Environment  Oscillators Provide Stable Clock Sources  Basic Analog Input/Output, Power, Ground and Multiplexer Cells Available, High-performance Analog Cells Can Be Developed on Request  Memory Cells Compiled to the Precise Requirements of the Design  Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard Interface and Application Specific Cells

Description

The Atmel A TC25 CBIC family is fabricated on a proprietary 0.25 micron five-layer- metal CMOS process intended for use with a supply voltage of 2.5V ± 0.25V. The fol- lowing table shows the range for which Atmel library cells have been characterized. The Atmel cell libraries and megacell compilers have been designed in order to be compatible with each other. Simulation representations exist for three types of operat- ing conditions; they correspond to three characterization conditions defined as follows:  MIN conditions: T J =- 4 0°C VDD (cell) = 2.75V Process = fast (industrial best case)  TYP conditions: TJ =+ 2 5°C VDD (cell) = 2.5V Process = typ (industrial typical case)  MAX conditions: TJ = +100°C VDD (cell) = 2.25V Process = slow (industrial worst case) Delays to tri-state are defined as delay to turn off (VGS < VT) of the driving devices. Output pad drain current corresponds to the output current of the pad when the output voltage is V OL or V OH. The output resistor of the pad and the voltage drop due to access resistors (in and out of the die) are taken into account. In order to have accu- rate timing estimates, all characterization has been run on electrical netlists extracted from the layout database. Table 1. Recommended Operating Conditions

2 ATC25 Summary

cell. This indicates the range of standard cells available. Table 2. Cell Codes

library. Note that all storage elements feature buffered clock inputs and buffered output. Table 3. JK Flip-flops Table 4. D Flip-flops Table 5. Scan Flip-flops

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of I/O cells, IO33lib, for interfacing with external 3V devices. volt standard cells library. power to the core without affecting noise performance. Table 6. VSS Power Pad Combinations

  • pv25i00 VSS
  • pv25a00 VSS
  • pv25d00 VSS
  • • pv25e00 VSS
  • • pv25b00 VSS
  • •• pv25f00 VSS

Table 7. VDD Power Pad Combinations

  • pv25i25 VDD
  • pv25a25 VDD
  • pv25d25 VDD
  • • pv25e25 VDD
  • • pv25b25 VDD
  • •• pv25f25 VDD

Table 8. CMOS Pads Table 9. TTL Pads Table 10. CMOS/TTL Input Only Pad

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supply voltage processes in order to interface 2.5V ASICs to 3.3V environments. level shifter (slow by construction) to reduce the slew rate without reducing speed. Table 11. IO33lib Pads Table 12. IO33lib Power Pads

pF. External capacitors must be added in order to obtain the correct load capacitance. Clock output is high at off state (onosc = 0). The oscillators provide a bypass mode (onosc = 1), clock = not (xin). Table 13 gives the available oscillator cells. – Multiplexers to minimize cross-talk (for use with high-impedance nodes). – Multiplexers to minimize ON resistance. Table 13. Oscillator and POR Cells

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1306DS–CBIC–09/02 Atmel Compiled Megacell Library The Atmel Compiled Megacell Library enables compilation of megacells for the func- tions Synchronous RAM, High-range Synchronous RAM, Asynchronous RAM, Asynchronous Dual-port RAM, Asynchronous Two-port RAM and Synchronous ROM, according to the user’s precise requirements. The Atmel megacells can be instanced as often as required in designs and can be used in parallel with cells from all other Atmel CBIC libraries. All the megacell representations required for schematic entry, simulation, place and route, layout generation, and verifi- cation are created automatically. Compiled Synchronous RAM Megacells The Atmel Synchronous RAM compiler has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Synchronous RAM megacell configurations is as follows: Number of bits 128, .. 144K bits Number of words 32, .. 8K Word Size 4, .. 36 bits The following table shows the range of performances for particular Synchronous RAM configurations under typical conditions. Compiled High-range Synchronous RAM Megacells The Atmel High-range Synchronous RAM compiler has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted High-range Synchronous RAM megacell configurations is as follows: Number of bits 16K, .. 2.25M bits Number of words 2K, .. 32K Word Size 8, .. 72 bits The following table shows the range of performances for particular High-range Synchro- nous RAM configurations under typical conditions. Configuration 1K x 8 (8K bits) 2K x 16 (32K bits) 4K x 32 (128K bits) Density (Kbits/mm2) 5 15 86 2 Frequency (MHz) 305 242 169 Dynamic Power Configuration 8K x 8 (64K bits) 16K x 16 (256K bits) 32K x 32 (1M bits) Density (Kbits/mm2) 8 08 48 7 Frequency (MHz) 186 120 71 Dynamic Power

1306DS–CBIC–09/02 Compiled Asynchronous RAM Megacells The Atmel Asynchronous RAM compiler has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Asynchronous RAM megacell configurations is as follows: Number of bits 128, .. 128K bits Number of words 16, .. 4K Word Size 8, .. 36 bits The following table shows the range of performances for particular Asynchronous RAM configurations under typical conditions. Compiled Asynchronous Dual-port RAM Megacells The Atmel Asynchronous Dual-port RAM has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Asynchronous Dual-port RAM Megacell configurations is as follows: Number of bits 128, .. 16K Number of words(1) 64, .. 2K Word Size(1) 2, .. 36 bits Note: 1. Must be the same for both ports. The following table shows the range of performances for particular Asynchronous Dual- port RAM configurations under typical conditions. Configuration 1K x 8 (8K bits) 2K x 16 (32K bits) 4K x 32 (128K bits) Density (Kbits/mm2) 4 04 05 0 Frequency (MHz) 380 378 293 Dynamic Power C o n f i g u r a t i o n 1 2 8x8( 1 Kb i t s ) 2 5 6x1 6( 4 Kb i t s ) 5 1 2x3 2( 1 6 Kb i t s ) Density (Kbits/mm2) 2 23 23 6 Frequency (MHz) 305 274 248 Dynamic Power

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1306DS–CBIC–09/02 Compiled Two-port RAM Megacells The Atmel Asynchronous Two-port RAM can be configured in multi-bank form, with a maximum of four banks, and can be used to achieve FIFO functions. The range of permitted Asynchronous Two-port RAM Megacell configurations is as follows: Number of bits 128, .. 36K Number of words(1) 64, .. 2K Word Size(1) 2, .. 36 bits Note: 1. Must be the same for both ports. The following table shows the range of performances for particular Asynchronous Two- port RAM configurations under typical conditions. Compiled Synchronous ROM Megacells The Atmel Synchronous ROM is diffusion programmable and is applicable in low power solutions. It can be configured in multi-bank form, with a maximum of four banks. The range of permitted Synchronous ROM Megacell configurations is as follows: Number of bits 256, .. 512K Number of words 64, .. 8K Word Size 4, .. 72 bits The following table shows the range of performances for particular Synchronous ROM configurations under typical conditions. C o n f i g u r a t i o n 2 5 6x8( 2 Kb i t s ) 5 1 2x1 6( 8 Kb i t s ) 1 Kx3 2( 3 2 Kb i t s ) Density (Kbits/mm2) 2 02 42 7 Frequency (MHz) 385 357 294 Dynamic Power Configuration 2K x 8 (16K bits) 4K x 16 (64K bits) 8K x 32 (256K bits) Density (Kbits/mm2) 400 568 669 Frequency (MHz) 198 187 140 Dynamic Power

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