ATAR090

ATAR090_14 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• 2-Kbyte ROM, 256 × 4-bit RAM  12 Bi-directional I/Os  Up to 6 External/Internal Interrupt Sources  Multifunction Timer/Counter with – IR Remote Control Carrier Generator – Bi-phase-, Manchester- and Pulse-width Modulator and Demodulator  Programmable System Clock with Prescaler and Five Different Clock Sources  Wide Supply-voltage Range (1.8 V to 6.5 V)  Very Low Sleep Current (< 1 µA)  32 × 16-bit EEPROM (ATAR890 only)  Synchronous Serial Interface (2-wire, 3-wire)  Watchdog, POR and Brown-out Function  Voltage Monitoring Inclusive Lo_BAT Detection  Flash Controller ATAM893 Available (SSO20)

Description

The ATAR090 and ATAR890 are members of Atmel’s family of 4-bit single-chip micro- controllers. They offer the highest integration for IR and RF data communication and remote-control. The ATAR090 and ATAR890 are suitable for the transmitter side. They contain ROM, RAM, parallel I/O ports, two 8-bit programmable multifunction timer/counters with modulator and demodulator function, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with exter- nal clock input, integrated RC-, 32-kHz crystal- and 4-MHz crystal-oscillators. The ATAR890 has an additional EEPROM as a second chip in one package. Figure 1. Block Diagram

2 K x 8 bit

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Figure 2. Pinning SSO20

7 Input

crystal oscillators. Table 2 provides an overview of the available variants. events. The MARC4 is designed for the high-level programming language qFORTH. high-level language programming without any loss of efficiency or code density. Figure 3. MARC4 Core Table 1. Available Variants of ATAxx9x

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routines and special subroutines accessible with single byte instructions (SCALL). also be held in ROM and are accessed via the MARC4’s built-in table instruction. Figure 4. ROM Map counts. The return stack can also be used as a temporary storage area. definable location and maximum depth.

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4696D–4BMCU–12/04 RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. Expression Stack Pointer (SP) The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. Every post-decre- ment operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset the stack pointer has to be initialized with >SP S0 to allocate the start address of the expression stack area. Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically pre-increments if an element is moved onto the stack, or it post- decrements if an element is removed from the stack. The return stack pointer incre- ments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initial- ized via >RP FCh. RAM Address Registers (X and Y) The X and Y registers are used to address any 4-bit item in RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement address- ing modes arrays in the RAM can be compared, filled or moved Top of Stack (TOS) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus. Condition Code Register (CCR) The 4-bit wide condition code r egister contains the branch, the carry and the interrupt enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. Carry/Borrow (C) The carry/borrow flag indicates that the borrowing or carrying out of the Arithmetic Logic Unit (ALU) occurred during the last arithmetic operation. During shift and rotate opera- tions, this bit is used as a fifth bit. Boolean operations have no affect on the C-flag. Branch (B) The branch flag controls the conditional program branching. Should the branch flag have been set by a previous instruction, a conditional branch will cause a jump. This flag is affected by arithmetic, logic, shift, and rotate operations. Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt rou- tines with the exception of the non-maskable reset. After a reset or while executing the DI instruction, the interrupt enable flag is reset, thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an EI or SLEEP instruction. ALU The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU operations affect the carry/borrow and branch flag in the condition code register (CCR).

Figure 7. ALU Zero-address Operations contain only the operation to be performed and no source or destination address fields. refer to the “MARC4 Programmer’s Guide”. cuted and the current PC is saved on the return stack.

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5 machine cycles depending on the state of the core). Figure 8. Interrupt Handling

registers. An overview of the possible hardware configurations is shown in Table 3. a watchdog time-out, or an external input clock supervisor stage (see Figure 9). ports are set to input mode. Table 2. Interrupt Priority Table Table 3. Hardware Interrupts

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ing reset by any external circuitry representing a resistor of less than 150 kΩ. necessary RAM variables, stack pointers and peripheral configuration registers. Figure 9. Reset Configuration circuitry. For reset generation no external components are needed. the brown-out voltage threshold are programmable via the BOT bit in the SC register. register description for BOT programming.

Figure 10. Brown-out Detection Note: BOT = 1, low brown-out voltage threshold 1.7 V (is reset value). BOT = 0, high brown-out voltage threshold 2.0 V . exactly the same manner as a reset stimulus from any of the above sources. (VIM) is reset in the VMC-register.

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Figure 11. Voltage Monitor Table 4. Voltage Monitor Modes

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or drops below 500 kHz for more than 1 ms. Figure 14. Clock Module Table 5. Clock Modes

f0 ≈ 3.8 MHz. The RC oscillator 1 is selected by default after power-on reset. Figure 15. RC-oscillator 1 is controlled via the OS1, OS0-bit in the SC register and the CCS-bit in the CM-register. the frequency is less than 500 kHz for more than 1 ms. Figure 16. External Input Clock Table 6. Supervisor Function Control Bits

110 E n a b l e

111 D i s a b l e

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connecting a resistor Rext = 360 kΩ (see Figure 17). Figure 17. RC-oscillator 2 Figure 18. 4-MHz Crystal Oscillator

4 MHz

Figure 19. Ceramic Resonator 32-kHz crystal oscillator can not be stopped while the power-down mode is in operation. Figure 20. 32-kHz Crystal Oscillator stage. Writing to this register triggers the synchronization cycle.

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Note: If the bit CCS = 0 in the CM-register the RC-oscillator 1 always stops. Table 7. Core Speed Select Table 8. Oscillator Select

mode by carrying out any interrupt or a reset. example NOP NOP NOP) between the IN or OUT command and the SLEEP command. 32-kHz oscillator is selected, power consumption is extremely low. Table 9. Power-down Modes

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Figure 21. Example of I/O Addressing

Table 10. Peripheral Addresses

2 P2DAT W/R 1111b Port 2 - data register/pin data M2 23

3 SC W 1x11b System configuration register M3 18

4 P4DAT W/R 1111b Port 4 - data register/pin data M2 26

5 P5DAT W/R 1111b Port 5 - data register/pin data M2 25

7 T12SUB W – Data to Timer 1/2 subport M1 20

0 T2C W 0000b Timer 2 control register M1 37

1 T2M1 W 1111b Timer 2 mode register 1 M1 37

2 T2M2 W 1111b Timer 2 mode register 2 M1 39

3 T2CM W 0000b Timer 2 compare mode register M1 40

4 T2CO1 W 1111b Timer 2 compare register 1 M1 40

5 T2CO2 W 1111 1111b Timer 2 compare register 2 (byte) M1 40

8 T1C1 W 1111b Timer 1 control register 1 M1 29

9 T1C2 W x111b Timer 1 control register 2 M1 29

8 ASW W 1111b Auxiliary/switch register ASW 20

9 STB W xxxx xxxxb Serial transmit buffer (byte) M2 51

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address and the Port Control Register (PxCR), to the corresponding auxiliary register. Port 2 4-bit wide bitwise programmable I/O port. pull-ups and programmable interrupt logic. interface to Timer 2, SSI, voltage monitor input and external interrupt input. output. It also opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self-testing and for serial bus applications. pull-up/-down transistor mask option. test logic thus disabling the application firmware. switches off the pull-down transistors during reset. Figure 22. Bi-directional Port 2

useful feature for self testing and for serial bus applications. ble and then the high nibble (see section “Addressing Peripherals”). Table 11. Port 2 Control Register

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Figure 23. Bi-directional Port 5 Figure 24. Port 5 External Interrupts

additional mode to generate an SSI-interrupt. 27 shows the internal interfaces to bi-directional Port 4. Table 12. Port 5 Control Register

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Figure 25. Bi-directional Port 4 and Port 6 Table 13. Port 4 Control Register

(Timer 1,Timer 2) and a Synchronous Serial Interface (SSI). prescaler for Timer 2, the serial interface and the watchdog function.  Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O). data bits into or out of the shift register. Figure 26. UTCM Block Diagram prescaler for Timer 2, the serial interface and the watchdog function.

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switched on and off by software, in the ot her mode the watchdog is active and locked. This mode can only be stopped by carrying out a system reset. programmed via the watchdog control register (WDC). Figure 27. Timer 1 Module Figure 28. Timer 1 and Watchdog

4-MHz oscillator or an external clock is divided by 16. Table 14. Timer 1 Control Bits

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can also be configured as 8-bit timer and separate 4-bit prescaler. an additional clock output (POUT). reset or power-on reset occurs. Table 15. Watchdog Time Control Bits

register data output to generate Bi-phase- or Manchester code. output for a programmable count of pulses. The timer has a 4-bit and an 8-bit compare regi ster for programming the time interval. tecture enables the timer to function for various modes. 8-bit compare register and 4-bit compare register. Figure 29. Timer 2

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(POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode. Figure 30. 12-bit Compare Counter (CM1) supplies the clock output (POUT) with clocks. Figure 31. 8-bit Compare Counter the stop signal for modulator 2.

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Figure 34. Interrupt Timer/Square Wave Generator – Output Toggles with Each Edge Figure 35. Pulse Generator – Timer Output Toggles with the Timer Start if the T2TS-bit Figure 36. Pulse Generator – Timer Toggles with Timer Overflow and Compare Match

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Figure 40. Manchester Modulation PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O). the timer output flip-flop, until overflow occurs all further compare match are ignored. Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit. Figure 41. PWM Modulation

the Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42. Table 16. Timer 2 Clock Select Bits

11 R e s e r v e d

Table 17. Timer 2 Duty Cycle Bits

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Figure 42. DCG Output Signals Table 18. Timer 2 Mode Select Bits

as SSI clock or as a clock for the next counter stage. This bit allows the programmer to preset the Timer 2 output T2O. Table 19. Timer 2 Output Select Bits

1111 T oggle mode: a Timer 2 compare match

6010 SSI output: T2O is used directly as SSI

8000 N o t a l l o w e d

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In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0. can generate an interrupt except on the Timer 2 output mode 7. compare register can generate an interrupt. Table 20. Timer 2 Toggle Mask Bits

4696D–4BMCU–12/04 Synchronous Serial Interface (SSI) SSI Features  2- and 3-wire NRZ  2-wire mode, additional internal 2-wire link for multi-chip packaging solutions  With Timer 2 – Bi-phase modulation – Manchester modulation – Pulse-width demodulation – Burst modulation SSI Peripheral Configuration The synchronous serial interface (SSI) can be used either for serial communication with external devices such as EEPROMs, shift registers, display drivers, other microcontrol- lers, or as a means for generating and capturing on-chip serial streams of data. External data communication takes place via Port 4 (BP4),a multi-functional port which can be software configured by writing the appropriate control word into the P4CR register. The SSI can be configured in any of the following ways: 1. 2-wire external interface for bi-directional data communication with one data ter - minal and one shift clock. The SSI uses Port BP43 as a bi-directional serial data line (SD) and BP40 as a shift clock line (SC). 2. 3-wire external interface for simultaneous input and output of serial data, with a serial input data terminal (SI), a serial output data terminal (SO) and a shift clock (SC). The SSI uses BP40 as a shift clock (SC), while the serial data input (SI) is applied to BP43 (configured in P4CR as input). Serial output data (SO) in this case is passed through to BP42 (configured in P4CR to T2O) via Timer 2 output stage (T2M2 configured in mode 6). 3. Timer/SSI combined modes – the SSI used together with Timer 2 is capable of performing a variety of data modulation and demodulation functions (see section “Timer”). The modulating data is converted by the SSI into a continuous serial stream of data which is in turn modulated in one of the timer functional blocks. 4. Multi-chip link (MCL) – the SSI can also be used as an interchip data interface for use in single package multi-chip modules or hybrids. For such applications, the SSI is provided with two dedicated pads (MCL_SD and MCL_SC) which act as a two-wire chip-to-chip link. The MCL can be activated by the MCL control bit. Should these MCL pads be used by the SSI, the standard SD and SC pins are not required and the corresponding Port 4 ports are available as conventional data ports.

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Figure 43. Block Diagram of the Synchronous Serial Interface continuous bit-streams can be supported. transmission begins after a valid start condition and ends with a valid stop condition. telegram for handshaking purposes (see “MCL Protocol”). be simultaneously received and transmitted if required.

4696D–4BMCU–12/04 Before data can be transferred, the SSI must first be activated. This is performed by means of the SSI reset control (SIR) bit. All further operation then depends on the data directional mode (TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX mode). The control logic ensures that data shif ting is temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will then automatically be set back to ‘1’ and data shifting resumed as soon as the applica- tion software loads the new data into the transmit register (in TX mode) or frees the shift register by reading it into the receive buffer (in RX mode). A further activity status (ACT) bit indicates the present status of serial communication. The ACT bit remains high for the duration of the serial telegram or if MCL stop or start conditions are currently being generated. Both the current SRDY and ACT status can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set high. 8-bit Synchronous Mode Figure 44. 8-bit Synchronous Mode In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface (see section “SSI Peripheral Configuration”). The serial data (SD) is received or trans- mitted in NRZ format, synchronized to either the rising or falling edge of the shift clock (SC). The choice of clock edge is defined by the Serial Mode Control bits (SM0,SM1). It should be noted that the transmission edge refers to the SC clock edge with which the SD changes. To avoid clock skew problems, the incoming serial input data is shifted in with the opposite edge. When used together with one of the timer modulator or demodulator stages, the SSI must be set in the 8-bit synchronous mode 1. In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and the incoming serial data is shifted into the shift register. This first telegram is automati- cally transferred into the receive buffer and the SRDY flag is set to 0 indicating that the receive buffer contains valid data. At the same time an interrupt (if enabled) is gener- ated. The SSI then continues shifting in the following 8-bit telegram. If, during this time the first telegram has been read by the controller, the second telegram will also be trans- ferred in the same way into the receive buffe r and the SSI will continue clocking in the next telegram. Should, however, the first telegram not have been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram in the shift register until a cer- tain point in time when the controller is able to service the receive buffer. In this way no data is lost or overwritten. SC SC DATA SD/TO2 11 0 10100 Bit 7 Bit 0 11 0 10100 Bit 7 Bit 0 Data: 00110101 (Rising edge) (Falling edge)

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contents will overwrite the receive buffer. Figure 45. Example of 8-bit Synchronous Transmit Operation Figure 46. Example of 8-bit Synchronous Receive Operation

to be returned to the device is predetermined by the SSI Status Register (RACK). using the SSI interrupt (IFN = 1) or by interrogating the ACT status. plete the current transfer and terminate the dialog with an MCL stop condition. Figure 47. Example of MCL Transmit Dialog

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Figure 48. Example of MCL Receive Dialog acknowledge-bit which is never expected or transmitted. multiple bus control and bus contention will be omitted at this point. All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit.

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vated (SIR = 0) and cease when deactivated (SIR = 1). all following data bits are blanked. ting the MCL-bit in the SISC register. Figure 51. Multi-chip Link Figure 52. SSI Output Masking Function

(synchronous 8-bit mode only). Table 21. Serial Clock Source Select Bits

01 P O U T / 2

modes for generating bit-streams which are not sub-multiples of 8 bits.

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Table 22. Serial Mode Control Bits SIM = 0, enable serial interrupt. An interrupt is generated. conditions are currently in progress.

shift register and starts shifting with the most significant bit. modes in which the timers and serial interface can work together. data bits into or out of the shift register. Figure 53. Combination Timer 2 and SSI

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Figure 54. Carrier Frequency Burst Modulation with the SSI Internal Data Output Figure 55. Bi-phase Modulation 1

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ure 58 shows an example for a 13-bit Bi-phase telegram. Figure 58. Bi-phase Modulation 2

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provides the clock for transmit and receive operations. Serial Protocol  Data states on the SDA-line change only while SCL is low. STOP condition returns the device to standby mode.  A receiving device generates an acknowledge (A) after the reception of each byte. stop condition to bring the device into a known state. Figure 61. MCL Protocol mode and the SDA line is switched as an input with a pull-up resistor. a write access and a ‘1’ a read access.

4696D–4BMCU–12/04  Control byte format EEPROM The EEPROM has a size of 512 bits and is organized as 32 x 16-bit matrix. To read and write data to and from the EEPROM the serial interface must be used. The interface supports one and two byte write accesses and one to n-byte read accesses to the EEPROM. EEPROM – Operating Modes The operating modes of the EEPROM are defined via the control byte. The control byte contains the row address, the mode control bits and the read/not-write bit that is used to control the direction of the following transfer. A ‘0’ defines a write access and a ‘1’ a read access. The five address bits select one of the 32 rows of the EEPROM memory to be accessed. For all accesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer must be read or overwritten via the serial interface. The two mode control bits C 1 and C2 define in which order the accesses to the buffer are performed: High byte – low byte or low byte – high byte. The EEPROM also supports auto-incre- ment and auto-decrement read operations. After sending the start address with the corresponding mode, consecutive memory ce lls can be read row by row without trans- mission of the row addresses. Two special control bytes enable the complete initialization of EEPROM with ‘0’ or with ‘1’. Write Operations The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the START condition followed by a write control byte and one or two data bytes from the master. It is completed via the STOP condition from the master after the acknowledge cycle. The programming cycle c onsists of an erase cycle (write ‘zeros’) and the write cycle (write ‘ones’). Both cycles together take about 10 ms. Acknowledge Polling If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will not acknowledge until the write cycle is finished. This can be used to detect the end of the write cycle. The master must perform acknowledge polling by sending a start condition followed by the control byte. If the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop con- dition or perform further acknowledge polling sequences. If the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle. Write One Data Byte Write Two Data Bytes Write Control Byte Only Start Control byte Ackn Data byte Ackn Data byte Ackn Stop Start Control byte A Data byte 1 A Stop Start Control byte A Data byte 1 A Data byte 2 A Stop Start Control byte A Stop

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4696D–4BMCU–12/04 Write Control Bytes A: acknowledge; HB: high byte; LB: low byte; R: row address Read Operations The EEPROM allows byte, word and current address read operations. The read opera- tions are initiated in the same way as write operations. Every read access is initiated by sending the START condition followed by the control byte which contains the address and the read mode. When the device has received a read command, it returns an acknowledge, loads the addressed word into the read/write buffer and sends the selected data byte to the master. The master has to acknowledge the received byte if it wants to proceed with the read operation. If two bytes are read out from the buffer the device increments respectively decrements the word address automatically and loads the buffer with the next word. The read mode bi ts determines if the low or high byte is read first from the buffer and if the word address is incremented or decremented for the next read access. If the memory address limit is reached, the data word address will ‘roll over’ and the sequential read will continue. The master can terminate the read operation after every byte by not responding with an acknowledge (N) and by issuing a stop condition. Read One Data Byte Read Two Data Bytes Read n Data Bytes MSB LSB Write low byte first A4 A3 A2 A1 A0 C1 C0 R/NW Row address 0 1 0 Byte order LB(R) HB(R) MSB LSB Write high byte first A4 A3 A2 A1 A0 C1 C0 R/NW Row address 1 0 0 Byte order HB(R) LB(R) Start Control byte A Data byte 1 N Stop Start Control byte A Data byte 1 A Data byte 2 N Stop Start Control byte A Data byte 1 A Data byte 2 A - - - Data byte n N Stop

4696D–4BMCU–12/04 Read Control Bytes A: acknowledge, N: no acknowledge; HB: high byte; LB: low byte, R: row address Initialization After a Reset Condition The EEPROM with the serial interface has its own reset circuitry. In systems with micro- controllers that have their own reset circuitry for power-on reset, watchdog reset or brown-out reset, it may be necessary to bring the U505M into a known state indepen- dent of its internal reset. This is performed by writing to the serial interface. If the U505M acknowledges this sequence it is in a defined state. It may be necessary to perform this sequence twice. MSB LSB Read low byte first, address increment A4 A3 A2 A1 A0 C1 C0 R/NW Row address 0 1 1 Byte order LB(R) HB(R) LB(R+1) HB(R+1) - - - LB(R+n) HB(R+n) MSB LSB Read high byte first, address decrement A4 A3 A2 A1 A0 C1 C0 R/NW Row address 1 0 1 Byte order HB(R) LB(R) HB(R-1) LB(R-1) - - - HB(R-n) LB(R-n) Start Control byte A Data byte 1 N Stop

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4696D–4BMCU–12/04 Absolute Maximum Ratings Voltages are given relative to VSS. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appro- priate logic voltage level (e.g., VDD). Parameters Symbol Value Unit Supply voltage VDD -0.3 to + 6.5 V Input voltage (on any pin) VIN VSS -0.3 ≤ VIN ≤ VDD +0.3 V Output short circuit duration tshort indefinite s Operating temperature range Tamb -40 to +85 °C Storage temperature range Tstg -40 to +130 °C Soldering temperature (t ≤ 10 s) Tsld 260 °C Thermal Resistance Parameter Symbol Value Unit Thermal resistance (SSO20) R thJA 140 K/W DC Operating Characteristics VSS = 0 V, Tamb = -40 to 85°C unless otherwise specified Parameters Test Conditions Symbol Min. Typ. Max. Unit Power Supply Operating voltage at V DD VDD VPOR 6.5 V Active current CPU active fSYSCL = 1 MHz VDD = 1.8 V VDD = 3.0 V VDD = 6.5 V IDD 150 220 600 350 µA µA µA Power down current (CPU sleep, RC oscillator active, 4-MHz quartz oscillator active) fSYSCL = 1 MHz VDD = 1.8 V VDD = 3.0 V VDD = 6.5 V IPD 150 100 µA µA µA Sleep current (CPU sleep, 32-kHz quartz oscillator active 4-MHz quartz oscillator inactive) VDD = 1.8 V VDD = 3.0 V VDD = 6.5 V ISleep 0.4 0.6 0.8 1.3 1.8 µA µA µA Sleep current (CPU sleep, 32-kHz quartz oscillator inactive 4-MHz quartz oscillator inactive) VDD = 1.8 V for ATAR090 VDD = 3.0 V for ATAR090 VDD = 6.5 V for ATAR090 VDD = 6.5 V for ATAR890 ISleep 0.1 0.3 0.5 0.6 0.5 0.8 1.0 µA µA µA µA Pin capacitance Any pin to V SS CL 71 0 p F

4696D–4BMCU–12/04 Note: The Pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller Power-on Reset Threshold Voltage POR threshold voltage BOT = 1 V POR 1.6 1.7 1.8 V POR threshold voltage BOT = 0 V POR 1.75 1.9 2.05 V POR hysteresis V POR 50 mV Voltage Monitor Threshold Voltage VM high threshold voltage V DD > VM, VMS = 1 V MThh 3.0 3.25 V VM high threshold voltage V DD < VM, VMS = 0 V MThh 2.8 3.0 V VM middle threshold voltage V DD > VM, VMS = 1 V MThm 2.6 2.8 V VM middle threshold voltage V DD < VM, VMS = 0 V MThm 2.4 2.6 V VM low threshold voltage V DD > VM, VMS = 1 V MThl 2.2 2.4 V VM low threshold voltage V DD < VM, VMS = 0 V MThl 2.0 2.2 V External Input Voltage VMI V VMI > VBG, VMS = 1 V VMI 1.3 1.4 V VMI V VMI > VBG, VMS = 0 V VMI 1.2 1.3 V All Bi-directional Ports Input voltage LOW V DD = 1.8 to 6.5 V V IL VSS 0.2 × VDD V Input voltage HIGH V DD = 1.8 to 6.5 V V IH 0.8 × VDD VDD V Input LOW current (switched pull-up) VDD = 2.0 V, VDD = 3.0 V, VIL= VSS VDD = 6.5 V IIL -10 -50 -20 -100 -12 -40 -200 µA µA µA Input HIGH current (switched pull-down) VDD = 2.0 V, VDD = 3.0 V, VIH = VDD VDD = 6.5 V IIH 100 200 µA µA µA Input LOW current (static pull-up) V DD = 2.0 V VDD = 3.0 V, VIL= VSS VDD = 6.5 V IIL -20 -80 -300 -50 -160 -600 -100 -320 -1200 µA µA µA Input LOW current (static pull-down) VDD = 2.0 V VDD = 3.0 V, VIH= VDD VDD = 6.5 V IIH 300 160 600 100 320 1200 µA µA µA Input leakage current V IL= VSS IIL 100 nA Input leakage current V IH= VDD IIH 100 nA Output LOW current VOL = 0.2 × VDD VDD = 2.0 V VDD = 3.0 V, VDD = 6.5 V IOL 0.6 1.2 2.5 mA mA mA Output HIGH current VOH = 0.8 × VDD VDD = 2.0 V VDD = 3.0 V, VDD = 6.5 V IOH -0.6 -1.2 -16 -2.5 -24 mA mA mA DC Operating Characteristics (Continued) VSS = 0 V, Tamb = -40 to 85°C unless otherwise specified Parameters Test Conditions Symbol Min. Typ. Max. Unit

62 ATAR090/ATAR890

4696D–4BMCU–12/04 AC Characteristics Supply voltage VDD = 1.8 to 6.5 V, VSS = 0 V, Tamb = 25°C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit Operation Cycle Time System clock cycle VDD = 1.8 to 6.5 V Tamb = -40 to 85°C tSYSCL 500 2000 ns VDD = 2.4 to 6.5 V Tamb = -40 to 85°C tSYSCL 250 2000 ns Timer 2 Input Timing Pin T2I Timer 2 input clock f T2I 5M H z Timer 2 input LOW time Rise/fall time < 10 ns t T2IL 100 ns Timer 2 input HIGH time Rise/fall time < 10 ns t T2IH 100 ns Interrupt Request Input Timing Interrupt request LOW time Rise/fall time < 10 ns t IRL 100 ns Interrupt request HIGH time Rise/fall time < 10 ns t IRH 100 ns External System Clock EXSCL at OSC1, ECM = EN Rise/fall time < 10 ns f EXSCL 0.5 4 MHz EXSCL at OSC1, ECM = DI Rise/fall time < 10 ns f EXSCL 0.02 4 MHz Input HIGH time Rise/fall time < 10 ns t IH 0.1 µs Reset Timing Power-on reset time V DD > VPOR tPOR 1.5 5 ms RC Oscillator 1 Frequency f RcOut1 3.8 MHz Stability VDD = 2.0 to 6.5 V Tamb = -40 to 85°C ∆f/f ±50 % RC Oscillator 2 – External Resistor Frequency R ext = 170 kΩ fRcOut2 4M H z Stability VDD = 2.0 to 6.5 V Tamb = -40 to 85°C ∆f/f ±15 % Stabilization time t S 10 µs 4-MHz Crystal Oscillator (Operating Range VDD = 2.2 V to 6.5 V) Frequency fX 4M H z Start-up time t SQ 5m s Stability ∆f/f -10 10 ppm 32-kHz Crystal Oscillator (Operating Range VDD = 2.0 V to 6.5 V) Frequency fX 32.768 kHz Start-up time t SQ 0.5 s Stability ∆f/f -10 10 ppm Note: 1. Endurance and data retention independent and separately characterized.

4696D–4BMCU–12/04 Crystal Characteristics Figure 62. Crystal Equivalent Circuit External 32-kHz Crystal Parameters Crystal frequency f X 32.768 kHz Serial resistance RS 30 50 k Ω Static capacitance C0 1.5 pF Dynamic capacitance C1 3 fF External 4-MHz Crystal Parameters Crystal frequency f X 4.0 MHz Serial resistance RS 40 150 Ω Static capacitance C0 1.4 3 pF Dynamic capacitance C1 3 fF External 4-MHz Ceramic Resonator Parameters Frequency f X 4.0 MHz Serial resistance RS 8 20 Ω Static capacitance C0 36 45 pF Dynamic capacitance C1 4.4 fF EEPROM Operating current during erase/write cycle I WR 600 1300 µA Endurance(1) Erase-/write cycles at 25°C at 60°C at 85°C ED 500,000 200,000 100,000 1,000,000 Cycles Data erase/write cycle time t DEW 91 2 m s Data retention time(1) At 25°C t DR 10 Y ears Power-up to read operation t PUR 0.2 ms Power-up to write operation t PUW 0.2 ms Serial Interface SCL clock frequency f SC_MCL 100 500 kHz AC Characteristics (Continued) Supply voltage VDD = 1.8 to 6.5 V, VSS = 0 V, Tamb = 25°C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit Note: 1. Endurance and data retention independent and separately characterized. L C1 RS OSCIN OSCOUT Equivalent circuit SCLIN SCLOUT

64 ATAR090/ATAR890

Figure 63. Active Supply Current versus Frequency Figure 64. Power-down Supply Current versus Frequency Figure 65. Sleep Current versus Tamb ATAR090

66 ATAR090/ATAR890

Figure 69. Internal RC Frequency versus VDD – ATAR090 Figure 70. External RC Frequency versus VDD Figure 71. System Clock versus VDD

68 ATAR090/ATAR890

Figure 75. Pull-up Resistor versus VDD Figure 76. Strong Pull-up Resistor versus VDD Figure 77. Output High Current versus VDD - Output High Voltage

70 ATAR090/ATAR890

Figure 81. Output High Current versus Tamb = 25°C, VDD = 6.5 V, VOH = 0.8 × VDD Figure 82. Output Low Current versus Tamb, VDD = 6.5 V, VOL = 0.2 × VDD

available via Port 0 and Port 1 to allow an ex ternal access to the on-chip peripherals. ler (target chip) and emulates the lost ports for the application. to analyze the executed instruction sequences and all the I/O activities. Figure 83. MARC4 Emulation

72 ATAR090/ATAR890

4696D–4BMCU–12/04 Please attach this page to the approval form. Notes: 1. It is required to select an output option for each port pin (Port 2, Port 4, Port 5). 2. Don’t use external components at BP20 that pull to V SS during reset representing a resistor < 150k. Option Settings for Ordering [ ] ATAR090 (-40°C to +85°C) [ ] ATAR890 (-40°C to +85°C) Please select the option settings from the list below and insert ROM CRC. Output(1) Input Output Input Port 2 Port 5 BP20(2) [ ] CMOS [ ] Switched pull-up BP50 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up [ ] Static pull-down [ ] Static pull-down BP21 [ ] CMOS [ ] Switched pull-up BP51 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up [ ] Static pull-down [ ] Static pull-down BP22 [ ] CMOS [ ] Switched pull-up BP52 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up [ ] Static pull-down [ ] Static pull-down BP23 [ ] CMOS [ ] Switched pull-up BP53 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Open drain [P] [ ] Static pull-up [ ] Static pull-down [ ] Static pull-down Port 4 Clock Used [ ] External resistor BP40 [ ] CMOS [ ] Switched pull-up [ ] External clock OSC1 [ ] Open drain [N] [ ] Switched pull-down [ ] External clock OSC2 [ ] Open drain [P] [ ] Static pull-up [ ] 32-kHz crystal [ ] Static pull-down [ ] 4-MHz crystal BP41 [ ] CMOS [ ] Switched pull-up ECM (External Clock Monitor) [ ] Open drain [N] [ ] Switched pull-down [ ] Enable [ ] Open drain [P] [ ] Static pull-up [ ] Disable [ ] Static pull-down Watchdog BP42 [ ] CMOS [ ] Switched pull-up [ ] Softlock [ ] Open drain [N] [ ] Switched pull-down [ ] Hardlock [ ] Open drain [P] [ ] Static pull-up [ ] Static pull-down BP43 [ ] CMOS [ ] Switched pull-up [ ] Open drain [N] [ ] Switched pull-down [ ] Open drain [P] [ ] Static pull-up [ ] Static pull-down

4696D–4BMCU–12/04

Package Information

Ordering Information

Extended Type Number Program Memory Data-EEPROM Package Delivery ATAR090x-yyy-TKQYz 2 kB ROM No SSO20 Taped and reeled ATAR090x-yyy-TKSYz 2 kB ROM No SSO20 Tubes ATAR890x-yyy-TKQYz 2 kB ROM 512 Bit SSO20 Taped and reeled ATAR890x-yyy-TKSYz 2 kB ROM 512 Bit SSO20 Tubes Note: 1. x = Hardware revision yyy = Customer specific ROM-version Y = Lead-free z = Operating temperature range: blank = -40°C to +85°C technical drawings according to DIN specifications Dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 11 0

74 ATAR090/ATAR890

4696D–4BMCU–12/04 Revision History Please note that the referring page numbers in this section are referred to the specific revision mentioned, not to this document. Changes from Rev. 4696A - 03/03 to Rev. 4696B - 01/04 1. Put datasheet in a new template. 2. Figure 5 “RAM Map” on page 5 changed. 3. Table 10 “Peripheral Addresses” on page 21 changed. 4. New heading rows at Table “Absolute Maximum Ratings” on page 60 added. 5. Section “Emulation” on page 71 added. 6. Table “Ordering Information” on page 73 added. 7. Table name on page 72 changed. Changes from Rev. 4696B - 01/04 to Rev. 4696C - 02/04 1. Figure 4 on page 4 changed. 2. “Ordering Information” on page 73 changed. Changes from Rev. 4696C - 02/04 to Rev. 4696D - 12/04 1. Put datasheet in a new template. 2. Lead-free Logo on page 1 added. 3. Section “ROM” on page 4 changed. 4. Section “Interrupt Processing” on pages 7-8 changed. 5. Section “4-MHz” Oscillator on pages 16-17 changed. 6. Section “32-kHz Oscillator” on page 17 changed. 7. Section “Timer 2” on page 30 changed. 8. Table 19 “Timer 2 Output Select Bits” on page 39 changed. 9. Table “AC Characteristics” on pages 62-63 changed. 10. “Option Settings for Ordering” on page 72 changed. 11. “Ordering Information” on page 73 changed.

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