ATAR080 ATMEL | Alldatasheet
Document overview
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Technical content
- Very Low Power Consumption in Active, Power-down and Sleep Mode 2-Kbyte ROM, 256 × 4-bit RAM 12 Bi-directional I/Os Up to 6 External/Internal Interrupt Sources Multifunction Timer/Counter Programmable System-clock with Prescaler and Five Different Clock Sources Wide Supply-voltage Range (1.8 V to 6.5 V) Very Low Sleep Current (< 1 µA) Synchronous Serial Interface (2-wire, 3-wire) Watchdog, POR and Brown-out Function Voltage Monitoring Inclusive Lo_BAT Detection Flash Controller ATAM893 available (SSO20)
Description
The ATAR080 is a member of Atmel’s family of 4-bit single-chip microcontrollers. It contains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter with modulator function, volt age supervision, interval timer with watch- dog function and a sophisticated on-chip clock generation with external clock input, integrated RC-, 32-kHz and 4-MHz crystal-oscillators. Figure 1. Block Diagram
2 K × 8 bit
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Figure 2. Pinning SSO20
events. The MARC4 is designed for the high-level programming language qFORTH. high-level language programming without any loss of efficiency or code density. Figure 3. MARC4 Core
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Figure 4. ROM Map routines and special subroutines accessible with single byte instructions (SCALL). also be held in ROM and are accessed via the MARC4's built-in table instruction. counts. The return stack can also be used as a temporary storage area. definable location and maximum depth.
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4675D–4BMCU–12/04 RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. Expression Stack Pointer (SP) The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. Every post-decre- ment operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate the start address of the expression stack area. Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically pre-increments if an element is moved onto the stack, or it post- decrements if an element is removed from the stack. The return stack pointer incre- ments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initial- ized via >RP FCh. RAM Address Registers (X and Y) The X and Y registers are used to address any 4-bit item in RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement address- ing modes, arrays in the RAM can be compared, filled or moved. Top Of Stack (TOS) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus. Condition Code Register (CCR) The 4-bit wide condition code r egister contains the branch, the carry and the interrupt enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. Carry/Borrow (C) The carry/borrow flag indicates that the borrowing or carrying out of the Arithmetic Logic Unit (ALU) occurred during the last arithmetic operation. During shift and rotate opera- tions, this bit is used as a fifth bit. Boolean operations have no effect on the C-flag. Branch (B) The branch flag controls the conditional program branching. Should the branch flag have been set by a previous instruction a conditional branch will cause a jump. This flag is affected by arithmetic, logic, shift, and rotate operations. Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt rou- tines with the exception of the non-maskable reset. After a reset or on executing the DI instruction, the interrupt enable flag is reset thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an EI or SLEEP instruction.
4675D–4BMCU–12/04 ALU Figure 7. ALU Zero-address Operations The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU operations affect the carry/borrow and branch flag in the condition code register (CCR). I/O Bus The I/O ports and the registers of the peripheral modules are I/O mapped. All communi- cation between the core and the on-chip peripherals take place via the I/O bus and the associated I/O control. With the MARC4 IN and OUT instructions, the I/O bus allows a direct read or write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the section “Peripheral Modules”. The I/O bus is internal and is not accessible by the customer on the final microcontroller device, but it is used as the interfac e for the MARC4 emulation (see section “Emulation”). Instruction Set The MARC4 instruction set is optimized for the high level programming language qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The CPU has an instruction pipeline allow- ing the controller to prefetch an instruction from ROM at the same time as the present instruction is being executed. The MARC4 is a zero address machine, the instructions containing only the operation to be perform ed and no source or destination address fields. The operations are implicitly perfo rmed on the data placed on the stack. There are one and two byte instructions which are executed within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock cycles (SYSCL). Most of the instructions are only one byte long and are executed in a single machine cycle. For more information refer to the “MARC4 Programmer's Guide”. Interrupt Structure The MARC4 can handle interrupts with eight different priority levels. They can be gener- ated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service routine in the ROM (see Table 1 on page 9). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be registered, but the inte rrupt routine only starts after the I flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section “Peripheral Modules”). TOS-1 CCR RAM TOS-2 SP TOS-3 TOS ALU TOS-4
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Figure 8. Interrupt Handling pending register is still set (i.e., the interrupt service routine is not yet finished). cycles depending on the state of the core).
registers. An overview of the possible hardware configurations is shown in Table 2. Table 1. Interrupt Priority Table Table 2. Hardware Interrupts
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an watchdog time-out, or an external input clock supervisor stage (see Figure 9). ports are set to input mode. ing reset by any external circuitry representing a resistor of less than 150 kΩ. necessary RAM variables, stack pointers and peripheral configuration registers. Figure 9. Reset Configuration The ATAR080 has a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed. stopped). In this power-down mode the brown-out detection is disabled.
Figure 10. Brown-out Detection Note: BOT = 1, low brown-out voltage threshold. (1.65 V is the reset value). BOT = 0, high brown-out voltage threshold (1.95 V). register description for BOT programming. the same manner as a reset stimulus from any of the above sources. (VIM) is reset in the VMC-register.
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Figure 11. Voltage Monitor Table 3. Voltage Monitor Modes
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or drops below 500 kHz for more than 1 ms. Figure 14. Clock Module Table 4. Clock Modes
f0 ≈ 3.8 MHz. The RC-oscillator 1 is selected by default after power-on reset. Figure 15. RC-oscillator 1 quency is less than 500 kHz for more than 1 ms. Figure 16. External Input Clock Table 5. Supervisor Function Control Bits
110 E n a b l e
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connecting a resistor Rext = 47 kΩ (see Figure 17). Figure 17. RC-oscillator 2 Figure 18. 4-MHz Crystal Oscillator
4 MHz
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Note: If the bit CCS = 0 in the CM-register the RC-oscillator 1 always stops. Table 6. Core Speed Select Table 7. Oscillator Select
mode by carrying out any interrupt or a reset. example NOP NOP NOP) between the IN or OUT command and the SLEEP command. DD depends on VDD and fsyscl. oscillator is selected, power consumption is extremely low. Table 8. Power-down Modes
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Figure 21. Example of I/O Addressing
Table 9. Peripheral Addresses
2 P2DAT W/R 1111b Port 2 - data register/pin data M2 page 23
3 SC W 1x11b Port 3 - system configuration register M3 page 18
4 P4DAT W/R 1111b Port 4 - data register/pin data M2 page 26
5 P5DAT W/R 1111b Port 5 - data register/pin data M2 page 25
7 T12SUB W — Data to Timer 1/2 subport M1 page 20
0 T2C W 0000b Timer 2 control register M1 page 37
1 T2M1 W 1111b Timer 2 mode register 1 M1 page 37
2 T2M2 W 1111b Timer 2 mode register 2 M1 page 39
3 T2CM W 0000b Timer 2 compare mode register M1 page 40
4 T2CO1 W 1111b Timer 2 compare register 1 M1 page 40
5 T2CO2 W 1111 1111b Timer 2 compare register 2 (byte) M1 page 40
8 T1C1 W 1111b Timer 1 control register 1 M1 page 29
9 T1C2 W x111b Timer 1 control register 2 M1 page 29
8 ASW W 1111b Auxiliary/switch register ASW page 20
9 STB W xxxx xxxxb Serial transmit buffer (byte) M2 page 50
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Port 2 - 4-bit wide bitwise programmable I/O port. pull-ups and programmable interrupt logic. interface to Timer 2, SSI, voltage monitor input and external interrupt input. up/-down transistor mask option. nal test logic thus disabling the application firmware. switches off the pull-down transistors during reset. Figure 22. Bi-directional Port 2
ful feature for self testing and for serial bus applications. then the high nibble (see section “Addressing Peripherals”). Table 10. Port 2 Control Register
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Figure 23. Bi-directional Port 5 Figure 24. Port 5 External Interrupts
additional mode to generate an SSI-interrupt. 26 shows the internal interfaces to bi-directional Port 4. Table 11. Port 5 Control Register
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Figure 25. Bi-directional Port 4 Table 12. Port 4 Control Register
Timer 2 and a Synchronous Serial Interface (SSI). prescaler for Timer 2, the serial interface and the watchdog function. Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O). The SSI operates as a two-wire serial interface or as a shift register for modulation. Figure 26. UTCM Block Diagram prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.
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switched on and off by software, in the ot her mode the watchdog is active and locked. This mode can only be stopped by carrying out a system reset. programmed via the watchdog control register (WDC). Figure 27. Timer 1 Module Figure 28. Timer 1 and Watchdog
4-MHz oscillator or an external clock is divided by 16. Table 13. Timer 1 Control Bits
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of Timer 2 are cascadable as a 12-bit timer or as an 8-bit timer with a 4-bit prescaler. The timer can also be configured as an 8-bit timer and a separate 4-bit prescaler. an additional clock output (POUT). reset or power-on reset occurs. Table 14. Watchdog Time Control Bits
register internal data output to generate Bi-phase- or Manchester-code. output for a programmable count of pulses. The timer has a 4-bit and an 8-bit compare regi ster for programming the time interval. tecture enables the timer to function for various modes. Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). pare register and 4-bit compare register. Figure 29. Timer 2
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(POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode. Figure 30. 12-bit Compare Counter (CM1) supplies the clock output (POUT) with clocks. Figure 31. 8-bit Compare Counter the stop signal for modulator 2.
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Figure 34. Interrupt Timer/Square Wave Generator – Output Toggles with Each Edge Figure 35. Pulse Generator – Timer Output Toggles with the Timer Start if the T2TS-bit Figure 36. Pulse generator – Timer Toggles with Timer Overflow and Compare Match
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Figure 40. Manchester Modulation PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O). the timer output flip-flop, until overflow occurs all further compare match are ignored. Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit. Figure 41. PWM Modulation
the Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42. Table 15. Timer 2 Clock Select Bits
11 R e s e r v e d
Table 16. Timer 2 Duty Cycle Bits
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Figure 42. DCG Output Signals Table 17. Timer 2 Mode Select Bits
as SSI clock or as a clock for the next counter stage. This bit allows the programmer to preset the Timer 2 output T2O. Table 18. Timer 2 Output Select Bits
1111 T oggle mode: a Timer 2 compare match
6010 SSI output: T2O is used directly as SSI
8000 N o t a l l o w e d
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In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0. can generate an interrupt except on the Timer 2 output mode 7. compare register can generate an interrupt. Table 19. Timer 2 Toggle Mask Bits
- 2-wire external interface for bi-directional data communication with one data ter -
line (SD) and BP40 as a shift clock line (SC).
- 3-wire external interface for simultaneous input and output of serial data, with a
stage (T2M2 configured in mode 6).
- Timer/SSI combined modes – the SSI used together with Timer 2 is capable of
which is in turn modulated in one of the timer functional blocks. Figure 43. Block Diagram of the Synchronous Serial Interface
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4675D–4BMCU–12/04 General SSI Operation The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buff- ers – the receive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for intermediate storage of data to be serially output. Both buffers are directly accessable by software. Transferring the parallel buffer data into and out of the shift register is controlled automatically by the SSI control, so that both single byte trans- fers or continuous bit-streams can be supported. The SSI can generate the shift clock (SC) from one of several on-chip clock sources or it can accept an external clock. The external shift clock is output on, or applied to the Port BP40. Selection of an external clock source is performed by the Serial Clock Direction control bit (SCD). In the combinational modes, the required clock is selected by the cor- responding timer mode. The SSI can operate in three data transfer modes – synchronous 8-bit shift mode, 9-bit MCL shift modes or 8-bit pseudo MCL protocol (without acknowledge-bit). External SSI clocking is not supported in these modes. The SSI should thus generate and have full control over the shift clock so that it can always be regarded as an MCL Bus Master device. All directional control of the external data port used by the SSI is handled automatically and is dependent on the transmission direction set by the Serial Data Direction (SDD) control bit. This control bit defines whether the SSI is currently operating in Transmit (TX) mode or Receive (RX) mode. Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. In the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see “MCL Protocol”). At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register and proceeds immediately to shift data serially out. At the same time, incoming data is shifted into the shift register input. This incoming data is automatically loaded into the receive buffer when the complete telegram has been received. Data can, if required thus be simultaneously received and transmitted. Before data can be transferred, the SSI must first be activated. This is performed by means of the SSI reset control (SIR) bit. All further operation then depends on the data directional mode (TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX mode). The control logic ensures that data shif ting is temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will then automatically be set back to '1' and data shifting resumed as soon as the applica- tion software loads the new data into the transmit register (in TX mode) or frees the shift register by reading it into the receive buffer (in RX mode). A further activity status (ACT) bit indicates the present status of serial communication. The ACT bit remains high for the duration of the serial telegram or if MCL stop or start conditions are currently being generated. Both the current SRDY and ACT status can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set high.
4675D–4BMCU–12/04 8-bit Synchronous Mode Figure 44. 8-bit Synchronous Mode In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface (see section “SSI Peripheral Configuration”). The serial data (SD) is received or trans- mitted in NRZ format, synchronized to either the rising or falling edge of the shift clock (SC). The choice of clock edge is defined by the Serial Mode Control bits (SM0,SM1). It should be noted that the transmission edge refers to the SC clock edge with which the SD changes. To avoid clock skew problems, the incoming serial input data is shifted in with the opposite edge. When used together with one of the timer modulator or demodulator stages, the SSI must be set in the 8-bit synchronous mode 1. In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and the incoming serial data is shifted into the shift register. This first telegram is automati- cally transferred into the receive buffer and the SRDY flag is set to 0 indicating that the receive buffer contains valid data. At the same time an interrupt (if enabled) is gener- ated. The SSI then continues shifting in the following 8-bit telegram. If, during this time the first telegram has been read by the controller, the second telegram will also be trans- ferred in the same way into the receive buffe r and the SSI will continue clocking in the next telegram. Should, however, the first telegram not have been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram in the shift register until a cer- tain point in time when the controller is able to service the receive buffer. In this way no data is lost or overwritten. Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch the present contents of the shift register into the receive buffer. This can be used for clocking in a data telegram of less than 8 bits in length. Care should be taken to read out the final complete 8-bit data telegram of a multiple word message before deactivat- ing the SSI (SIR = 1) and terminating the reception. After termination, the shift register contents will overwrite the receive buffer. DATA SD/TO2 110 10100 Bit 7 Bit 0 110 10100 Bit 7 Bit 0 Data: 00110101 SC (rising edge) SC (falling edge)
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Figure 45. Example of 8-bit Synchronous Transmit Operation Figure 46. Example of 8-bit Synchronous Receive Operation to be returned to the device is predetermined by the SSI Status Register (RACK).
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acknowledge-bit which is never expected or transmitted. multiple bus control and bus contention will be omitted at this point. All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. Figure 49. MCL Bus Protocol 1 Bus not busy (1) Both data and clock lines remain HIGH. is HIGH defines a START condition. is HIGH defines a STOP condition. duration of the HIGH period of the clock signal. to acknowledge word receipt.
Figure 50. MCL Bus Protocol 2 of waking the controller out of sleep mode. control bits in P4CR register. conventional bi-directional ports. ceases when deactivated (SIR = 1). all following data bits are blanked.
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Figure 51. SSI Output Masking Function Table 20. Serial Clock Source Select Bits
01 P O U T / 2
(synchronous 8-bit mode only). modes for generating bit-streams which are not sub-multiples of 8 bits. Table 21. Serial Mode Control Bits
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4675D–4BMCU–12/04 Serial Interface Status and Control Register (SISC) Serial Transmit Buffer (STB) – Byte Write The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting with the most significant bit. Serial Receive Buffer (SRB) – Byte Read The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads the content in to the receive buffer when a complete tele- gram has been received. Primary register address: ’A’hex B i t 3B i t 2B i t 1B i t 0 SISC write RACK SIM IFN Reset value: 1111b SISC read – TACK ACT SRDY Reset value: xxxxb RACK Receive ACKnowledge status/control bit for MCL mode RACK = 0, transmit acknowledge in next receive telegram RACK = 1, transmit no acknowledge in last receive telegram TACK Transmit ACKnowledge status/control bit for MCL mode TACK = 0, acknowledge received in last transmit telegram TACK = 1, no acknowledge received in last transmit telegram SIM Serial Interrupt Mask SIM = 1, disable interrupts SIM = 0, enable serial interrupt. An interrupt is generated. IFN Interrupt FuNction IFN = 1, the serial interrupt is generated at the end of the telegram IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes empty/full in transmit/receive mode) SRDY Serial interface buffer ReaDY status flag SRDY = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full SRDY = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty ACT Transmission ACTive status flag ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions are currently in progress. ACT = 0, transmission is inactive Primary register address: ’9’hex STB First write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: xxxxb Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb Primary register address: ’9’hex SRB First read cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb Second read cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: xxxxb
modes in which the timers and serial interface can work together. units work together with the timers and shift the data bits into or out of the shift register. Figure 52. Combination Timer 2 and SSI
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Figure 53. Carrier Frequency Burst Modulation with the SSI Internal Data Output Figure 54. Bi-phase Modulation 1
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Figure 57. Bi-phase Modulation 2 specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. appropriate logic voltage level (e.g., VDD).
4675D–4BMCU–12/04 Electrical Characteristics – DC Operating VSS = 0 V , Tamb = -40°C to +85°C unless otherwise specified Parameters Test Conditions Symbol Min. Typ. Max. Unit Power Supply Operating voltage at V DD VDD VPOR 6.5 V Active current CPU active fSYSCL = 1 MHz VDD = 1.8 V VDD = 3.0 V VDD = 6.5 V IDD 110 180 500 300 µA µA µA Power down current (CPU sleep, RC oscillator active, 4-MHz quartz-oscillator active) fSYSCL = 1 MHz, R = 35k VDD = 1.8 V VDD = 3.0 V VDD = 6.5 V IPD µA µA µA Sleep current (CPU sleep, 32-kHz quartz-oscillator active 4-MHz quartz-oscillator inactive) VDD = 1.8 V VDD = 3.0 V VDD = 6.5 V ISleep 0.4 0.6 0.8 1.8 µA µA µA Sleep current (CPU sleep, 32-kHz quartz-osillator inactive 4-MHz quartz-oscillator inactive) VDD = 1.8 V VDD = 3.0 V VDD = 6.5 V ISleep 0.1 0.3 0.5 0.8 µA µA µA Pin capacitance Any pin to V SS CL 71 0 p F Power-on Reset Threshold Voltage POR threshold voltage BOT = 1 V POR 1.50 1.65 1.80 V POR threshold voltage BOT = 0 V POR 1.75 1.95 2.15 V POR hysteresis V POR 50 mV Voltage Monitor Threshold Voltage VM high threshold voltage V DD > VM, VMS = 1 V MThh 2.95 3.25 V VM high threshold voltage V DD < VM, VMS = 0 V MThh 2.65 2.95 V VM middle threshold voltage V DD > VM, VMS = 1 V MThm 2.55 2.80 V VM middle threshold voltage V DD < VM, VMS = 0 V MThm 2.30 2.55 V VM low threshold voltage V DD > VM, VMS = 1 V MThl 2.15 2.35 V VM low threshold voltage V DD < VM, VMS = 0 V MThl 1.95 2.15 V External Input Voltage VMI VMI > VBG, VMS = 1 V VMI 1.25 1.4 V VMI VMI < VBG, VMS = 0 V VMI 1.1 1.25 V All Bi-directional Ports Input voltage LOW V DD = 1.8 V to 6.5 V V IL VSS 0.2 × VDD V Input voltage HIGH V DD = 1.8 V to 6.5 V V IH 0.8 × VDD VDD V Input LOW current (dynamic pull-up) VDD = 3.0 V, VIL = VSS VDD = 6.5 V IIL -10 -50 -20 -100 -40 -200 µA µA Input HIGH current (dynamic pull-down) VDD = 3.0 V, VIH = VDD VDD = 6.5 V IIH 100 200 µA µA Note: The pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller.
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4675D–4BMCU–12/04 Input LOW current (static pull-up) VDD = 3.0 V , VIL = VSS VDD = 6.5 V IIL -80 -300 -160 -600 -320 -1200 µA µA Input LOW current (static pull-down) VDD = 3.0 V , VIH = VDD VDD = 6.5 V IIH 300 160 600 320 1200 µA µA Input leakage current V IL = VSS IIL 100 nA Input leakage current V IH = VDD IIH 100 nA Output LOW current VOL = 0.2 × VDD VDD = 3.0 V, VDD = 6.5 V IOL mA mA Output HIGH current VOH = 0.8 × VDD VDD = 3.0 V, VDD = 6.5 V IOH -16 -24 mA mA Electrical Characteristics – DC Operating (Continued) VSS = 0 V , Tamb = -40°C to +85°C unless otherwise specified Parameters Test Conditions Symbol Min. Typ. Max. Unit Note: The pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller. Electrical Characteristics – Operation Cycle Time VSS = 0 V , Tamb = -40°C to 85°C Parameters Test Conditions Symbol Min. Typ. Max. Unit System clock cycle VDD = 1.8 V to 6.5 V t SYSCL 0.5 100 µs VDD = 2.4 V to 6.5 V t SYSCL 0.25 100 µs Electrical Characteristics – AC Operating Supply voltage VDD = 1.8 V to 6.5 V, VSS = 0 V , Tamb = 25°C unless otherwise specified Parameters Test Conditions Symbol Min. Typ. Max. Unit Timer 2 Input Timing Pin T2I Timer 2 input clock f T2I 5M H z Timer 2 input LOW time Rise/fall time < 10 ns t T2IL 100 ns Timer 2 input HIGH time Rise/fall time < 10 ns t T2IH 100 ns Interrupt Request Input Timing Interrupt request LOW time Rise/fall time < 10 ns t IRL 100 ns Interrupt request HIGH time Rise/fall time < 10 ns t IRH 100 ns External System Clock EXSCL at OSC1 input ECM = EN, rise/fall time < 10 ns f EXSCL 0.5 8 MHz EXSCL at OSC1 input ECM = DI, rise/fall time < 10 ns f EXSCL 0.02 8 MHz Input HIGH time Rise/fall time < 10 ns t IH 0.1 µs Reset Timing Power-on reset time V DD > VPOR tPOR 1.5 5 ms
Figure 58. Crystal and Equivalent Circuit
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Figure 59. Active Supply Current versus Frequency Figure 60. Power-down Supply Current versus Frequency Figure 61. Sleep Current versus Tamb
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Figure 65. External RC Frequency versus VDD Figure 66. Maximum System Clock versus VDD Figure 67. Internal RC Frequency versus Tamb
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Figure 71. Strong Pull-up Resistor versus VDD Figure 72. Output High Current versus VDD - Output High Voltage Figure 73. Pull-down Resistor versus VDD
64 ATAR080
Figure 77. Output Low Current versus Tamb, VDD = 6.5 V, VOL = 0.2 × VDD available via Port 0 and Port 1 to allow an ex ternal access to the on-chip peripherals. ler (target chip) and emulates the lost ports for the application. to analyze the executed instruction sequences and all the I/O activities. Figure 78. MARC4 Emulation
4675D–4BMCU–12/04 Please attach this page to the approval form. Notes: 1. It is required to select an output option for each port pin (Port 2, Port 4, Port 5). 2. Don’t use external components at BP20 that pull to V SS during reset representing a resistor < 150k. Option Settings for Ordering [X] ATAR080 (-40°C to +85°C) [ ] ATAR080-D (-40°C to +125°C) Please select the option settings from the list below and insert ROM CRC. Output(1) Input Output Input Port 2 Port 5 BP20(2) [ ] CMOS [] Pull-up BP50 [ ] CMOS [] Pull-up [ ] Open drain [N] [] Pull-down [ ] Open drain [N] [] Pull-down [ ] Open drain [P] [] Pull-up Static [ ] Open drain [P] [] Pull-up Static [] Pull-down Static [] Pull-down Static BP21 [ ] CMOS [] Pull-up BP51 [ ] CMOS [] Pull-up [ ] Open drain [N] [] Pull-down [ ] Open drain [N] [] Pull-down [ ] Open drain [P] [] Pull-up Static [ ] Open drain [P] [] Pull-up Static [] Pull-down Static [] Pull-down Static BP22 [ ] CMOS [] Pull-up BP52 [ ] CMOS [] Pull-up [ ] Open drain [N] [] Pull-down [ ] Open drain [N] [] Pull-down [ ] Open drain [P] [] Pull-up Static [ ] Open drain [P] [] Pull-up Static [] Pull-down Static [] Pull-down Static BP23 [ ] CMOS [] Pull-up BP53 [ ] CMOS [] Pull-up [ ] Open drain [N] [] Pull-down [ ] Open drain [N] [] Pull-down [ ] Open drain [P] [] Pull-up Static [ ] Open drain [P] [] Pull-up Static [] Pull-down Static [] Pull-down Static Port 4 ECM (External Clock Monitor) BP40 [ ] CMOS [] Pull-up [ ] Enable [ ] Open drain [N] [] Pull-down [ ] Disable [ ] Open drain [P] [] Pull-up Static Used oscillator [] Pull-down Static [ ] Ext. clock BP41 [ ] CMOS [] Pull-up [ ] Ext. resistor [ ] Open drain [N] [] Pull-down [ ] 4-MHz crystal [ ] Open drain [P] [] Pull-up Static [ ] 32-kHz crystal [] Pull-down Static Pin 8 function BP42 [ ] CMOS [] Pull-up [ ] NRST [ ] Open drain [N] [] Pull-down [ ] OSC2 [ ] Open drain [P] [] Pull-up Static Watchdog [] Pull-down Static [ ] Softlock BP43 [ ] CMOS [] Pull-up [ ] Hardlock [ ] Open drain [N] [] Pull-down [ ] Open drain [P] [] Pull-up Static [] Pull-down Static
66 ATAR080
4675D–4BMCU–12/04
Package Information
Ordering Information
Extended Type Number(1) Program Memory Data-EEPROM Package Delivery ATAR080x-yyy-TKQYz 2 kB ROM No SSO20 Taped and reeled ATAR080x-yyy-TKSYz 2 kB ROM No SSO20 Tubes Note: 1. x = Hardware revision yyy = Customer specific ROM-version z = Operating temperature range: blank = -40°C to +85°C Y = Lead-free technical drawings according to DIN specifications Dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 11 0
4675D–4BMCU–12/04 Revision History Please note that the referring page numbers in this section are referred to the specific revision mentioned, not to this document. Changes from Rev. 4675A - 03/03 to Rev. 4675B - 12/03 1. Put datasheet in a new template. 2. Figure 5 “RAM Map” on page 5 changed. 3. Table 9 “Pheripheral Addresses” on page 21 changed. 4. New heading rows at Table “Absolute Maximum Ratings” on page 54 added. 5. Section “Emulation” on page 58 added. 6. Table “Ordering Information” on page 60 added. 7. Table name on page 59 changed. Changes from Rev. 4675B - 12/03 to Rev. 4675C - 02/04 1. Figure 4 on page 4 changed. 2. Figure 59 to Figure 77 on page 58 to page 64 added. 3. “Ordering Information” on page 66 changed. Changes from Rev. 4675C - 02/04 to Rev. 4675D - 12/04 1. Put datasheet in a new template. 2. Lead-free Logo on page 1 added. 3. Section “ROM” on page 4 changed. 4. Section “Interrupt processing” on page 8 changed. 5. Section “4-MHz” Oscillator on pages 16-17 changed. 6. Section “32-kHz Oscillator” on page 17 changed. 7. Section “Timer 2” on page 30 changed. 8. Table 18 “Timer 2 Output Select Bits” on page 39 changed. 9. “Option Settings for Ordering” on page 65 changed. 10. “Ordering Information” on page 66 changed.
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