ATAM862X-TNSYZF

ATAM862-4_06 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Single Package Fully-integrated 4-bit Flash Microcontroller with RF Transmitter
• Low Power Consumption in Sleep Mode (< 1 µA Typically)
• Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically)
• 2.0 V to 4.0 V Operation Voltage for Single Li-cell Power Supply
• -40°C to +125°C Operation Temperature
• SSO24 Package
• About Seven External Components

Description

The ATAM862-4 is a single package dual-chip circuit. It combines a UHF ASK/FSK transmitter with a 4-bit microcontroller. It supports highly integrated solutions in car access and tire pressure monitoring applications, as well as manifold applications in the industrial and consumer segment. It is available for the transmitting frequency range of 429 MHz to 439 MHz with data rates up to 32 kbaud Manchester coded. For further frequency ranges such as 310 MHz to 330 MHz and 868 MHz to 928 MHz separate datasheets are available. The device contains a flash microcontroller. Figure 1-1. Application Diagram Antenna Micro- controller PLL- Transmitter ATAM862 Keys UHF ASK/FSK Receiver Micro- controller Microcontroller with UHF ASK/FSK Transmitter ATAM862-4 4551F–4BMCU–05/06

4551F–4BMCU–05/06 ATAM862-4 Pin Configuration Figure 2-1. Pinning SSO24 XTAL VS GND ENABLE NRESET BP63/T3I BP20/NTE BP23 BP41/T2I/VMI BP42/T2O BP43/SD/INT3 VSS ANT1 ANT2 PA_ENABLE CLK BP60/T3O OSC2 OSC1 BP50/INT6 BP52/INT1 BP53/INT1 BP40/SC/INT3 VDD Table 2-1. Pin Description: RF Part Pin Symbol Function Configuration XTAL Connection for crystal VS Supply voltage ESD protection circuitry (see Figure 7-5 on page 11) GND Ground ESD protection circuitry (see Figure 7-5 on page 11) ENABLE Enable input XTAL 1.2k VS 1.5k VS 182 µA ENABLE 200k

4551F–4BMCU–05/06 ATAM862-4 CLK Clock output signal for microcontroller, the clock output frequency is set by the crystal to fXTAL/4. PA_ENABLE Switches on power amplifier, used for ASK modulation ANT2 ANT1 Emitter of antenna output stage Open collector antenna output Table 2-1. Pin Description: RF Part (Continued) Pin Symbol Function Configuration CLK VS 100 100 PA_ENABLE 50k Uref=1.1V 20 µA ANT1 ANT2 Table 2-2. Pin Description: Microcontroller Part Name Type Function Alternate Function Pin No. Reset State VDD Supply voltage NA VSS Circuit ground NA BP20 I/O Bi-directional I/O line of Port 2.0 NTE-test mode enable, see section “Master Reset” on page 23 Input BP40 I/O Bi-directional I/O line of Port 4.0 SC-serial clock or INT3 external interrupt input Input BP41 I/O Bi-directional I/O line of Port 4.1 VMI voltage monitor input or T2I external clock input Timer 2 Input BP42 I/O Bi-directional I/O line of Port 4.2 T2O Timer 2 output Input BP43 I/O Bi-directional I/O line of Port 4.3 SD serial data I/O or INT3 external interrupt input Input BP50 I/O Bi-directional I/O line of Port 5.0 INT6 external interrupt input Input BP52 I/O Bi-directional I/O line of Port 5.2 INT1 external interrupt input Input BP53 I/O Bi-directional I/O line of Port 5.3 INT1 external interrupt input Input BP60 I/O Bi-directional I/O line of Port 6.0 T3O Timer 3 output Input BP63 I/O Bi-directional I/O line of Port 6.3 T3I Timer 3 input Input OSC1 I Oscillator input 4-MHz crystal input or 32-kHz crystal input or external clock input or external trimming resistor input Input OSC2 O Oscillator output 4-MHz crystal output or 32-kHz crystal output or external clock input Input NRESET I/O Bi-directional reset pin I/O

4551F–4BMCU–05/06 ATAM862-4 UHF ASK/FSK Transmitter Block

• Integrated PLL Loop Filter
• ESD Protection (4 kV HBM/200 V MM, Except Pin 2: 4 kV HBM/100 V MM) also at ANT1/ANT2
• Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically)
• Modulation Scheme ASK/FSK – FSK Modulation is Achieved by Connecting an Additional Capacitor between the XTAL Load Capacitor and the Open-drain Output of the Modulating Microcontroller
• Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply
• Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -40°C to +125° C
• Single-ended Antenna Output with High Efficient Power Amplifier
• External CLK Output for Clocking the Microcontroller
• 125° C Operation for Tire Pressure Systems

The PLL transmitter block has been developed for the demands of RF low-cost transmission systems, at data rates up to 32 kbaud. The transmitting frequency range is 429 MHz to 439 MHz. It can be used in both FSK and ASK systems.

4551F–4BMCU–05/06 ATAM862-4 Figure 5-1. Block Diagram CLK PA_ENABLE ANT2 ANT1 ENABLE GND VS XTAL VCO LF CP PFD f XTO PLL PA f Power up / down Voltage monitor External input UTCM OSC1 OSC2 I/O bus EEPROM RAM 4-bit CPU core 256 x 4 bit Data direction + alternate function Data direction + interrupt control Port 4 Port 5 Data direction + alternate function Port 6 Timer 3 Brown-out protect. RESET Clock management Timer 1 watchdog timer Timer 2 Serial interface Port 1 Port 2 Data direction T2O SD SC T3O T3I BP10 BP13 BP20/NTE BP21 BP22 BP23 RC oscillators Crystal oscillators

4 K x 8 bit

µC ATAM862

4551F–4BMCU–05/06 ATAM862-4 General Description The fully-integrated PLL transmitter that allows particularly simple, low-cost RF miniature trans- mitters to be assembled. The VCO is locked to 32 × fXTAL, thus, a 13.56 MHz crystal is needed for a 433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator so that only one capacitor together with a crystal con- nected in series to GND are needed as external elements. The crystal oscillator together with the PLL needs maximum < 1 ms until the PLL is locked and the CLK output is stable. A wait time of ≥1 ms until the CLK is used for the microcontroller and the PA is switched on. The power amplifier is an open-collector output delivering a current pulse which is nearly inde- pendent from the load impedance. The delivered output power is controllaed via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50 Ω. A high power efficiency of η= Pout/(IS,PA × VS) of 36% for the power amplifier results when an optimized load impedance of ZLoad = (166 + j223) Ω is used at 3 V supply voltage. Functional Description If ENABLE = L and PA_ENABLE = L, the circuit is in standby mode consuming only a very small amount of current so that a lithium cell used as power supply can work for several years. With ENABLE = H, the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L, only the PLL and the XTO are running and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency. With ENABLE = H and PA_ENABLE = H, the PLL, XTO, CLK driver and the power amplifier are on. With PA_ENABLE, the power amplifier can be switched on and off, which is used to perform the ASK modulation. 7.1 ASK Transmission The PLL transmitter block is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1 ms, then the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means of pin PA_ENABLE. After transmission, PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The PLL transmitter block is switched back to standby mode with ENABLE = L. 7.2 FSK Transmission The PLL transmitter block is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1 ms, then the CLK signal can be taken to clock the microcontroller and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The microcon- troller starts to switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain output port, thus changing the reference frequency of the PLL. If the switch is closed, the output frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The PLL transmitter block is switched back to standby mode with ENABLE = L. The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the fol- lowing tolerances are considered.

4551F–4BMCU–05/06 ATAM862-4 Figure 7-1. Tolerances of Frequency Modulation Using C4 = 9.2 pF ±2%, C5 = 6.8 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray capaci- tances on each side of the crystal of CStray1 = CStray2 = 1 pF ±10%, a parallel capacitance of the crystal of C0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, an FSK deviation of ±21 kHz typical with worst case tolerances of ±16.3 kHz to ±28.8 kHz results. 7.3 CLK Output An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS compatible if the load capacitance is lower than 10 pF. 7.3.1 Clock Pulse Take Over The clock of the crystal oscillator can be used for clocking the microcontroller. the microcontrol- ler block has the special feature of starting with an integrated RC-oscillator to switch on the PLL transmitter block with ENABLE = H, and after 1 ms to assume the clock signal of the transmis- sion IC, so the message can be sent with crystal accuracy. 7.3.2 Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of ZLoad,opt = (166 + j223) Ω. There must be a low resistive path to VS to deliver the DC current. The delivered current pulse of the power amplifier is 9 mA and the maximum output power is delivered to a resistive load of 465 Ω if the 1.0 pF output capacitance of the power amplifier is compensated by the load impedance. An optimum load impedance of: ZLoad = 465 Ω|| j/(2 × π 1.0 pF) = (166 + j223) Ω thus results for the maximum output power of 7.5 dBm. The load impedance is defined as the impedance seen from the PLL transmitter block’s ANT1, ANT2 into the matching network. Do not confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier. Less output power is achieved by lowering the real parallel part of 465 Ω where the parallel imaginary part should be kept constant. Output power measurement can be done with the circuit shown in Figure 7-2 on page 8. Note that the component values must be changed to compensate the individual board parasitics until the PLL transmitter block has the right load impedance ZLoad,opt = (166 + j223) Ω. Also the damp- ing of the cable used to measure the output power must be calibrated. VS XTAL CStray1 CM LM RS CStray2 Crystal equivalent circuit CSwitch

4551F–4BMCU–05/06 ATAM862-4 Figure 7-2. Output Power Measurement 7.4 Application Circuit For the supply-voltage blocking capacitor C3, a value of 68 nF/X7R is recommended (see Figure 7-3 on page 9 and Figure 7-4 on page 10). C1 and C2 are used to match the loop antenna to the power amplifier where C1 typically is 8.2 pF/NP0 and C2 is 6 pF/NP0 (10 pF + 15 pF in series); for C2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility to realize the ZLoad,opt by using standard valued capacitors. C1 forms together with the pins of PLL transmitter block and the PCB board wires a series reso- nance loop that suppresses the 1st harmonic, thus, the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high. L1 (≈50 nH to 100 nH) can be printed on PCB. C4 should be selected so the XTO runs on the load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF load-capacitance crystal. ANT2 ANT1 Rin Power meter C1 = 1n L1 = 33n C2 = 2.2p ZLopt VS Z = 50 Ω 50 Ω

4551F–4BMCU–05/06 ATAM862-4 Figure 7-3. CLK PA_ENABLE ANT2 ANT1 ENABLE GND VS XTAL VCO LF CP PFD f XTO PLL PA f Power up/down VS VS Loop Antenna XTAL BP20/NTE VDD BP42/T2O VSS OSC1 OSC2 BP60/T3O BP50/INT6 BP63/T3I BP23 NRESET BP41/T2I/VMI BP43/SD/ INT3 BP52/INT1 BP53/INT1 BP40/SC/INT3 VS

4551F–4BMCU–05/06 ATAM862-4 Figure 7-4. CLK PA_ENABLE ANT2 ANT1 ENABLE GND VS XTAL VCO LF CP PFD f XTO PLL PA f Power up/down VS VS Loop Antenna XTAL BP20/NTE VDD BP42/T2O VSS OSC1 OSC2 BP60/T3O BP50/INT6 BP63/T3I BP23 NRESET BP41/T2I/VMI BP43/SD/ INT3 BP52/INT1 BP53/INT1 BP40/SC/INT3 VS

4551F–4BMCU–05/06 ATAM862-4 Figure 7-5. ESD Protection Circuit CLK PA_ENABLE ANT2 ANT1 XTAL ENABLE VS GND Absolute Maximum Ratings: RF Part Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage VS V Power dissipation Ptot 100 mW Junction temperature Tj 150 Storage temperature Tstg -55 +125 Ambient temperature Tamb -55 +125 Input voltage VmaxPA_ENABLE -0.3 (VS + 0.3)(1) V Note: Thermal Resistance Parameters Symbol Value Unit Junction ambient RthJA 135 K/W 10. Electrical Characteristics VS = 2.0 V to 4.0 V, Tamb = -40° C to +125°C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25° C. All parameters are referred to GND (Pin 3). Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply current Power down, VENABLE < 0.25 V, -40°C to +85°C VPA-ENABLE < 0.25 V, -85°C to +125°C VPA-ENABLE < 0.25 V, 25°C (100% correlation tested) IS_Off <10 350 nA µA nA Supply current Power up, PA off, VS = 3 V VENABLE > 1.7 V, VPA-ENABLE < 0.25 V IS 3.7 4.8 mA Supply current Power up, VS = 3.0 V VENABLE > 1.7 V, VPA-ENABLE > 1.7 V IS_Transmit 11.6 mA Output power VS = 3.0 V, Tamb = 25°C f = 433.92 MHz, ZLoad = (166 + j233) Ω PRef 5.5 7.5 dBm

4551F–4BMCU–05/06 ATAM862-4 Output power variation for the full temperature range Tamb = -40°C to +85° C VS = 3.0 V VS = 2.0 V ∆PRef ∆PRef -1.5 -4.0 dB dB Output power variation for the full temperature range Tamb = -40°C to +125°C VS = 3.0 V VS = 2.0 V POut = PRef + ∆PRef ∆PRef ∆PRef -2.0 -4.5 dB dB Achievable output-power range Selectable by load impedance POut_typ 7.5 dBm Spurious emission fCLK = f0/128 Load capacitance at Pin CLK = 10 pF fO ± 1× fCLK fO ± 4 × fCLK other spurious are lower -55 -52 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO = f0/32 fXTAL = resonant frequency of the XTAL, CM ≤ 10 fF, load capacitance selected accordingly Tamb = -40°C to +85° C Tamb = -40°C to +125°C fXTO -30 -40 fXTAL +30 +40 ppm ppm PLL loop bandwidth 250 kHz Phase noise of phase comparator Referred to fPC = fXT0, 25 kHz distance to carrier -116 -110 dBc/Hz In loop phase noise PLL 25 kHz distance to carrier -86 -80 dBc/Hz Phase noise VCO at 1 MHz at 36 MHz -94 -125 -90 -121 dBc/Hz dBc/Hz Frequency range of VCO fVCO 429 439 MHz Clock output frequency (CMOS microcontroller compatible) f0/128 MHz Voltage swing at Pin CLK CLoad ≤ 10 pF V0h V0l VS × 0. VS × 0. V V Series resonance R of the crystal Rs 110 Ω Capacitive load at Pin XT0 pF FSK modulation frequency rate Duty cycle of the modulation signal = 50% kHz ASK modulation frequency rate Duty cycle of the modulation signal = 50% kHz ENABLE input Low level input voltage High level input voltage Input current high VIl VIh IIn 1.7 0.25 V V µA PA_ENABLE input Low level input voltage High level input voltage Input current high VIl VIh IIn 1.7 0.25 VS (1) V V µA Note: 1. If VS is higher than 3.6 V, the maximum voltage will be reduced to 3.6 V. 10. Electrical Characteristics (Continued) VS = 2.0 V to 4.0 V, Tamb = -40° C to +125°C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25° C. All parameters are referred to GND (Pin 3). Parameters Test Conditions Symbol Min. Typ. Max. Unit

4551F–4BMCU–05/06 ATAM862-4 11. Microcontroller Block 12. Features

• 4-Kbyte ROM, 256 x 4-bit RAM
• EEPROM Programmable Options
• Read Protection for the EEPROM Program Memory
• 11 Bi-directional I/Os
• Up to Seven External/Internal Interrupt Sources
• Eight Hardware and Software Interrupt Priorities
• Multifunction Timer/Counter - IR Remote Control Carrier Generator - Biphase-, Manchester- and Pulse-width Modulator and Demodulator - Phase Control Function
• Programmable System Clock with Prescaler and Five Different Clock Sources
• Very Low Sleep Current (< 1 µA)
• 2 × 512-bit EEPROM Data Memory
• 256 × 4-bit RAM Data Memory
• Synchronous Serial Interface (2-wire, 3-wire)
• Watchdog, POR and Brown-out Function
• Voltage Monitoring Inclusive Lo_BAT Detect 13. Description The microcontroller is designed with EEPROM cells so it can be programmed several times. To offer full compatibility with each ROM version, the I/O configuration is stored into a separate internal EEPROM block during programming. The configuration is downloaded to the I/Os with every power-on reset. 14. Introduction The microcontroller block is a member of Atmel’s family of 4-bit single-chip microcontrollers. Instead of ROM it contains EEPROM, RAM, parallel I/O ports, two 8-bit programmable multi- function timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with integrated RC-, 32-kHz and 4-MHz crystal oscillators.

4551F–4BMCU–05/06 ATAM862-4 14.1 Differences between ATAM862-4 and ATAR862 Microcontrollers 14.1.1 Program Memory The program memory of the devices is realized as an EEPROM. The memory size for user pro- grams is 4096 bytes. It is programmed as 258 × 16 bytes blocks of data. the implement LOCK-bit function is user-selectable and protects the device from unauthorized read-out of the program memory. 14.1.2 Configuration Memory An additional area of 32 bytes of the EEPROM is used to store information about the hardware configuration. All the options that are selectable for the ROM versions are available to the user. This includes not only the different port options but also the possibilities to select different capac- itors for OSC1 and OSC2, the option to enable or disable the hardlock for the watchdog, the option to select OSC2 instead of OSC1 as external clock input and the option to enable the external clock monitor as a reset source. 14.1.3 Data Memory The microcontroller block contains an internal data EEPROM that is organized as two pages of 32 × 16-bit. To be compatible with the ROM parts, the page used has to be defined within the application software by writing the 2-wire interface (TWI) command "09h" to the EEPROM. This command has no effect for the microcontroller block, if it is left inside the HEX-file for the ROM version. Also for compatibility reasons, the access to the EEPROM is handled via the MCL (serial interface) as in the corresponding ROM parts. 14.1.4 Reset Function During each reset (power-on or brown-out), the I/O configuration is deleted and reloaded with the data from the configuration memory. This leads to a slightly different behavior compared to the ROM versions. Both devices switch their I/Os to input during reset but the ROM part has the mask selected pull-up or pull-down resistors active while the MTP has them removed until the download is finished.

4551F–4BMCU–05/06 ATAM862-4 15. MARC4 Architecture General Description The microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip peripher- als. The CPU is based on the Harvard architecture with physically separated program memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus, are used for parallel communication between ROM, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and a simulta- neous communication to the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. The microcontroller is designed for the high-level programming language qFORTH. The core includes both an expression and a return stack. This architecture enables high-level language programming without any loss of efficiency or code density. Figure 15-1. MARC4 Core 16. Components of MARC4 Core The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction decoder and interrupt controller. The following sections describe each functional block in more detail. Instruction decoder CCR TOS ALU RAM RP X Y Program 256 x 4-bit MARC4 CORE Clock Reset Sleep Memory bus I/O bus Instruction bus Reset System clock Interrupt controller On-chip peripheral modules memory SP PC

4551F–4BMCU–05/06 ATAM862-4 16.1 Program Memory The program memory (EEPROM) is programmable with the customer application program dur- ing the fabrication of the microcontroller. The EEPROM is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 4-Kbytes. The lowest user program memory address segment is taken up by a 512 bytes Zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (SCALL). The corresponding memory map is shown in Figure 16-1. Look-up tables of constants can also be held in ROM and are accessed via the microcontrollers’ built-in table instruction. Figure 16-1. ROM Map of the Microcontroller Block 16.2 RAM The microcontroller block contains a 256 x 4-bit wide static random access memory (RAM), which is used for the expression stack. The return stack and data memory are used for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. 16.2.1 Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arith- metic, I/O and memory reference operations take their operands, and return their results to the expression stack. The microcontroller performs the operations with the top of stack items (TOS and TOS-1). The TOS register contains the top element of the expression stack and works in the same way as an accumulator. This stack is also used for passing parameters between subrou- tines and as a scratch pad area for temporary storage of data. 16.2.2 Return Stack The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used as a temporary storage area. The microcontroller instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks within the RAM have a user definable location and maximum depth. EEPROM (4 K x 8 bit) Zero page FFFh 7FFh 1FFh 000h 1F0h 1F8h 010h 018h 000h 008h 020h 1E8h 1E0h SCALL addresses 140h 180h 040h 0C0h 008h $AUTOSLEEP $RESET INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 1E0h 1C0h 100h 080h page 000h

4551F–4BMCU–05/06 ATAM862-4 16.3.2 RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. 16.3.3 Expression Stack Pointer (SP) The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. Every post-decrement operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate the start address of the expression stack area. 16.3.4 Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically pre-increments if an element is moved onto the stack, or it post-decrements if an element is removed from the stack. The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initialized via >RP FCh. 16.3.5 RAM Address Registers (X and Y) The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement addressing mode arrays in the RAM can be compared, filled or moved. 16.3.6 Top of Stack (TOS) The top of stack register is the accumulator of the microcontroller block. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, EEPROM, RAM or I/O bus. 16.3.7 Condition Code Register (CCR) The 4-bit wide condition code register contains the branch, the carry and the interrupt enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. 16.3.8 Carry/Borrow (C) The carry/borrow flag indicates that the borrowing or carrying out of arithmetic logic unit (ALU) occurred during the last arithmetic operation. During shift and rotate operations, this bit is used as a fifth bit. Boolean operations have no effect on the C-flag. 16.3.9 Branch (B) The branch flag controls the conditional program branching. Should the branch flag has been set by a previous instruction, a conditional branch will cause a jump. This flag is affected by arith- metic, logic, shift, and rotate operations.

4551F–4BMCU–05/06 ATAM862-4 16.3.10 Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset or while executing the DI instruction, the interrupt enable flag is reset, thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an EI or SLEEP instruction. 16.4 ALU The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two ele- ments of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU operations affects the carry/borrow and branch flag in the condition code register (CCR). Figure 16-4. ALU Zero-address Operations 16.5 I/O Bus The I/O ports and the registers of the peripheral modules are I/O mapped. All communication between the core and the on-chip peripherals take place via the I/O bus and the associated I/O control. With the microcontroller IN and OUT instructions, the I/O bus allows a direct read or write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the section“”Peripheral Modules”. The I/O bus is internal and is not accessible by the customer on the final microcontroller device, but it is used as the interface for the microcontroller emulation (see section “Emulation” on page 104). 16.6 Instruction Set The microcontroller instruction set is optimized for the high level programming language qFORTH. Many microcontroller instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The CPU has an instruction pipeline allowing the controller to prefetch an instruction from EEPROM at the same time as the present instruction is being executed. The microcontroller is a zero-address machine, the instructions contain only the operation to be performed and no source or destination address fields. The operations are implicitly performed on the data placed on the stack. There are one- and two-byte instructions which are executed within 1 to 4 machine cycles. A microcontroller machine cycle is made up of two system clock cycles (SYSCL). Most of the instructions are only one byte long and are exe- cuted in a single machine cycle. For more information refer to the “MARC4 Programmer’s Guide”. TOS-1 CCR RAM TOS-2 SP TOS-3 TOS ALU TOS-4

4551F–4BMCU–05/06 ATAM862-4 16.7 Interrupt Structure The microcontroller can handle interrupts with eight different priority levels. They can be gener- ated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service rou- tine in the EEPROM (see Table 16-1 on page 21). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occur- rence will still be registered, but the interrupt routine only started after the I-flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section “Peripheral Modules” on page 32). 16.7.1 Interrupt Processing For processing the eight interrupt levels, the microcontroller includes an interrupt controller with two 8-bit wide interrupt pending and interrupt active registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pend- ing register. If no higher priority interrupt is present in the interrupt active register, it signals the CPU to interrupt the current program execution. If the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the service routine is executed and the current PC is saved on the return stack. An interrupt service routine is completed with the RTI instruction. This instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the pro- gram counter. When the interrupt enable flag is reset (triggering of interrupt routines is disabled), the execution of new interrupt service routines is inhibited but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt is delayed until the inter- rupt enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). It should be noted that automatic stacking of the RBR is not carried out by the hardware and so if ROM banking is used, the RBR must be stacked on the expression stack by the application program and restored before the RTI. After a master reset (power-on, brown-out or watchdog reset), the interrupt enable flag and the interrupt pending and interrupt active register are all reset. 16.7.2 Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou- tine being activated. This is extremely short (taking between 3 to 5 machine cycles depending on the state of the core).

4551F–4BMCU–05/06 ATAM862-4 Figure 16-5. Interrupt Handling Priority level INT5 active INT7 active INT2 pending SWI0 INT2 active INT0 pending INT0 active INT2 RTI RTI INT5 INT3 active INT3 RTI RTI RTI INT7 Time Main / Autosleep Main / Autosleep Table 16-1. Interrupt Priority Interrupt Priority ROM Address Interrupt Opcode Function INT0 Lowest 040h C8h (SCALL 040h) Software interrupt (SWI0) INT1 080h D0h (SCALL 080h) External hardware interrupt, any edge at BP52 or BP53 INT2 0C0h D8h (SCALL 0C0h) Timer 1 interrupt INT3 100h E8h (SCALL 100h) SSI interrupt or external hardware interrupt at BP40 or BP43 INT4 140h E8h (SCALL 140h) Timer 2 interrupt INT5 180h F0h (SCALL 180h) Timer 3 interrupt INT6 1C0h F8h (SCALL 1C0h) External hardware interrupt, at any edge at BP50 or BP51 INT7 Highest 1E0h FCh (SCALL 1E0h) Voltage monitor (VM) interrupt

4551F–4BMCU–05/06 ATAM862-4 16.8 Software Interrupts The programmer can generate interrupts by using the software interrupt instruction (SWI), which is supported in qFORTH by predefined macros named SWI0...SWI7. The software triggered interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prior- itized or lower priority processes scheduled for later execution. 16.9 Hardware Interrupts In the microcontroller block, there are eleven hardware interrupt sources with seven different lev- els. Each source can be masked individually by mask bits in the corresponding control registers. An overview of the possible hardware configurations is shown in Table 16-2. Table 16-2. Hardware Interrupts Interrupt Interrupt Mask Interrupt Source Register Bit INT1 P5CR P52M1, P52M2 P53M1, P53M2 Any edge at BP52 any edge at BP53 INT2 T1M T1IM Timer 1 INT3 SISC SIM SSI buffer full/empty or BP40/BP43 interrupt INT4 T2CM T2IM Timer 2 compare match/overflow INT5 T3CM1 T3CM2 T3C T3IM1 T3IM2 T3EIM Timer 3 compare register 1 match Timer 3 compare register 2 match Timer 3 edge event occurs (T3I) INT6 P5CR P50M1, P50M2 P51M1, P51M2 Any edge at BP50, any edge at BP51 INT7 VCM VIM External/internal voltage monitoring

4551F–4BMCU–05/06 ATAM862-4 17. Master Reset The master reset forces the CPU into a well-defined condition. It is unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power supply, brown-out detection circuitry, watchdog time-out, or an exter- nal input clock supervisor stage (see Figure 17-1). A master reset activation will reset the interrupt enable flag, the interrupt pending register and the interrupt active register. During the power-on reset phase, the I/O bus control signals are set to reset mode, thereby, initializing all on-chip peripherals. All bi-directional ports are set to input mode. Attention: During any reset phase, the BP20/NTE input is driven towards VDD by an additional internal strong pull-up transistor. This pin must not be pulled down to VSS during reset by any external circuitry representing a resistor of less than 150 kΩ. Releasing the reset results in a short call instruction (opcode C1h) to the ROM address 008h. This activates the initialization routine $RESET which in turn has to initialize all necessary RAM variables, stack pointers and peripheral configuration registers (see Table 21-1 on page 34). Figure 17-1. Reset Configuration 17.1 Power-on Reset and Brown-out Detection The microcontroller block has a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed. These circuits ensure that the core is held in the reset state until the minimum operating supply voltage has been reached. A reset condition will also be generated should the supply voltage drop momentarily below the minimum operating level except when a power-down mode is acti- vated (the core is in SLEEP mode and the peripheral clock is stopped). In this power-down mode the brown-out detection is disabled. Two values for the brown-out voltage threshold are programmable via the BOT bit in the SC register. Reset timer VDD CL Power-on reset Internal reset res CL=SYSCL/4 VDD VSS Brown-out detection VDD VSS Watch- dog CWD res Ext. clock supervisor ExIn Pull-up NRST

4551F–4BMCU–05/06 ATAM862-4 A power-on reset pulse is generated by a VDD rise across the default BOT voltage level (1.7 V). A brown-out reset pulse is generated when VDD falls below the brown-out voltage threshold. Two values for the brown-out voltage threshold are programmable via the BOT bit in the SC register. When the controller runs in the upper supply voltage range with a high system clock frequency, the high threshold must be used. When it runs with a lower system clock frequency, the low threshold and a wider supply voltage range may be chosen. For further details, see the electrical specification and the SC register description for BOT programming. Figure 17-2. Brown-out Detection 17.1.1 Watchdog Reset The watchdog’s function can be enabled at the WDC register and triggers a reset with every watchdog counter overflow. To suppress the watchdog reset, the watchdog counter must be regularly reset by reading the watchdog register address (CWD). The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources. 17.1.2 External Clock Supervisor The external input clock supervisor function can be enabled if the external input clock is selected within the CM and SC registers of the clock module. The CPU reacts in exactly the same man- ner as a reset stimulus from any of the above sources. 18. Voltage Monitor The voltage monitor consists of a comparator with internal voltage reference. It is used to super- vise the supply voltage or an external voltage at the VMI pin. The comparator for the supply voltage has three internal programmable thresholds one lower threshold (2.2 V), one middle threshold (2.6 V) and one higher threshold (3.0 V). For external voltages at the VMI pin, the comparator threshold is set to VBG = 1.3 V. The VMS bit indicates if the supervised voltage is below (VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated when the VMS bit is set or reset to detect a rising or falling slope. A voltage monitor interrupt (INT7) is enabled when the interrupt mask bit (VIM) is reset in the VMC register. VDD CPU Reset t BOT = '1' 2.0 V 1.7 V CPU Reset BOT = '0' td td td= 1.5 ms (typically) td BOT = 1, low brown-out voltage threshold 1.7 V (is reset value). BOT = 0, high brown-out voltage threshold 2.0 V.

4551F–4BMCU–05/06 ATAM862-4 Figure 18-1. Voltage Monitor 18.0.1 Voltage Monitor Control/Status Register Primary register address: "F"hex VM2: Voltage monitor Mode bit 2 VM1: Voltage monitor Mode bit 1 VM0: Voltage monitor Mode bit 0 Table 18-1. Voltage Monitor Modes VIM Voltage Interrupt Mask bit VIM = 0, voltage monitor interrupt is enabled VIM = 1, voltage monitor interrupt is disabled VMS Voltage Monitor Status bit VMS = 0, the voltage at the comparator input is below VRef VMS = 1, the voltage at the comparator input is above VRef V DD VM2 Voltage monitor VM1 VM0 VIM VMS res OUT IN BP41/ VMI INT7 VMC : VMST : Bit 3 Bit 2 Bit 1 Bit 0 VMC: Write VM2 VM1 VM0 VIM Reset value: 1111b VMST: Read Reserved VMS Reset value: xx11b VM2 VM1 VM0 Function Disable voltage monitor External (VIM input), internal reference threshold (1.3 V), interrupt with negative slope Not allowed External (VMI input), internal reference threshold (1.3 V), interrupt with positive slope Internal (supply voltage), high threshold (3.0 V), interrupt with negative slope Internal (supply voltage), middle threshold (2.6 V), interrupt with negative slope Internal (supply voltage), low threshold (2.2 V), interrupt with negative slope Not allowed

4551F–4BMCU–05/06 ATAM862-4 If an external input clock is selected, a supervisor circuit monitors the external input and gener- ates a hardware reset if the external clock source fails or drops below 500 kHz for more than 1 ms. Figure 19-1. Clock Module Table 19-1. Clock Modes The clock module generates two output clocks. One is the system clock (SYSCL) and the other the periphery (SUBCL). The SYSCL can supply the core and the peripherals and the SUBCL can supply only the peripherals with clocks. The modes for clock sources are programmable with the OS1 bit and OS0 bit in the SC register and the CCS bit in the CM register. 19.2 Oscillator Circuits and External Clock Input Stage The microcontroller block series consists of four different internal oscillators: two RC-oscillators, one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and one external clock input stage. 19.2.1 RC-oscillator 1 Fully Integrated For timing insensitive applications, it is possible to use the fully integrated RC oscillator 1. It operates without any external components and saves additional costs. The RC-oscillator 1 cen- ter frequency tolerance is better than ±50% over the full temperature and voltage range. The basic center frequency of the RC-oscillator 1 is fO ≈3.8 MHz. The RC oscillator 1 is selected by default after power-on reset. Mode OS1 OS0 Clock Source for SYSCL Clock Source for SUBCL CCS = 1 CCS = 0 RC-oscillator 1 (internal) External input clock Cin/16 RC-oscillator 1 (internal) RC-oscillator 2 with external trimming resistor Cin/16 RC-oscillator 1 (internal) 4-MHz oscillator Cin/16 RC-oscillator 1 (internal) 32-kHz oscillator 32 kHz Ext. clock ExI n ExOu t Stop RC oscillator2 RCOut2 Stop RTrim 4-MHz oscillator 4Out Stop Osci n Oscou t Osci n Oscou t 32-kHz oscillator 32Out Osci n Oscou t RC oscillator 1 RCOut1 Control Stop IN1 IN2 Cin Divide r Sleep WDL Osc- Stop NSTOP CCS CSS1 CSS0 CM: BOT - - - OS1 OS0 SUBCL SYSCL SC: OSC1 OSC2 Configurable Cin/16 kHz

4551F–4BMCU–05/06 ATAM862-4 Figure 19-4. RC-oscillator 2 19.2.4 4-MHz Oscillator The microcontroller block 4-MHz oscillator options need a crystal or ceramic resonator con- nected to the OSC1 and OSC2 pins to establish oscillation. All the necessary oscillator circuitry is integrated, except the actual crystal, resonator, C3 and C4. Figure 19-5. 4-MHz Crystal Oscillator Figure 19-6. Ceramic Resonator 19.2.5 32-kHz Oscillator Some applications require long-term time keeping or low resolution timing. In this case, an on-chip, low power 32-kHz crystal oscillator can be used to generate both the SUBCL and the SYSCL. In this mode, power consumption is greatly reduced. The 32-kHz crystal oscillator can not be stopped while the power-down mode is in operation. RC oscillator 2 RcOut2 Stop RcOut2 Osc-Stop RTrim OSC1 OSC2 Rext VDD 4-MHz oscillator 4Out 4Out OSC1 OSC2 Oscin Oscout XTAL

4 MHz

Cer. Res Configurable

4551F–4BMCU–05/06 ATAM862-4 Figure 19-7. 32-kHz Crystal Oscillator Note: Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to sta- bilize oscillation before the oscillator output is used as system clock. This results in an additional delay of about 4 ms for the 4-MHz crystal and about 500 ms for the 32-kHz crystal. 19.3 Clock Management The clock management register controls the system clock divider and synchronization stage. Writing to this register triggers the synchronization cycle. 19.3.1 Clock Management Register (CM) Auxiliary register address: "3"hex Table 19-3. Core Speed Select 32-kHz oscillator 32Out 32Out OSC1 OSC2 Oscin Oscout XTAL 32 kHz Configurable Bit 3 Bit 2 Bit 1 Bit 0 CM: NSTOP CCS CSS1 CSS0 Reset value: 1111b NSTOP Not STOP peripheral clock NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode CCS Core Clock Select CCS = 1, the internal RC-oscillator 1 generates SYSCL CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the internal RC-oscillator 2 with the external resistor at OSC1 generates SYSCL dependent on the setting of OS0 and OS1 in the system configuration register CSS1 Core Speed Select 1 CSS0 Core Speed Select 0 CSS1 CSS0 Divider Note Reset value

4551F–4BMCU–05/06 ATAM862-4 19.3.2 System Configuration Register (SC) Primary register address: "3"hex Table 19-4. Oscillator Select 20. Power-down Modes The sleep mode is a shut-down condition which is used to reduce the average system power consumption in applications where the microcontroller is not fully utilized. In this mode, the sys- tem clock is stopped. The sleep mode is entered via the SLEEP instruction. This instruction sets the interrupt enable bit (I) in the condition code register to enable all interrupts and stops the core. During the sleep mode the peripheral modules remain active and are able to generate interrupts. The microcontroller exits the sleep mode by carrying out any interrupt or a reset. The sleep mode can only be kept when none of the interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. For standard applications use the $AUTOSLEEP routine to enter the power-down mode. Using the SLEEP instruction instead of the $AUTOSLEEP following an I/O instruction requires to insert 3 non-I/O instruction cycles (for example NOP NOP NOP) between the IN or OUT com- mand and the SLEEP command. The total power consumption is directly proportional to the active time of the microcontroller. For a rough estimation of the expected average system current consumption, the following formula should be used: Itotal (VDD, fsyscl) = ISleep + (IDD × tactive/ttotal) IDD depends on VDD and fsyscl Bit 3 Bit 2 Bit 1 Bit 0 SC: write BOT OS1 OS0 Reset value: 1x11b BOT Brown-Out Threshold BOT = 1, low brown-out voltage threshold (1.7 V) BOT = 0, high brown-out voltage threshold (2.0 V) OS1 Oscillator Select 1 OS0 Oscillator Select 0 Mode OS1 OS0 Input for SUBCL Selected Oscillators Cin/16 RC-oscillator 1 and external input clock Cin/16 RC-oscillator 1 and RC-oscillator 2 Cin/16 RC-oscillator 1 and 4-MHz crystal oscillator 32 kHz RC-oscillator 1 and 32-kHz crystal oscillator Note: If bit CCS = 0 in the CM register the RC-oscillator 1 always stops.

4551F–4BMCU–05/06 ATAM862-4 The microcontroller block has various power-down modes. During the sleep mode the clock for the microcontroller block core is stopped. With the NSTOP bit in the clock management register (CM), it is programmable if the clock for the on-chip peripherals is active or stopped during the sleep mode. If the clock for the core and the peripherals is stopped, the selected oscillator is switched off. An exception is the 32-kHz oscillator, if it is selected it runs continuously indepen- dent of the NSTOP bit. If the oscillator is stopped or the 32-kHz oscillator is selected, power consumption is extremely low. Table 20-1. Power-down Modes 21. Peripheral Modules 21.1 Addressing Peripherals Accessing the peripheral modules takes place via the I/O bus (see Figure 21-1 on page 33). The IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register address- ing scheme has been adopted to enable direct addressing of the primary register. To address the auxiliary register, the access must be switched with an auxiliary switching module. Thus, a single IN (or OUT) to the module address will read (or write into) the module primary register. Accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. Byte wide registers are accessed by multi- ple IN- (or OUT-) instructions. For more complex peripheral modules, with a larger number of registers, extended addressing is used. In this case, a bank of up to 16 subport registers are indirectly addressed with the subport address. The first OUT instruction writes the subport address to the sub address register, the second IN or OUT instruction reads data from or writes data to the addressed subport. Mode CPU Core Osc-Sto p(1) Brown-out Function RC-oscillator 1 RC-oscillator 2 4-MHz Oscillator 32-kHz Oscillator External Input Clock Active RUN NO Active RUN RUN YES Power-down SLEEP NO Active RUN RUN YES SLEEP SLEEP YES STOP STOP RUN STOP Note: 1. Osc-Stop = SLEEP and NSTOP and WDL

4551F–4BMCU–05/06 ATAM862-4 Figure 21-1. Example of I/O Addressing Module ASW Module M1 Module M2 Module M3 Auxiliary Switch Module Primary Reg. (Address Pointer) Subaddress Reg. Bank of Primary Reg. to other modules Subport Fh Subport Eh Subport 1 Subport 0 Primary Reg. Aux. Reg. Primary Reg. I/O bus Example of qFORTH program code Indirect Subport Access (Subport Register Write) 1 Addr. (SPort) Addr. (M1) OUT 2 SPort _Data Addr. (M1) OUT (Subport Register Read) 1 Addr. (SPort) Addr. (M1) OUT 2 Addr. (M1) IN (Subport Register Write Byte) 1 Addr. (SPort) Addr. (M1) OUT (Subport Register Read Byte) 1 Addr. (SPort) Addr. (M1) OUT 2 Addr. (M1) IN (hi) 2 Addr. (M1) IN (lo) 3 Prim._Data Addr. (M2) OUT 4 Addr. (M2) Addr. (ASW) OUT 4 Addr. (M2) Addr. (ASW) OUT Dual Register Access (Primary Register Write) (Auxiliary Register Write) 5 Aux._Data Addr. (M2) OUT (Primary Register Read) 5 Addr. (M2) IN (Auxiliary Register Read) 3 Addr. (M2) IN (Auxiliary Register Write Byte) 4 Addr. (M2) Addr. (ASW) OUT 5 Aux._Data (lo) Addr. (M2) OUT 5 Aux._Data (hi) Addr. (M2) OUT 6 Prim._Data Addr.(M3) OUT Single Register Access (Primary Register Write) 6 Addr. (M3) IN (Primary Register Read) 2 SPort _Data(lo) Addr. (M1) OUT 2 SPort _Data(hi) Addr. (M1) OUT Addr.(ASW) = Auxiliary Switch Module address Addr.(Mx) = Module Mx address Addr.(SPort) = Subport address Prim._Data = Data to be written into Primary Register Aux._Data = Data to be written into Auxiliary Register Prim._Data(lo)= Data to be written into Auxiliary Register (low nibble) Prim._Data(hi) = Data to be written into Auxiliary Register (high nibble) SPort_Data(lo) = Data to be written into SubPort (low nibble) SPort_Data(hi) = Data to be written into SubPort (high nibble) (lo) = SPort_Data (low nibble) (hi) = SPort_Data (high nibble)

4551F–4BMCU–05/06 ATAM862-4 Table 21-1. Peripheral Addresses Port Address Name Write/ Read Reset Value Register Function Module Type P1DAT W/R 1xx1b Port 1 - data register/input data P2DAT W/R 1111b Port 2 - data register/pin data Auxiliary P2CR W 1111b Port 2 - control register SC W 1x11b System configuration register CWD R xxxxb Watchdog reset Auxiliary CM W 1111b Clock management register P4DAT W/R 1111b Port 4 - data register/pin data Auxiliary P4CR W 1111 1111b Port 4 - control register (byte) P5DAT W/R 1111b Port 5 - data register/pin data Auxiliary P5CR W 1111 1111b Port 5 - control register (byte) P6DAT W/R 1xx1b Port 6 - data register/pin data Auxiliary P6CR W 1111b Port 6 - control register (byte) T12SUB W Data to Timer 1/2 subport Subport address T2C W 0000b Timer 2 control register T2M1 W 1111b Timer 2 mode register 1 T2M2 W 1111b Timer 2 mode register 2 T2CM W 0000b Timer 2 compare mode register T2CO1 W 1111b Timer 2 compare register 1 T2CO2 W 1111 1111b Timer 2 compare register 2 (byte) Reserved Reserved T1C1 W 1111b Timer 1 control register 1 T1C2 W x111b Timer 1 control register 2 A WDC W 1111b Watchdog control register B-F Reserved ASW W 1111b Auxiliary/switch register ASW STB W xxxx xxxxb Serial transmit buffer (byte) SRB R xxxx xxxxb Serial receive buffer (byte) Auxiliary SIC1 W 1111b Serial interface control register 1 A SISC W/R 1x11b Serial interface status/control register Auxiliary SIC2 W 1111b Serial interface control register 2 B T3SUB W/R Data to/from Timer 3 subport Subport address T3M W 1111b Timer 3 mode register T3CS W 1111b Timer 3 clock select register T3CM1 W 0000b Timer 3 compare mode register 1 T3CM2 W 0000b Timer 3 compare mode register 2 T3CO1 W 1111 1111b Timer 3 compare register 1 (byte) T3CP R xxxx xxxxb Timer 3 capture register (byte) T3CO2 W 1111 1111b Timer 3 compare register 2 (byte) W 1111b Reserved 7-F Reserved C T3C W 0000b Timer 3 control register T3ST R x000b Timer 3 status register D, E Reserved F VMC W 1111b Voltage monitor control register VMST R xx11b Voltage monitor status register

4551F–4BMCU–05/06 ATAM862-4 22. Bi-directional Ports With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1 and Port 6 have a data width of 2 bits (bit 0 and bit 3). All ports may be used for data input or output. All ports are equipped with Schmitt trigger inputs and a variety of mask options for open-drain, open-source, full-complementary outputs, pull-up and pull-down transistors. All Port Data Regis- ters (PxDAT) are I/O mapped to the primary address register of the respective port address and the Port Control Register (PxCR), to the corresponding auxiliary register. There are five different directional ports available: Port 1 2-bit wide bi-directional port with automatic full bus width direction switching. Port 2 4-bit wide bitwise-programmable I/O port. Port 5 4-bit wide bitwise-programmable bi-directional port with optional strong pull-ups and programmable interrupt logic. Port 4 4-bit wide bitwise-programmable bi-directional port also provides the I/O interface to Timer 2, SSI, voltage monitor input and external interrupt input. Port 6 2-bit wide bitwise-programmable bi-directional port also provides the I/O interface to Timer 3 and external interrupt input. 22.1 Bi-directional Port 1 In Port 1 the data direction register is not independently software programmable, the direction of the complete port being switched automatically when an I/O instruction occurs (see Figure 22-1 on page 36). The port is switched to output mode via an OUT instruction and to input via an IN instruction. The data written to a port will be stored into the output data latches and appears immediately at the port pin following the OUT instruction. After RESET all output latches are set to "1" and the port is switched to input mode. An IN instruction reads the condition of the associ- ated pins. Note: Care must be taken when switching the bi-directional port from output to input. The capacitive pin loading at this port in conjunction with the high resistance pull-ups may cause the CPU to read the contents of the output data register rather than the external input state. To avoid this, one of the following programming techniques should be used: Use two IN instructions and DROP the first data nibble. The first IN switches the port from output to input and the DROP removes the first invalid nibble. The second IN reads the valid pin state. Use an OUT instruction followed by an IN instruction. Via the OUT instruction, the capacitive load is charged or discharged depending on the optional pull-up/pull-down configuration. Write a "1" for pins with pull-up resistors and a "0" for pins with pull-down resistors.

4551F–4BMCU–05/06 ATAM862-4 Figure 22-1. Bi-directional Port 1 22.2 Bi-directional Port 2 As all other bi-directional ports, this port includes a bitwise programmable Control Register (P2CR), which enables the individual programming of each port bit as input or output. It also opens up the possibility of reading the pin condition when in output mode. This is a useful fea- ture for self testing and for serial bus applications. Port 2, however, has an increased drive capability and an additional low resistance pull-up/pull-down transistor mask option. are should be taken connecting external components to BP20/NTE. During any reset phase, the BP20/NTE input is driven towards VDD by an additional internal strong pull-up transistor. This pin must not be pulled down (active or passive) to VSS during reset by any external circuitry repre- senting a resistor of less than 150 kΩ. This prevents the circuit from unintended switching to test mode enable through the application circuitry at pin BP20/NTE. Resistors less than 150 kΩ might lead to an undefined state of the internal test logic thus disabling the application firmware. To avoid any conflict with the optional internal pull-down transistors, BP20 handles the pull-down options in a different way than all other ports. BP20 is the only port that switches off the pull-down transistors during reset. OUT IN Reset I/O Bus D R S Q Q NQ R Master reset P1DATy (Data out) (Direction) BP1y V DD Switched pull-up *) Configurable V DD Static pull-up Static pull-down Switched pull-down

4551F–4BMCU–05/06 ATAM862-4 Figure 22-2. Bi-directional Port 2 22.2.1 Port 2 Data Register (P2DAT) Primary register address: "2"hex * Bit 3 -> MSB, Bit 0 -> LSB 22.2.2 Port 2 Control Register (P2CR) Auxiliary register address: "2"hex Value: 1111b means all pins in input mode Table 22-1. Port 2 Control Register Master reset Q Q BP2y Configurable P2DATy P2CRy I/O Bus D I/O Bus I/O Bus Switched pull-up Static Pull-up (Data out) (Direction) S D S V DD Static Pull-down Switched pull-down V DD Bit 3 * Bit 2 Bit 1 Bit 0 P2DAT3 P2DAT2 P2DAT1 P2DAT0 Reset value: 1111b Bit 3 Bit 2 Bit 1 Bit 0 P2CR3 P2CR2 P2CR1 P2CR0 Reset value: 1111b Code 3 2 1 0 Function x x x 1 BP20 in input mode x x x 0 BP20 in output mode x x 1 x BP21 in input mode x x 0 x BP21 in output mode x 1 x x BP22 in input mode x 0 x x BP22 in output mode 1 x x x BP23 in input mode 0 x x x BP23 in output mode

4551F–4BMCU–05/06 ATAM862-4 22.3.1 Port 5 Data Register (P5DAT) Primary register address: "5"hex 22.3.2 Port 5 Control Register (P5CR) Byte Write Auxiliary register address: "5"hex P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code Bit 3 Bit 2 Bit 1 Bit 0 P5DAT3 P5DAT2 P5DAT1 P5DAT0 Reset value: 1111b Bit 3 Bit 2 Bit 1 Bit 0 First write cycle P51M2 P51M1 P50M2 P50M1 Reset value: 1111b Bit 7 Bit 6 Bit 5 Bit 4 Second write cycle P53M2 P53M1 P52M2 P52M1 Reset value: 1111b Table 22-2. Port 5 Control Register Auxiliary Address: "5"hex, First Write Cycle Second Write Cycle Code 3 2 1 0 Function Code 3 2 1 0 Function x x 1 1 BP50 in input mode – interrupt disabled x x 1 1 BP52 in input mode – interrupt disabled x x 0 1 BP50 in input mode – rising edge interrupt x x 0 1 BP52 in input mode – rising edge interrupt x x 1 0 BP50 in input mode – falling edge interrupt x x 1 0 BP52 in input mode – falling edge interrupt x x 0 0 BP50 in output mode – interrupt disabled x x 0 0 BP52 in output mode – interrupt disabled 1 1 x x BP51 in input mode – interrupt disabled 1 1 x x BP53 in input mode – interrupt disabled 0 1 x x BP51 in input mode – rising edge interrupt 0 1 x x BP53 in input mode – rising edge interrupt 1 0 x x BP51 in input mode – falling edge interrupt 1 0 x x BP53 in input mode – falling edge interrupt 0 0 x x BP51 in output mode – interrupt disabled 0 0 x x BP53 in output mode – interrupt disabled

4551F–4BMCU–05/06 ATAM862-4 22.4 Bi-directional Port 4 The bi-directional Port 4 is a bitwise configurable I/O port and provides the external pins for the Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in exactly the same way as bi-directional Port 2 (see Figure 22-5). Two additional multiplexes allow data and port direction control to be passed over to other internal modules (Timer 2, VM or SSI). The I/O-pins for SC and SD line have an additional mode to generate an SSI-interrupt. All four Port 4 pins can be individually switched by the P4CR register. Figure 22-5 shows the internal interfaces to bi-directional Port 4. Figure 22-5. Bi-directional Port 4 and Port 6 22.4.1 Port 4 Data Register (P4DAT) Primary register address: "4"hex 22.4.2 Port 4 Control Register (P4CR) Byte Write Auxiliary register address: "4"hex P4xM2, P4xM1 – Port 4x Interrupt mode/direction code Master reset Q V DD VDD BPxy Configurable PxDATy I/O Bus D I/O Bus I/O Bus Switched pull-up Switched pull-down S PxCRy S Q D PxMRy POut (Direction) PDir Intx PIn VDD Static pull-up Static pull-down Bit 3 Bit 2 Bit 1 Bit 0 P4DAT3 P4DAT2 P4DAT1 P4DAT0 Reset value: 1111b Bit 3 Bit 2 Bit 1 Bit 0 First write cycle P41M2 P41M1 P40M2 P40M1 Reset value: 1111b Bit 7 Bit 6 Bit 5 Bit 4 Second write cycle P43M2 P43M1 P42M2 P42M1 Reset value: 1111b

4551F–4BMCU–05/06 ATAM862-4 Table 22-3. Port 4 Control Register 22.5 Bi-directional Port 6 The bi-directional Port 6 is a bitwise configurable I/O port and provides the external pins for the Timer 3. As a normal port, it performs in exactly the same way as bi-directional Port 6 (see Fig- ure 22-5 on page 40). Two additional multiplexes allow data and port direction control to be passed over to other internal module (Timer 3). The I/O pin for T3I line has an additional mode to generate a Timer 3 interrupt. All two Port 6 pins can be individually switched by the P6CR register. Figure 22-5 on page 40 shows the internal interfaces to bi-directional Port 6. 22.5.1 Port 6 Data Register (P6DAT) Primary register address: "6"hex 22.5.2 Port 6 Control Register (P6CR) Auxiliary register address: "6"hex P6xM2, P6xM1 – Port 6x Interrupt mode/direction code Auxiliary Address: "4"hex First Write Cycle Second Write Cycle Code 3 2 1 0 Function Code 3 2 1 0 Function x x 1 1 BP40 in input mode x x 1 1 BP42 in input mode x x 1 0 BP40 in output mode x x 1 0 BP42 in output mode x x 0 1 BP40 enable alternate function (SC for SSI) x x 0 x BP42 enable alternate function (T2O for Timer 2) x x 0 0 BP40 enable alternate function (falling edge interrupt input for INT3) 1 1 x x BP43 in input mode 1 1 x x BP41 in input mode 1 0 x x BP43 in output mode 1 0 x x BP41 in output mode 0 1 x x BP43 enable alternate function (SD for SSI) 0 1 x x BP41 enable alternate function (VMI for voltage monitor input) 0 0 x x BP43 enable alternate function (falling edge interrupt input for INT3) 0 0 x x BP41 enable alternate function (T2I external clock input for Timer 2) Bit 3 Bit 2 Bit 1 Bit 0 P6DAT3 P6DAT0 Reset value: 1xx1b Bit 3 Bit 2 Bit 1 Bit 0 P63M2 P63M1 P60M2 P60M0 Reset value: 1111b

4551F–4BMCU–05/06 ATAM862-4 Table 22-4. Port 6 Control Register 22.6 Universal Timer/Counter/ Communication Module (UTCM) The Universal Timer/counter/Communication Module (UTCM) consists of three timers (Timer 1,Timer 2, Timer 3) and a Synchronous Serial Interface (SSI).

• Timer 1 is an interval timer that can be used to generate periodical interrupts and as prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.
• Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O).
• Timer 3 is an 8-bit timer/counter with its own input (T3I) and output (T3O).
• The SSI operates as two wire serial interface or as shift register for modulation and demodulation. The modulator and demodulator units work together with the timers and shift the data bits into or out of the shift register. There is a multitude of modes in which the timers and the serial interface can work together. Auxiliary Address: "6"hex Write Cycle Code 3 2 1 0 Function Code 3 2 1 0 Function x x 1 1 BP60 in input mode 1 1 x x BP63 in input mode x x 1 0 BP60 in output mode 1 0 x x BP63 in output mode x x 0 x BP60 enable alternate port function (T3O for Timer 3) 0 x x x BP63 enable alternate port function (T3I for Timer 3)

4551F–4BMCU–05/06 ATAM862-4 Figure 22-6. UTCM Block Diagram 22.7 Timer 1 The Timer 1 is an interval timer which can be used to generate periodical interrupts and as pres- caler for Timer 2, Timer 3, the serial interface and the watchdog function. The Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or SYSCL. The timer output signal can be used as prescaler clock or as SUBCL and as source for the Timer 1 interrupt. Because of other system requirements, the Timer 1 output T1OUT is syn- chronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes), the output T1OUT is stopped (T1OUT = 0). Nevertheless, the Timer 1 can be active in SLEEP and generate Timer 1 interrupts. The interrupt is maskable via the T1IM bit and the SUBCL can be bypassed via the T1BP bit of the T1C2 register. The time interval for the timer output can be programmed via the Timer 1 control register T1C1. Demodu- lator 3 8-bit Counter 3 Capture 3 Compare 3/1 Compare 3/2 Modu- lator 3 MUX MUX Control Watchdog Interval / Prescaler Timer 1 Timer 3 Modu- lator 2 4-bit Counter 2/1 Compare 2/1 MUX MUX DCG 8-bit Counter 2/2 Compare 2/2 Control Timer 2 MUX 8-bit shift register Receive buffer Transmit buffer Control SSI SCL INT4 INT5 INT2 NRST INT3 POUT TOG2 TOG3 T1OUT SUBCL SYSCL from clock module T3O T3I T2I T2O SC SD I/O bus

4551F–4BMCU–05/06 ATAM862-4 22.7.1 Timer 1 Control Register 1 (T1C1) Address: "7"hex - Subaddress: "8"hex * Bit 3 -> MSB, Bit 0 -> LSB The three bits T1C[2:0] select the divider for Timer 1. The resulting time interval depends on this divider and the Timer 1 input clock source. The timer input can be supplied by the system clock, the 32-kHz oscillator or via the clock management. If the clock management generates the SUBCL, the selected input clock from the RC oscillator, 4-MHz oscillator or an external clock is divided by 16. Table 22-5. Timer 1 Control Bits Bit 3 * Bit 2 Bit 1 Bit 0 T1RM T1C2 T1C1 T1C0 Reset value: 1111b T1RM Timer 1 Restart Mode T1RM = 0, write access without Timer 1 restart Note: If WDL = 0, Timer 1 restart is impossible T1C2 Timer 1 Control bit 2 T1C1 Timer 1 Control bit 1 T1C0 Timer 1 Control bit 0 T1C2 T1C1 T1C0 Divider Time Interval with SUBCL Time Interval with SUBCL = 32 kHz Time Interval with SYSCL = 2/1 MHz SUBCL/2 61 µs 1 µs/2 µs SUBCL/4 122 µs 2 µs/4 µs SUBCL/8 244 µs 4 µs/8 µs SUBCL/16 488 µs 8 µs/16 µs SUBCL/32 0.977 ms 16 µs/32 µs 256 SUBCL/256 7.812 ms 128 µs/256 µs 2048 SUBCL/2048 62.5 ms 1024 µs/2048 µs 16384 SUBCL/16384 500 ms 8192 µs/16384 µs

4551F–4BMCU–05/06 ATAM862-4 22.7.2 Timer 1 Control Register 2 (T1C2) Address: "7"hex - Subaddress: "9"hex * Bit 3 -> MSB, Bit 0 -> LSB 22.7.3 Watchdog Control Register (WDC) Address: "7"hex - Subaddress: "A"hex * Bit 3 -> MSB, Bit 0 -> LSB Both these bits control the time interval for the watchdog reset. Table 22-6. Watchdog Time Control Bits Bit 3 * Bit 2 Bit 1 Bit 0 T1BP T1CS T1IM Reset value: x111b T1BP Timer 1 SUBCL ByPassed T1BP = 1, TIOUT = T1MUX T1BP = 0, T1OUT = SUBCL T1CS Timer 1 input Clock Select T1CS = 1, CL1 = SUBCL (see Figure 22-7 on page 44) T1CS = 0, CL1 = SYSCL (see Figure 22-7 on page 44) T1IM Timer 1 Interrupt Mask T1IM = 1, disables Timer 1 interrupt T1IM = 0, enables Timer 1 interrupt Bit 3 * Bit 2 Bit 1 Bit 0 WDL WDR WDT1 WDT0 Reset value: 1111b WDL WatchDog Lock mode WDL = 1, the watchdog can be enabled and disabled by using the WDR bit WDL = 0, the watchdog is enabled and locked. In this mode the WDR bit has no effect. After the WDL bit is cleared, the watchdog is active until a system reset or power-on reset occurs. WDR WatchDog Run and stop mode WDR = 1, the watchdog is stopped/disabled WDR = 0, the watchdog is active/enabled WDT1 WatchDog Time 1 WDT0 WatchDog Time 0 WDT1 WDT0 Divider Delay Time to Reset with SUBCL = 32 kHz Delay Time to Reset with SYSCL = 2/1 MHz 512 15.625 ms 0.256 ms/0.512 ms 2048 62.5 ms 1.024 ms/2.048 ms 16384 0.5 s 8.2 ms/16.4 ms 131072 4 s 65.5 ms/131 ms

4551F–4BMCU–05/06 ATAM862-4 22.8 Timer 2 8-/12-bit Timer for:

• Interrupt, square-wave, pulse and duty cycle generation
• Baud-rate generation for the internal shift register
• Manchester and Biphase modulation together with the SSI
• Carrier frequency generation and modulation together with the SSI Timer 2 can be used as an interval timer for interrupt generation, as signal generator or as baud-rate generator and modulator for the serial interface. It consists of a 4-bit and an 8-bit up counter stage which both have compare registers. The 4-bit counter stages of Timer 2 are cas- cadable as a 12-bit timer or as an 8-bit timer with 4-bit prescaler. The timer can also be configured as an 8-bit timer and a separate 4-bit prescaler. The Timer 2 input can be supplied via the system clock, the external input clock (T2I), the Timer 1 output clock, the Timer 3 output clock or the shift clock of the serial interface. The external input clock T2I is not synchronized with SYSCL. Therefore, it is possible to use Timer 2 with a higher clock speed than SYSCL. Furthermore, with that input clock the Timer 2 operates in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes) as well as in the POWER-DOWN (CPU core -> sleep and OSC-Stop -> no). All other clock sources supply no clock signal in SLEEP if NSTOP = 0. The 4-bit counter stages of Timer 2 have an additional clock output (POUT). Its output has a modulator stage that allows the generation of pulses as well as the generation and modulation of carrier frequencies. The Timer 2 output can modulate with the shift register data output to generate Biphase- or Manchester code. If the serial interface is used to modulate a bitstream, the 4-bit stage of Timer 2 has a special task. The shift register can only handle bitstream lengths divisible by 8. For other lengths, the 4-bit counter stage can be used to stop the modulator after the right bit-count is shifted out. If the timer is used for carrier frequency modulation, the 4-bit stage works together with an addi- tional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty cycle. The 8-bit counter is used to enable and disable the modulator output for a programmable count of pulses. For programming the time interval, the timer has a 4-bit and an 8-bit compare register. For pro- gramming the timer function, it has four mode and control registers. The comparator output of stage 2 is controlled by a special compare mode register (T2CM). This register contains mask bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a compare match event or the counter overflow. This architecture enables the timer function for various modes. The Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). Both these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register and 4-bit compare register. For 12-bit compare data value: m = x +1 0 ≤ x ≤ 4095 For 8-bit compare data value: n = y +1 0 ≤ y ≤ 255 For 4-bit compare data value: l = z +1 0 ≤ z ≤ 15

4551F–4BMCU–05/06 ATAM862-4

22.10 Timer 2 Output Modes

The signal at the timer output is generated via modulator 2. In the toggle mode, the compare match event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator modes the DCG output is connected to T2O and switched on and off either by the toggle flip-flop output or the serial data line of the SSI. Modulator 2 also has two modes to output the content of the serial interface as Biphase or Manchester code. The modulator output stage can be configured by the output control bits in the T2M2 register. The modulator is started with the start of the shift register (SIR = 0) and stopped either by carry- ing out a shift register stop (SIR = 1) or compare match event of stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler has to be supplied with the internal shift clock (SCL). Figure 22-13. Timer 2 Modulator Output Stage

22.11 Timer 2 Output Signals

22.11.1 Timer 2 Output Mode 1 Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 22-14. Interrupt Timer/Square Wave Generator – the Output Toggles with Each Edge Compare Match Event Toggle RES/SET Biphase/ Manchester modulator T2TOP T2OS2, 1, 0 T2M2 T2O Modulator3 RE FE OMSK SSI CONTROL TOG2 SO DCGO Input Counter 2 T2R Counter 2 CMx INT4 T2O

4551F–4BMCU–05/06 ATAM862-4 22.11.5 Timer 2 Output Mode 5 Manchester Modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester code Figure 22-20. Manchester Modulation 22.11.6 Timer 2 Output Mode 7 In this mode the timer overflow defines the period and the compare register defines the duty cycle. During one period only the first compare match occurrence is used to toggle the timer out- put flip-flop, until the overflow all further compare match are ignored. This avoids the situation that changing the compare register causes the occurrence of several compare match during one period. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit. PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O) Figure 22-21. PWM Modulation

22.12 Timer 2 Registers

Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function. All registers are indirectly addressed using extended addressing as described in section "Addressing Peripherals". The alternate functions of the Ports BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42. TOG2 SC SO T2O 8-bit SR-Data Bit 7 Bit 0 Bit 7 Bit 0 Data: 00110101 255 100 255 0 150 255 0 50 255 0 100 T2R Input clock Counter 2/2 Counter 2/2 OVF2 CM2 INT4 T2O load the next compare value T2CO2=150 load load T T T T T

4551F–4BMCU–05/06 ATAM862-4 22.12.1 Timer 2 Control Register (T2C) Address: "7"hex - Subaddress: "0"hex Table 22-7. Timer 2 Clock Select Bits 22.12.2 Timer 2 Mode Register 1 (T2M1) Address: "7"hex - Subaddress: "1"hex Table 22-8. Timer 2 Duty Cycle Bits Bit 3 Bit 2 Bit 1 Bit 0 T2CS1 T2CS0 T2TS T2R Reset value: 0000b T2CS1 Timer 2 Clock Select bit 1 T2CS0 Timer 2 Clock Select bit 0 T2CS1 T2CS0 Input Clock (CL 2/1) of Counter Stage 2/1 System clock (SYSCL) Output signal of Timer 1 (T1OUT) Internal shift clock of SSI (SCL) Output signal of Timer 3 (TOG3) T2TS Timer 2 Toggle with Start T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R T2R Timer 2 Run T2R = 0, Timer 2 stop and reset T2R = 1, Timer 2 run Bit 3 Bit 2 Bit 1 Bit 0 T2D1 T2D0 T2MS1 T2MS0 Reset value: 1111b T2D1 Timer 2 Duty cycle bit 1 T2D0 Timer 2 Duty cycle bit 0 T2D1 T2D0 Function of Duty Cycle Generator (DCG) Additional Divider Effect Bypassed (DCGO0) Duty cycle 1/1 (DCGO1) Duty cycle 1/2 (DCGO2) Duty cycle 1/3 (DCGO3) T2MS1 Timer 2 Mode Select bit 1 T2MS0 Timer 2 Mode Select bit 0

4551F–4BMCU–05/06 ATAM862-4 Table 22-9. Timer 2 Mode Select Bits 22.12.3 Duty Cycle Generator The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as additional programmable prescaler for Timer 2. Figure 22-22. DCG Output Signals 22.12.4 Timer 2 Mode Register 2 (T2M2) Address: "7"hex - Subaddress: "2"hex Mode T2MS1 T2MS0 Clock Output (POUT) Timer 2 Modes 4-bit counter overflow (OVF1) 12-bit compare counter; the DCG has to be bypassed in this mode 4-bit compare output (CM1) 8-bit compare counter with 4-bit programmable prescaler and duty cycle generator 4-bit compare output (CM1) 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4-bit prescaler run, the counter 2/1 starts after writing mode 3 4-bit compare output (CM1) 8-bit compare counter clocked by SYSCL or the external clock input T2I, 4-bit prescaler stop and resets DCGIN DCGO0 DCGO1 DCGO2 DCGO3 Bit 3 Bit 2 Bit 1 Bit 0 T2TOP T2OS2 T2OS1 T2OS0 Reset value: 1111b T2TOP Timer 2 Toggle Output Preset This bit allows the programmer to preset the Timer 2 output T2O. T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0) T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1) Note: If T2R = 1, no output preset is possible T2OS2 Timer 2 Output Select bit 2 T2OS1 Timer 2 Output Select bit 1 T2OS0 Timer 2 Output Select bit 0

4551F–4BMCU–05/06 ATAM862-4 Table 22-10. Timer 2 Output Select Bits If one of these output modes is used the T2O alternate function of Port 4 must also be activated. 22.12.5 Timer 2 Compare and Compare Mode Registers Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for the 8-bit stage of Timer 2. The timer compares the contents of the compare register current counter value and if it matches it generates an output signal. Dependent on the timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop as SSI clock or as a clock for the next counter stage. In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit com- pare value. In all other modes, the two compare registers work independently as a 4- and 8-bit compare register. When assigned to the compare register a compare event will be suppressed. Output Mode T2OS2 T2OS1 T2OS0 Clock Output Toggle mode: a Timer 2 compare match toggles the output flip-flop (M2) -> T2O Duty cycle burst generator 1: the DCG output signal (DCG0) is given to the output and gated by the output flip-flop (M2) Duty cycle burst generator 2: the DCG output signal (DCGO) is given to the output and gated by the SSI internal data output (SO) Biphase modulator: Timer 2 modulates the SSI internal data output (SO) to Biphase code Manchester modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester code SSI output: T2O is used directly as SSI internal data output (SO) PWM mode: an 8/12-bit PWM mode Not allowed

4551F–4BMCU–05/06 ATAM862-4 22.12.6 Timer 2 Compare Mode Register (T2CM) Address: "7"hex - Subaddress: "3"hex Table 22-11. Timer 2 Toggle Mask Bits 22.12.7 Timer 2 COmpare Register 1 (T2CO1) Address: "7"hex - Subaddress: "4"hex In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0. 22.12.8 Timer 2 COmpare Register 2 (T2CO2) Byte Write Address: "7"hex - Subaddress: "5"hex Bit 3 Bit 2 Bit 1 Bit 0 T2OTM T2CTM T2RM T2IM Reset value: 0000b T2OTM Timer 2 Overflow Toggle Mask bit T2OTM = 0, disable overflow toggle T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output flip-flop (TOG2). If the T2OTM bit is set, only a counter overflow can generate an interrupt except on the Timer 2 output mode 7. T2CTM Timer 2 Compare Toggle Mask bit T2CTM = 0, disable compare toggle T2CTM = 1, enable compare toggle, a match of the counter with the compare register toggles output flip-flop (TOG2). In Timer 2 output mode 7 and when the T2CTM bit is set, only a match of the counter with the compare register can generate an interrupt. T2RM Timer 2 Reset Mask bit T2RM = 0, disable counter reset T2RM = 1, enable counter reset, a match of the counter with the compare register resets the counter T2IM Timer 2 Interrupt Mask bit T2IM = 0, disable Timer 2 interrupt T2IM = 1, enable Timer 2 interrupt Timer 2 Output Mode T2OTM T2CTM Timer 2 Interrupt Source 1, 2, 3, 4, 5 and 6 x Compare match (CM2) 1, 2, 3, 4, 5 and 6 x Overflow (OVF2) x Compare match (CM2) Write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: 1111b First write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: 1111b Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b

4551F–4BMCU–05/06 ATAM862-4 23. Timer 3 23.1

• Two Compare Registers
• Capture Register
• Edge Sensitive Input with Zero Cross Detection Capability
• Trigger and Single Action Modes
• Output Control Modes
• Automatically Modulation and Demodulation Modes
• FSK Modulation
• Pulse Width Modulation (PWM)
• Manchester Demodulation Together with SSI
• Biphase Demodulation Together with SSI
• Pulse-width Demodulation Together with SSI Figure 23-1. Timer 3 Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. The timer can be used as event counter, timer and signal generator. Its output can be programmed as modulator and demodulator for the serial interface. The two compare registers enable various modes of signal generation, modulation and demodulation. The counter can be driven by inter- nal and external clock sources. For external clock sources, it has a programmable edge-sensitive input which can be used as counter input, capture signal input or trigger input. This timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes), this timer input is stopped too. The counter is readable via its capture register while it is running. In capture mode, the counter value can be captured by a programmable capture event from the Timer 3 input or Timer 2 output. 8-bit comparator Compare register 1 RES Capture register 8-bit counter Compare register 2 Control C31 C32 Control T3SM1 NQ D T3RM1 T3IM1 T3TM1 TOG2 T3I T3TM2 T3IM2 T3RM2 T3SM2 NQ D CL3 T3EIM TOG3 INT5 CM31 CM32 : T3M1 : T3M2

4551F–4BMCU–05/06 ATAM862-4 A special feature of this timer is the trigger- and single-action mode. In trigger mode, the counter starts counting triggered by the external signal at its input. In single-action mode, the counter counts only one time up to the programmed compare match event. These modes are very useful for modulation, demodulation, signal generation, signal measurement and phase controlling. For phase controlling, the timer input is protected against negative voltages and has zero-cross detection capability. Timer 3 has a modulator output stage and input functions for demodulation. As modulator it works together with Timer 2 or the serial interface. When the shift register is used for modulation the data shifted out of the register is encoded bitwise. In all demodulation modes, the decoded data bits are shifted automatically into the shift register. 23.2 Timer/Counter Modes Timer 3 has 6 timer modes and 6 modulator/demodulator modes. The mode is set via the Timer 3 Mode Register T3M. In all these modes, the compare register and the compare-mode register belonging to it define the counter value for a compare match and the action of a compare match. A match of the cur- rent counter value with the content of one compare register triggers a counter reset, a Timer 3 interrupt or the toggling of the output flip-flop. The compare mode registers T3M1 and T3M2 contain the mask bits for enabling or disabling these actions. The counter can also be enabled to execute single actions with one or both compare registers. If this mode is set the corresponding compare match event is generated only once after the counter start. Most of the timer modes use their compare registers alternately. After the start has been acti- vated, the first comparison is carried out via the compare register 1, the second is carried out via the compare register 2, the third is carried out again via the compare register 1 and so on. This makes it easy to generate signals with constant periods and variable duty cycle or to generate signals with variable pulse and space widths. If single-action mode is set for one compare register, the comparison is always carried out after the first cycle via the other compare register. The counter can be started and stopped via the control register T3C. This register also controls the initial level of the output before start. T3C contains the interrupt mask for a T3I input interrupt. Via the Timer 3 clock-select register, the internal or external clock source can be selected. This register selects also the active edge of the external input. An edge at the external input T3I can generate also an interrupt if the T3EIM bit is set and the Timer 3 is stopped (T3R = 0) in the T3C register.

4551F–4BMCU–05/06 ATAM862-4 23.2.3 Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2) The counter is driven by an internal or external (T3I) clock source. The output toggle signal of Timer 2 resets the counter. The counter value before the reset is saved in the capture register. If single-action mode is activated for one or both compare registers, the trigger signal restarts the single actions. This mode can be used for frequency measurements or as event counter with time gate (see “Combination Mode 10: Frequency Measurement or Event Counter with Time Gate” on page 91). Figure 23-7. Event Counter with Time Gate 23.2.4 Timer 3 – Mode 4: Timer/Counter The timer runs as timer/counter in mode 1, but its output T3O is used as output for the Timer 2 output signal. 23.2.5 Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input) The Timer 3 runs as timer/counter in mode 2, but its output T3O is used as output for the Timer 2 output signal. 0 0 1 2 3 4 5 6 7 8 9 10 Counter 3 TOG2 T3CP- Register 0 1 0 1 T3I T3R Capture value = 0 Capture value = 11 Capture value = 4

4551F–4BMCU–05/06 ATAM862-4 23.3 Timer 3 Modulator/Demodulator Modes 23.3.1 Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle Flip-Flop (M2) The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare mode registers must be programmed to generate the carrier frequency via the output toggle flip-flop. The output toggle flip-flop of Timer 2 is used to enable or disable the Timer 3 output. Timer 2 can be driven by the toggle output signal of Timer 3 or any other clock source (see “Combination Mode 11: Burst Modulation 1” on page 92). 23.3.2 Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO) The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare mode registers must be programmed to generate the carrier frequency via the output toggle flip-flop. The output (SO) of the SSI is used to enable or disable the Timer 3 output. The SSI should be supplied with the toggle signal of Timer 2 (see “Combination Mode 12: Burst Modula- tion 2” on page 94). 23.3.3 Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO) The two compare registers are used for generating two different time intervals. The SSI internal data output (SO) selects which compare register is used for the output frequency generation. A "0" level at the SSI data output enables the compare register 1. A "1" level enables compare reg- ister 2. The compare- and compare-mode registers must be programmed to generate the two frequencies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer 2. The Timer 3 counter is driven by an internal or external clock source. The Timer 2 counter is driven by the Counter 3 (TOG3) (see “Combination Mode 13: FSK Modulation” on page 94). Figure 23-8. FSK Modulation 0 1 2 3 4 0 1 2 3 4 0 1 2 3 Counter 3 CM31 CM32 SO 4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 T3R 4 0 T3O

4551F–4BMCU–05/06 ATAM862-4 23.4 Timer 3 Modulator for Carrier Frequency Burst Modulation If the output stage operates as pulse-width modulator for the shift register, the output can be stopped with stage 1 of Timer 2. For this task, the timer mode 3 must be used and the prescaler must be supplied by the internal shift clock of the shift register. The modulator can be started with the start of the shift register (SIR = 0) and stopped either by a shift register stop (SIR = 1) or compare match event of stage 1 of Timer 2. For this task, the Timer 2 must be used in mode 3 and the prescaler stage must be supplied by the internal shift clock of the shift register. Figure 23-13. Modulator 3 23.5 Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals The demodulator stage of Timer 3 can be used to decode Biphase, Manchester and pulse-width-coded signals. Figure 23-14. Timer 3 Demodulator 3 Set Res T3O T3TOP OMSK TOG3 SO SSI/ Control MUX T3M Timer 3 Mode T3O

6 MUX 1

7 MUX 2

9 MUX 3

4551F–4BMCU–05/06 ATAM862-4 23.6 Timer 3 Registers 23.6.1 Timer 3 Mode Register (T3M) Address: "B"hex - Subaddress: "0"hex Table 23-1. Timer 3 Mode Seledt Bits Note: 1. In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All other SSI modes are not allowed. Bit 3 Bit 2 Bit 1 Bit 0 T3M3 T3M2 T3M1 T3M0 Reset value: 1111b T3M3 Timer 3 Mode select bit 3 T3M2 Timer 3 Mode select bit 2 T3M1 Timer 3 Mode select bit 1 T3M0 Timer 3 Mode select bit 0 Mode T3M3 T3M2 T3M1 T3M0 Timer 3 Modes Timer/counter with a read access Timer/counter, external capture and external trigger restart mode (T3I) Timer/counter, internal capture and internal trigger restart mode (TOG2) Timer/counter mode 1 without output (T2O -> T3O) Timer/counter mode 2 without output (T2O -> T3O) Burst modulation with Timer 2 (M2) Burst modulation with shift register (SO) FSK modulation with shift register (SO) Pulse-width modulation with shift register (SO) and Timer 2 (TOG2), internal trigger restart (SCO) -> counter reset Manchester demodulation/pulse-width demodulation (1) (T2O -> T3O) Biphase demodulation (T2O -> T3O) Timer/counter with external capture mode (T3I) Not allowed Not allowed Not allowed Not allowed

4551F–4BMCU–05/06 ATAM862-4 23.6.2 Timer 3 Control Register 1 (T3C) Write Primary register address: "C"hex - Write 23.6.3 Timer 3 Status Register 1 (T3ST) Read Primary register address: "C"hex - Read Note: The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST. Bit 3 Bit 2 Bit 1 Bit 0 Write T3EIM T3TOP T3TS T3R Reset value: 0000b T3EIM Timer 3 Edge Interrupt Mask T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I) T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I) T3TOP Timer 3 Toggle Output Preset T3TOP = 0, sets toggle output (M3) to "0" T3TS Timer 3 Toggle with Start . T3TS = 0, Timer 3 output is not toggled during the start T3R Timer 3 Run Bit 3 Bit 2 Bit 1 Bit 0 Read T3ED T3C2 T3C1 Reset value: x000b T3ED Timer 3 Edge Detect This bit will be set by the edge-detect logic of Timer 3 input (T3I) T3C2 Timer 3 Compare 2 This bit will be set when a match occurs between Counter 3 and T3CO2 T3C1 Timer 3 Compare 1 This bit will be set when a match occurs between Counter 3 and T3CO1

4551F–4BMCU–05/06 ATAM862-4 23.6.4 Timer 3 Clock Select Register (T3CS) Address: "B"hex - Subaddress: "1"hex Table 23-2. Timer 3 Edge Select Bits Table 23-3. Timer 3 Clock Select Bits 23.6.5 Timer 3 Compare- and Compare-mode Register Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3. The timer compares the content of the compare register with the current counter value. If both match, it generates a signal. This signal can be used for the counter reset, to generate a timer interrupt, for toggling the output flip-flop, as SSI clock or as clock for the next counter stage. For each compare register, a compare-mode register exists. These registers contain mask bits to enable or disable the generation of an interrupt, a counter reset, or an output toggling with the occurrence of a compare match of the corresponding compare register. The mask bits for acti- vating the single-action mode can also be located in the compare mode registers. When assigned to the compare register a compare event will be suppressed. Bit 3 Bit 2 Bit 1 Bit 0 T3CS T3E1 T3E0 T3CS1 T3CS0 Reset value: 1111b T3E1 Timer 3 Edge select bit 1 T3E0 Timer 3 Edge select bit 0 T3E1 T3E0 Timer 3 Input Edge Select (T3I) Positive edge at T3I pin Negative edge at T3I pin Each edge at T3I pin T3CS1 Timer 3 Clock Source select bit 1 T3CS0 Timer 3 Clock Source select bit 0 T3CS1 TCS0 Counter 3 Input Signal (CL3) System clock (SYSCL) Output signal of Timer 2 (POUT) Output signal of Timer 1 (T1OUT) External input signal from T3I edge detect

4551F–4BMCU–05/06 ATAM862-4 23.6.6 Timer 3 Compare-Mode Register 1 (T3CM1) Address: "B"hex - Subaddress: "2"hex T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1 23.6.7 Timer 3 Compare Mode Register 2 (T3CM2) Address: "B"hex - Subaddress: "3"hex T3CM2 contains the mask bits for the match event of Counter 3 compare register 2 Bit 3 Bit 2 Bit 1 Bit 0 T3CM1 T3SM1 T3TM1 T3RM1 T3IM1 Reset value: 0000b T3SM1 Timer 3 Single action Mask bit 1 T3SM1 = 0, disables single-action compare mode T3SM1 = 1, enables single-compare mode. After this bit is set, the compare register (T3CO1) is used until the next compare match. T3TM1 Timer 3 compare Toggle action Mask bit 1 T3TM1 = 0, disables compare toggle T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare register (T3CO1) toggles the output flip-flop (TOG3). T3RM1 Timer 3 Reset Mask bit 1 T3RM1 = 0, disables counter reset T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare register (T3CO1) resets the Counter 3. T3IM1 Timer 3 Interrupt Mask bit 1 T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register. T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register. Bit 3 Bit 2 Bit 1 Bit 0 T3CM2 T3SM2 T3TM2 T3RM2 T3IM2 Reset value: 0000b T3SM2 Timer 3 Single action Mask bit 2 T3SM2 = 0, disables single-action compare mode T3SM2 = 1, enables single-compare mode. After this bit is set, the compare register (T3CO2) is used until the next compare match. T3TM2 Timer 3 compare Toggle action Mask bit 2 T3TM2 = 0, disables compare toggle T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare register (T3CO2) toggles the output flip-flop (TOG3). T3RM2 Timer 3 Reset Mask bit 2 T3RM2 = 0, disables counter reset T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare register (T3CO2) resets the Counter 3. T3IM2 Timer 3 Interrupt Mask bit 2 T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register. T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register.

4551F–4BMCU–05/06 ATAM862-4 The compare registers and corresponding counter reset masks can be used to program the counter time intervals and the toggle masks can be used to program output signal. The sin- gle-action mask can also be used in this mode. It starts operating after the timer started with T3R. 23.6.8 Timer 3 COmpare Register 1 (T3CO1) Byte Write Address: "B"hex - Subaddress: "4"hex 23.6.9 Timer 3 COmpare Register 2 (T3CO2) Byte Write Address: "B"hex - Subaddress: "5"hex 23.7 Timer 3 Capture Register The counter content can be read via the capture register. There are two ways to use the capture register. In modes 1 and 4, it is possible to read the current counter value directly out of the cap- ture register. In the capture modes 2, 3, 5 and 12, a capture event like an edge at the Timer 3 input or a signal from Timer 2 stores the current counter value into the capture register. This counter value can be read from the capture register. 23.7.1 Timer 3 CaPture Register (T3CP) Byte Read Address: "B"hex - Subaddress: "4"hex High Nibble Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b Low Nibble First write cycle Bit 3 Bit 2 Bit 15 Bit 0 Reset value: 1111b High Nibble Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b Low Nibble First write cycle Bit 3 Bit 2 Bit 15 Bit 0 Reset value: 1111b High Nibble First read cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb Low Nibble Second read cycle Bit 3 Bit 2 Bit 15 Bit 0 Reset value: xxxxb

4551F–4BMCU–05/06 ATAM862-4 23.8 Synchronous Serial Interface (SSI) 23.8.1 SSI Features:

• With Timer 1 – 2- and 3-wire NRZ – 2-wire mode multi-chip link mode (MCL), additional internal 2-wire link for multi-chip packaging solutions
• With Timer 2 – Biphase modulation – Manchester modulation – Pulse-width demodulation – Burst modulation
• With Timer 3 – Pulse-width modulation (PWM) – FSK modulation – Biphase demodulation – Manchester demodulation – Pulse-width demodulation – Pulse position Demodulation 23.8.2 SSI Peripheral Configuration The synchronous serial interface (SSI) can be used either for serial communication with external devices such as EEPROMs, shift registers, display drivers, other microcontrollers, or as a means for generating and capturing on-chip serial streams of data. External data communication takes place via the Port 4 (BP4),a multi-functional port which can be software configured by writ- ing the appropriate control word into the P4CR register. The SSI can be configured in any of the following ways: 2-wire external interface for bi-directional data communication with one data terminal and one shift clock. The SSI uses the Port BP43 as a bi-directional serial data line (SD) and BP40 as shift clock line (SC). 3-wire external interface for simultaneous input and output of serial data, with a serial input data terminal (SI), a serial output data terminal (SO) and a shift clock (SC). The SSI uses BP40 as shift clock (SC), while the serial data input (SI) is applied to BP43 (configured in P4CR as input). Serial output data (SO) in this case is passed through to BP42 (configured in P4CR to T2O) via the Timer 2 output stage (T2M2 configured in mode 6). Timer/SSI combined modes – the SSI used together with Timer 2 or Timer 3 is capable of performing a variety of data modulation and demodulation functions (see section Timer). The modulating data is converted by the SSI into a continuous serial stream of data which is in turn modulated in one of the timer functional blocks. Serial demodu- lated data can be serially captured in the SSI and read by the controller. In the Timer 3 modes 10 and 11 (demodulation modes) the SSI can only be used as demodulator.

4551F–4BMCU–05/06 ATAM862-4 Multi-chip link (MCL) – the SSI can also be used as an interchip data interface for use in single package multi-chip modules or hybrids. For such applications, the SSI is pro- vided with two dedicated pads (MCL_SD and MCL_SC) which act as a two-wire chip-to-chip link. The MCL can be activated by the MCL control bit. Should these MCL pads be used by the SSI, the standard SD and SC pins are not required and the corre- sponding Port 4 ports are available as conventional data ports. Figure 23-15. Block Diagram of the Synchronous Serial Interface 23.8.3 General SSI Operation The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buffers – the receive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for inter- mediate storage of data to be serially output. Both buffers are directly accessable by software. Transferring the parallel buffer data into and out of the shift register is controlled automatically by the SSI control, so that both single byte transfers or continuous bit streams can be supported. The SSI can generate the shift clock (SC) either from one of several on-chip clock sources or accept an external clock. The external shift clock is output on, or applied to the Port BP40. Selection of an external clock source is performed by the Serial Clock Direction control bit (SCD). In the combinational modes, the required clock is selected by the corresponding timer mode. The SSI can operate in three data transfer modes – synchronous 8-bit shift mode, a 9-bit Multi-Chip Link Mode (MCL) ,or 8-bit pseudo MCL protocol (without acknowledge-bit). External SSI clocking is not supported in these modes. The SSI should thus generate and has full control over the shift clock so that it can always be regarded as an MCL bus master device. All directional control of the external data port used by the SSI is handled automatically and is dependent on the transmission direction set by the Serial Data Direction (SDD) control bit. This control bit defines whether the SSI is currently operating in Transmit (TX) mode or Receive (RX) mode. Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. In the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see “MCL Bus Protocol” on page 77). 8-bit Shift Register MSB LSB Shift_CL SO SIC1 SIC2 SISC SC Control STB SRB SI Timer 2 / Timer 3 Output INT3 SC I/O-bus I/O-bus SSI-Control TOG2 POUT T1OUT SYSCL SO SI MCL_SC SD MCL_SD Transmit Buffer Receive Buffer SCI

4551F–4BMCU–05/06 ATAM862-4 At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register and proceeds immediately to shift data serially out. At the same time, incoming data is shifted into the shift register input. This incoming data is automatically loaded into the receive buffer when the complete telegram has been received. Thus, data can be simultaneously received and transmitted if required. Before data can be transferred, the SSI must first be activated. This is performed by means of the SSI reset control (SIR) bit. All further operation then depends on the data directional mode (TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX mode). The control logic ensures that data shifting is temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will then automatically be set back to ‘1’ and data shifting resumed as soon as the application software loads the new data into the transmit register (in TX mode) or frees the shift register by reading it into the receive buffer (in RX mode). A further activity status (ACT) bit indicates the present status of the serial communication. The ACT bit remains high for the duration of the serial telegram or if MCL stop or start conditions are currently being generated. Both the current SRDY and ACT status can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set high. 23.8.4 8-bit Synchronous Mode Figure 23-16. 8-bit Synchronous Mode In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface (see “SSI Peripheral Configuration” on page 72). The serial data (SD) is received or transmitted in NRZ format, synchronized to either the rising or falling edge of the shift clock (SC). The choice of clock edge is defined by the Serial Mode Control bits (SM0,SM1). It should be noted that the transmission edge refers to the SC clock edge with which the SD changes. To avoid clock skew problems, the incoming serial input data is shifted in with the opposite edge. When used together with one of the timer modulator or demodulator stages, the SSI must be set in the 8-bit synchronous mode 1. In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and the incoming serial data is shifted into the shift register. This first telegram is automatically trans- ferred into the receive buffer and the SRDY set to 0 indicating that the receive buffer contains valid data. At the same time an interrupt (if enabled) is generated. The SSI then continues shift- ing in the following 8-bit telegram. If, during this time the first telegram has been read by the controller, the second telegram will also be transferred in the same way into the receive buffer SC SC DATA SD/TO2 Bit 7 Bit 0 Bit 7 Bit 0 Data: 00110101 (Rising edge) (Falling edge)

4551F–4BMCU–05/06 ATAM862-4 23.8.5 9-bit Shift Mode (MCL) In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always operates as an MCL master device, i.e., SC is always generated and output by the SSI. Both the MCL start and stop conditions are automatically generated whenever the SSI is activated or deactivated by the SIR bit. In accordance with the MCL protocol, the output data is always changed in the clock low phase and shifted in on the high phase. Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate data direc- tion for the first word must be set using the SDD control bit. The state of this bit controls the direction of the data port (BP43 or MCL_SD). Once started, the 8 data bits are, depending on the selected direction, either clocked into or out of the shift register. During the 9th clock period, the port direction is automatically switched over so that the corresponding acknowledge bit can be shifted out or read in. In transmit mode, the acknowledge bit received from the device is cap- tured in the SSI Status Register (TACK) where it can be read by the controller. In receive mode, the state of the acknowledge bit to be returned to the device is predetermined by the SSI Status Register (RACK). Changing the directional mode (TX/RX) should not be performed during the transfer of an MCL telegram. One should wait until the end of the telegram which can be detected using the SSI interrupt (IFN =1) or by interrogating the ACT status. Once started, a 9-bit telegram will always run to completion and will not be prematurely termi- nated by the SIR bit. So, if the SIR bit is set to ‘1’ in telegram, the SSI will complete the current transfer and terminate the dialog with an MCL stop condition. Figure 23-19. Example of MCL Transmit Dialog 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0 A msb lsb tx data 1 tx data 2 msb lsb Write STB (tx data 1) SC SD SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = 1) 0 A Write STB (tx data 2) SIR SDD Start Stop

4551F–4BMCU–05/06 ATAM862-4 Figure 23-20. Example of MCL Receive Dialog 23.8.6 8-bit Pseudo MCL Mode In this mode, the SSI exhibits all the typical MCL operational features except for the acknowl- edge bit which is never expected or transmitted. 23.8.7 MCL Bus Protocol The MCL protocol constitutes a simple 2-wire bi-directional communication highway via which devices can communicate control and data information. Although the MCL protocol can support multi-master bus configurations, the SSI in MCL mode is intended for use purely as a master controller on a single master bus system. So all reference to multiple bus control and bus con- tention will be omitted at this point. All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge bit. Nor- mally the communication channel is opened with a so-called start condition, which initializes all devices connected to the bus. This is then followed by a data telegram, transmitted by the mas- ter controller device. This telegram usually contains an 8-bit address code to activate a single slave device connected onto the MCL bus. Each slave receives this address and compares it with its own unique address. The addressed slave device, if ready to receive data, will respond by pulling the SD line low during the 9th clock pulse. This represents a so-called MCL acknowl- edge. The controller detecting this affirmative acknowledge then opens a connection to the required slave. Data can then be passed back and forth by the master controller, each 8-bit tele- gram being acknowledged by the respective recipient. The communication is finally closed by the master device and the slave device put back into standby by applying a stop condition onto the bus. 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0 A msb lsb tx data 1 rx data 2 msb lsb Write STB (tx data 1) SC SD SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = 1) 0 A Read SRB (rx data 2) SIR SDD Start Stop

4551F–4BMCU–05/06 ATAM862-4 23.8.9 Modulation and Demodulation If the shift register is used together with Timer 2 or Timer 3 for modulation or demodulation pur- poses, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can be used as conventional bi-directional ports. The modulation and demodulation stages, if enabled, operate as soon as the SSI is activated (SIR = 0) and cease when deactivated (SIR = 1). Due to the byte-orientated data control, the SSI (when running normally) generates serial bit streams which are submultiples of 8 bits. An SSI output masking (OMSK) function permits; how- ever, the generation of bit streams of any length. The OMSK signal is derived indirectly from the 4-bit prescaler of the Timer 2 and masks out a programmable number of unrequired trailing data bits during the shifting out of the final data word in the bit stream. The number of non-masked data bits is defined by the value pre-programmed in the prescaler compare register. To use out- put masking, the modulator stop mode bit (MSM) must be set to "0" before programming the final data word into the SSI transmit buffer. This in turn, enables shift clocks to the prescaler when this final word is shifted out. On reaching the compare value, the prescaler triggers the OMSK signal and all following data bits are blanked. Figure 23-23. SSI Output Masking Function 8-bit shift register MSB LSB Shift_CL SO Control SI Timer 2 Output SSI-control SO Compare 2/1 4-bit counter 2/1 CL2/1 SCL CM1 OMSK SC TOG2 POUT T1OUT SYSCL

4551F–4BMCU–05/06 ATAM862-4 23.9 Serial Interface Registers 23.9.1 Serial Interface Control Register 1 (SIC1) Auxiliary register address: "9"hex Note: This bit has to be set to "1" during the MCL mode and the Timer 3 mode 10 or 11 Note: with SCD = 0 the bits SCS1 and SCS0 are insignificant Table 23-4. Serial Clock Source Select Bits

• In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1).
• Setting SIR bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only).
• In MCL modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop condition. Bit 3 Bit 2 Bit 1 Bit 0 SIR SCD SCS1 SCS0 Reset value: 1111b SIR Serial Interface Reset SIR = 1, SSI inactive SIR = 0, SSI active SCD Serial Clock Direction SCD = 1, SC line used as output SCD = 0, SC line used as input SCS1 Serial Clock source Select bit 1 SCS0 Serial Clock source Select bit 0 SCS1 SCS0 Internal Clock for SSI SYSCL/2 T1OUT/2 POUT/2 TOG2/2

4551F–4BMCU–05/06 ATAM862-4 23.9.2 Serial Interface Control Register 2 (SIC2) Auxiliary register address: "A"hex Table 23-5. Serial Mode Control Bits Note: SDD controls port directional control and defines the reset function for the SRDY-flag Bit 3 Bit 2 Bit 1 Bit 0 MSM SM1 SM0 SDD Reset value: 1111b MSM Modular Stop Mode MSM = 1, modulator stop mode disabled (output masking off) MSM = 0, modulator stop mode enabled (output masking on) - used in modulation modes for generating bit streams which are not sub-multiples of 8 bits. SM1 Serial Mode control bit 1 SM0 Serial Mode control bit 0 Mode SM1 SM0 SSI Mode 8-bit NRZ-Data changes with the rising edge of SC 8-bit NRZ-Data changes with the falling edge of SC 9-bit two-wire MCL mode 8-bit two-wire MCL mode (no acknowledge) SDD Serial Data Direction SDD = 1, transmit mode - SD line used as output (transmit data). SRDY is set SDD = 0, receive mode – . SD line used as input (receive data). SRDY is set

4551F–4BMCU–05/06 ATAM862-4 23.9.3 Serial Interface Status and Control Register (SISC) Primary register address: "A"hex 23.9.4 Serial Transmit Buffer (STB) – Byte Write Primary register address: "9"hex The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting with the most significant bit. Bit 3 Bit 2 Bit 1 Bit 0 Write MCL RACK SIM IFN Reset value: 1111b Read TACK ACT SRDY Reset value: xxxxb MCL Multi-Chip Link activation MCL = 1,multi-chip link disabled. This bit has to be set to "0" during transactions to/from the internal EEPROM MCL = 0, connects SC and SD additionally to the internal multi-chip link pads RACK Receive ACKnowledge status/control bit for MCL mode RACK = 0, transmit acknowledge in next receive telegram RACK = 1, transmit no acknowledge in last receive telegram TACK Transmit ACKnowledge status/control bit for MCL mode TACK = 0, acknowledge received in last transmit telegram TACK = 1, no acknowledge received in last transmit telegram SIM Serial Interrupt Mask SIM = 1, disable interrupts SIM = 0, enable serial interrupt. An interrupt is generated. IFN Interrupt FuNction IFN = 1, the serial interrupt is generated at the end of telegram IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes empty/full in transmit/receive mode) SRDY Serial interface buffer ReaDY status flag SRDY = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full SRDY = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty ACT Transmission ACTive status flag ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions are currently in progress. ACT = 0, transmission is inactive First write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: xxxxb Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb

4551F–4BMCU–05/06 ATAM862-4 23.9.5 Serial Receive Buffer (SRB) – Byte Read Primary register address: "9"hex The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads content into the receive buffer when complete telegram has been received. 24. Combination Modes The UTCM consists of two timers (Timer 2 and Timer 3) and a serial interface. There is a multi- tude of modes in which the timers and serial interface can work together. The 8-bit wide serial interface operates as shift register for modulation and demodulation. The modulator and demodulator units work together with the timers and shift the data bits into or out of the shift register. 24.1 Combination Mode Timer 2 and SSI Figure 24-1. Combination Timer 2 and SSI First read cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb Second read cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: xxxxb 4-bit counter 2/1 RES OVF1 Compare 2/1 T2CO1 POUT CL2/2 DCG T2M1 P4CR 8-bit counter 2/2 RES OVF2 Compare 2/2 T2CO2 T2CM Timer 2 - control TOG2 INT4 Biphase-, Manchester- modulator Output MOUT T2O Timer 2 modulator output-stage T2M2 SO Control T2C CL2/1 T2I SYSCL T1OUT TOG3 SCL I/O-bus 8-bit shift register MSB LSB Shift_CL SO SIC1 SIC2 SISC SCLI Control STB SRB SI Output INT3 I/O-bus SSI-control TOG2 POUT T1OUT SYSCL MCL_SC MCL_SD Transmit buffer Receive buffer CM1 I/O-bus POUT SO SCL SC SD DCGO TOG2

4551F–4BMCU–05/06 ATAM862-4 24.1.5 Combination Mode 5: Biphase Modulation 2 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage Timer 2 mode 3: 8-bit compare counter and 4-bit prescaler Timer 2 output mode 4: The modulator 2 of Timer 2 modulates the SSI data output to Biphase code The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special mode to supply the prescaler via the shift clock. The control output signal (OMSK) of the SSI is used as stop signal for the modulator. Figure 24-1 on page 83 shows an example for a 13-bit Biphase telegram. Figure 24-6. Biphase Modulation 2 Counter 2/1 = Compare Register 2/1 (= 5) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCLI Buffer full SIR SO SC MSM Timer 2 Mode 3 SCL Counter 2/1 OMSK T2O

4551F–4BMCU–05/06 ATAM862-4 24.2 Combination Mode Timer 3 and SSI Figure 24-7. Combination Timer 3 and SSI 8-bit counter 3 RES Compare 3/1 T3CO1 T3CP T3CO2 Timer 3 - control T3O CL3 T3I T3EX SYSCL T1OUT POUT I/O-bus Compare 3/2 T3CM1 T3CM2 T3C T3ST Modulator 3 Demodu- lator 3 Control SO TOG3 INT5 RES CM31 T3I T3EX SI SC T3M T3CS CP3 8-bit shift register MSB LSB Shift_CL SO SIC1 SIC2 SISC SCLI Control STB SRB SI Output INT3 I/O-bus SSI-control TOG2 POUT T1OUT SYSCL SI MCL_SC MCL_SD Transmit buffer Receive buffer SC SC SI

4551F–4BMCU–05/06 ATAM862-4 24.2.3 Combination Mode 8: Manchester Demodulation/Pulse-width Demodulation SSI mode 1: 8-bit shift register internal data input (SI) and the internal shift clock (SCI) from the Timer 3 Timer 3 mode 10: Manchester demodulation/pulse-width demodulation with Timer 3 For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used to generate the shift clock for the SSI. A compare register 1 match event defines the correct moment for shifting the state from the input T3I as the decoded bit into shift register. After that, the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The compare register 2 can be used to detect a time error and handle it with an interrupt routine. Before activating the demodulator mode the timer and the demodulator stage must be synchro- nized with the bitstream. The Manchester code timing consists of parts with the half bitlength and the complete bitlength. A synchronization routine must start the demodulator after an inter- val with the complete bitlength. The counter can be driven by any internal clock source. The output T3O can be used by Timer 2 in this mode. The Manchester decoder can also be used for pulse-width demodulation. The input must programmed to detect the positive edge. The demodulator and timer must be synchronized with the leading edge of the pulse. After that a counter match with the compare register 1 shifts the state at the input T3I into the shift register. The next positive edge at the input restarts the timer. Figure 24-10. Manchester Demodulation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Synchronize Manchester demodulation mode Timer 3 mode T3EX SI SR-DATA T3I CM31=SCI Bit 0

4551F–4BMCU–05/06 ATAM862-4 24.2.4 Combination Mode 9: Biphase Demodulation SSI mode 1: 8-bit shift register internal data input (SI) and the internal shift clock (SCI) from the Timer 3 Timer 3 mode 11: Biphase demodulation with Timer 3 In the Biphase demodulation mode the timer works like in the Manchester demodulation mode. The difference is that the bits are decoded with the toggle flip-flop. This flip-flop samples the edge in the middle of the bitframe and the compare register 1 match event shifts the toggle flip-flop output into shift register. Before activating the demodulation the timer and the demodula- tion stage must be synchronized with the bitstream. The Biphase code timing consists of parts with the half bitlength and the complete bitlength. The synchronization routine must start the demodulator after an interval with the complete bitlength. The counter can be driven by any internal clock source and the output T3O can be used by Timer 2 in this mode. Figure 24-11. Biphase Demodulation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Synchronize Biphase demodulation mode Timer 3 mode T3EX Q1=SI CM31=SCI SR-DATA T3I Reset Counter 3 Bit 0

4551F–4BMCU–05/06 ATAM862-4 24.3 Combination Mode Timer 2 and Timer 3 Figure 24-12. Combination Timer 3 and Timer 2 24.3.1 Combination Mode 10: Frequency Measurement or Event Counter with Time Gate Timer 2 mode 1/2: 12-bit compare counter/8-bit compare counter and 4-bit prescale Timer 2 output mode 1/6: Timer 2 compare match toggles (TOG2) to the Timer 3 Timer 3 mode 3: Timer/Counter; internal trigger restart and internal capture (with Timer 2 TOG2-signal) The counter is driven by an external (T3I) clock source. The output signal (TOG2) of Timer 2 resets the counter. The counter value before reset is saved in the capture register. If sin- gle-action mode is activated for one or both compare registers, the trigger signal restarts also the single actions. This mode can be used for frequency measurements or as event counter with time gate. 8-bit counter 3 RES Compare 3/1 T3CO1 T3CP T3CO2 Timer 3 - control T3O CL3 T3I T3EX SYSCL T1OUT POUT I/O-bus Compare 3/2 T3CM1 T3CM2 T3C T3ST Modulator 3 Demodu- lator 3 Control SO TOG3 INT5 RES CM31 T3I T3EX TOG2 SI SCI SSI CP3 4-bit counter 2/1 RES OVF1 Compare 2/1 T2CO1 CM1 POUT SSI CL2/2 DCG T2M1 P4CR 8-bit counter 2/2 RES OVF2 Compare 2/2 T2CO2 T2CM TOG2 INT4 Biphase-, Manchester- modulator OUTPUT MOUT T2O Timer 2 modulator 2 output-stage T2M2 Control (RE, FE, SCO, OMSK) SSI T2C CL2/1 TOG3 SYSCL T1OUT SCL Timer 2 - control T3CS T3M POUT DCGO SO T2I I/O-bus I/O-bus

4551F–4BMCU–05/06 ATAM862-4 24.4 Combination Mode Timer 2, Timer 3 and SSI Figure 24-16. Combination Timer 2, Timer 3 and SSI 8-bit Counter 3 RES Compare 3/1 T3CO1 T3CP T3CO2 Timer 3 - control T3O CL3 T3I T3EX SYSCL T1OUT POUT I/O-bus Compare 3/2 T3CM1 T3CM2 T3C T3ST Modulator 3 Demodu- lator 3 Control SO TOG3 INT5 RES CM31 T3I T3EX TOG2 SI SCI SSI CP3 4-bit Counter 2/1 RES OVF1 Compare 2/1 T2CO1 CM1 POUT CL2/2 DCG T2M1 P4CR 8-bit Counter 2/2 RES OVF2 Compare 2/2 T2CO2 T2CM TOG2 INT4 Biphase-, Manchester- modulator OUTPUT MOUT T2O Timer 2 modulator 2 output-stage T2M2 Control (RE, FE, SCO, OMSK) T2C CL2/1 TOG3 SYSCL T1OUT SCL Timer 2 - control T3CS T3M POUT DCGO SO T2I I/O-bus I/O-bus 8-bit shift register MSB LSB Shift_CL SO SIC1 SIC2 SISC SCLI Control STB SRB SI Output INT3 I/O-bus SSI-control TOG2 POUT T1OUT SYSCL MCL_SC MCL_SD Transmit buffer Receive buffer SC SI SCL

4551F–4BMCU–05/06 ATAM862-4 24.4.1 Combination Mode 12: Burst Modulation 2 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3 Timer 2 output mode 2: 8-bit compare counter and 4-bit prescaler Timer 2 output mode 1/6: Timer 2 compare match toggles (TOG2) to the SSI Timer 3 mode 7: Carrier frequency burst modulation controlled by the internal output (SO) of SSI The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare mode registers must be programmed to generate the carrier frequency with the output toggle flip-flop (M3). The internal data output (SO) of the SSI is used to enable and disable the Timer 3 output. The SSI can be supplied with the toggle signal of Timer 2. Figure 24-17. Burst Modulation 2 24.4.2 Combination Mode 13: FSK Modulation SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3 Timer 2 output mode 3: 8-bit compare counter and 4-bit prescaler Timer 2 output mode 1/6: Timer 2 4-bit compare match signal (POUT) to the SSI Timer 3 mode 8: FSK modulation with shift register data output (SO) The two compare registers are used to generate two different time intervals. The SSI data output selects which compare register is used for the output frequency generation. A "0" level at the SSI data output enables the compare register 1 and a "1" level enables the compare register 2. The compare- and compare mode registers must be programmed to generate the two frequen- cies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer 2 or any other clock source. The Timer 3 counter is driven by an internal or external clock source. 0 1 01 2 34 5 01 0 12 3 45 0 10 1 23 4 50 1 01 5 0 1 01 5 0 1 01 5 0 1 01 5 0 1 01 5 0 1 0 1 5 0 1 01 5 0 1 0 1 5 0 1 0 1 5 0 1 01 CL3 Counter 3 CM31 CM32 TOG3 Counter 2/2 TOG2 SO T3O

4551F–4BMCU–05/06 ATAM862-4 24.6 Serial Interface The EEPROM uses a two-wire serial interface (TWI) to the microcontroller for read and write accesses to the data. It is considered to be a slave in all these applications. That means, the controller has to be the master that initiates the data transfer and provides the clock for transmit and receive operations. The serial interface is controlled by the microcontroller which generates the serial clock and con- trols the access via the SCL-line and SDA-line. SCL is used to clock the data into and out of the device. SDA is a bi-directional line that is used to transfer data into and out of the device. The following protocol is used for the data transfers. 24.6.1 Serial Protocol

• Data states on the SDA ine changing only while SCL is low.
• Changes on the SDA line while SCL is high are interpreted as START or STOP condition.
• A START condition is defined as high to low transition on the SDA line while the SCL-line is high.
• A STOP condition is defined as low to high transition on the SDA line while the SCL line is high.
• Each data transfer must be initialized with a START condition and terminated with a STOP condition. The START condition wakes the device from standby mode and the STOP condition returns the device to standby mode.
• A receiving device generates an acknowledge (A) after the reception of each byte. This requires an additional clock pulse, generated by the master. If the reception was successful the receiving master or slave device pulls down the SDA line during that clock cycle. If an acknowledge is not detected (N) by the interface in transmit mode, it will terminate further data transmissions and go into receive mode. A master device must finish its read operation by a non-acknowledge and then send a stop condition to bring the device into a known state. Figure 24-20. MCL Protocol
• Before the START condition and after the STOP condition the device is in standby mode and the SDA line is switched as input with pull-up resistor.
• The control byte that follows the START condition determines the following operation. It consists of the 5-bit row address, 2 mode control bits and the READ/NWRITE bit that is used to control the direction of the following transfer. A "0" defines a write access and a "1" a read access. Start condition Data valid Data change Data/ acknowledge valid Stop condition SCL SDA Stand by Stand- by

4551F–4BMCU–05/06 ATAM862-4 24.6.2 Control Byte Format 24.7 EEPROM The EEPROM has a size of 2 × 512 bits and is organized as 32 × 16-bit matrix each. To read and write data to and from the EEPROM the serial interface must be used. The interface sup- ports one and two byte write accesses and one to n-byte read accesses to the EEPROM. 24.7.1 EEPROM – Operating Modes The operating modes of the EEPROM are defined via the control byte. The control byte contains the row address, the mode control bits and the read/not-write bit that is used to control the direc- tion of the following transfer. A "0" defines a write access and a "1" a read access. The five address bits select one of the 32 rows of the EEPROM memory to be accessed. For all accesses the complete 16-bit word of the selected row is loaded into a buffer. The buffer must be read or overwritten via the serial interface. The two mode control bits C1 and C2 define in which order the accesses to the buffer are performed: High byte – low byte or low byte – high byte. The EEPROM also supports autoincrement and autodecrement read operations. After sending the start address with the corresponding mode, consecutive memory cells can be read row by row without transmission of the row addresses. Two special control bytes enable the complete initialization of EEPROM with "0" or with "1". 24.7.2 Write Operations The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the START condition followed by a write control byte and one or two data bytes from the master. It is com- pleted via the STOP condition from the master after the acknowledge cycle. The programming cycle consists of an erase cycle (write "zeros") and the write cycle (write "ones"). Both cycles together take about 10 ms. 24.7.3 Acknowledge Polling If the EEPROM is busy with an internal write cycle, all inputs are disabled and the EEPROM will not acknowledge until the write cycle is finished. This can be used to detect the end of the write cycle. The master must perform acknowledge polling by sending a start condition followed by the control byte. If the device is still busy with the write cycle, it will not return an acknowledge and the master has to generate a stop condition or perform further acknowledge polling sequences. If the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle. EEPROM Address Mode Control Bits Read/ NWrite Start R/NW Ackn Start Control byte Ackn Data byte Ackn Data byte Ackn Stop

4551F–4BMCU–05/06 ATAM862-4 24.7.4 Write One Data Byte 24.7.5 Write Two Data Bytes 24.7.6 Write Control Byte Only 24.7.7 Write Control Bytes A -> acknowledge; HB: high byte; LB: low byte; R: row address 24.7.8 Read Operations The EEPROM allows byte-, word- and current address read operations. The read operations are initiated in the same way as write operations. Every read access is initiated by sending the START condition followed by the control byte which contains the address and the read mode. When the device has received a read command, it returns an acknowledge, loads the addressed word into the read/write buffer and sends the selected data byte to the master. The master has to acknowledge the received byte if it wants to proceed the read operation. If two bytes are read out from the buffer the device increments respectively decrements the word address automati- cally and loads the buffer with the next word. The read mode bits determines if the low or high byte is read first from the buffer and if the word address is incremented or decremented for the next read access. If the memory address limit is reached, the data word address will roll over and the sequential read will continue. The master can terminate the read operation after every byte by not responding with an acknowledge (N) and by issuing a stop condition. Start Control byte A Data byte 1 A Stop Start Control byte A Data byte 1 A Data byte 2 A Stop Start Control byte A Stop MSB LSB Write low byte first R/NW Row address Byte order LB(R) HB(R) MSB LSB Write high byte first R/NW Row address Byte order HB(R) LB(R)

4551F–4BMCU–05/06 ATAM862-4 24.7.9 Read One Data Byte 24.7.10 Read Two Data Bytes 24.7.11 Read n Data Bytes 24.7.12 Read Control Bytes A -> acknowledge, N -> no acknowledge; HB: high byte; LB: low byte, R: row address 24.8 Initialization the Serial Interface to the EEPROM To prevent unexpected behavior of he EEPROM and its interface it is good practice to use an initialization sequence after any reset of the circuit. This is performed by writing: to the serial interface. If the EEPROM acknowledges this sequence it is in a defined state. Maybe it is necessary to perform this sequence twice. Start Control byte A Data byte 1 N Stop Start Control byte A Data byte 1 A Data byte 2 N Stop Start Control byte A Data byte 1 A Data byte 2 A Data byte n N Stop MSB LSB Read low byte first, address increment R/NW Row address Byte order LB(R) HB(R) LB(R+1) HB(R+1) LB(R+n) HB(R+n) MSB LSB Read high byte first, address decrement R/NW Row address Byte order HB(R) LB(R) HB(R-1) LB(R-1) HB(R-n) LB(R-n) Start "FFh" A Stop

4551F–4BMCU–05/06 ATAM862-4 25. Absolute Maximum Ratings: Microcontroller Block Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., VDD). Voltages are given relative to VSS Parameters Symbol Value Unit Supply voltage VDD -0.3 to + 6.5 V Input voltage (on any pin) VIN VSS -0.3 ≤ VIN ≤ VDD +0.3 V Output short circuit duration tshort Indefinite s Operating temperature range Tamb -40 to +125 Storage temperature range Tstg -40 to +150 Soldering temperature (t ≤ 10 s) Tsld 260 26. Thermal Resistance Parameter Symbol Value Unit Thermal resistance RthJA 135 K/W 27. DC Operating Characteristics VSS = 0 V, Tamb = -40°C to +125°C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit Power Supply Operating voltage at VDD VDD VPOR 4.0 V Active current CPU active fSYSCL = 1 MHz VDD = 1.8 V VDD = 3.0 V IDD 0.3 0.4 0.4 mA mA Power down current (CPU sleep, RC oscillator active, 4-MHz quartz oscillator active) fSYSCL = 1 MHz VDD = 1.8 V VDD = 3.0 V IPD 150 µA µA Sleep current (CPU sleep, 32-kHz quartz oscillator active 4-MHz quartz oscillator inactive) VDD = 1.8 V VDD = 3.0 V VDD = 3.0 V at 85° C ISleep 0.4 0.6 4.3 1.5 µA µA µA Sleep current (CPU sleep, 32-kHz quartz oscillator inactive 4-MHz quartz oscillator inactive) VDD = 3.0 V VDD = 3.0 V at 85° C ISleep 0.3 3.5 1.0 µA µA Pin capacitance Any pin to VSS CL pF

4551F–4BMCU–05/06 ATAM862-4 Note: The pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller Power-on Reset Threshold Voltage POR threshold voltage BOT = 1 VPOR 1.54 1.7 1.88 V POR threshold voltage BOT = 0 VPOR 1.83 2.0 2.20 V POR hysteresis VPOR mV Voltage Monitor Threshold Voltage VM high threshold voltage VDD > VM, VMS = 1 VMThh 3.0 3.35 V VM high threshold voltage VDD < VM, VMS = 0 VMThh 2.77 3.0 V VM middle threshold voltage VDD > VM, VMS = 1 VMThm 2.6 2.9 V VM middle threshold voltage VDD < VM, VMS = 0 VMThm 2.4 2.6 V VM low threshold voltage VDD > VM, VMS = 1 VMThl 2.2 2.44 V VM low threshold voltage VDD < VM, VMS = 0 VMThl 2.0 2.2 V External Input Voltage VMI VDD = 3 V, VMS = 1 VVMI 1.3 1.44 V VMI VDD = 3 V, VMS = 0 VVMI 1.18 1.3 V All Bi-directional Ports Input voltage LOW VDD = 2.0 to 4.0 V VIL VSS 0.2 × VDD V Input voltage HIGH VDD = 2.0 to 4.0 V VIH 0.8 × VDD VDD V Input LOW current (switched pull-up) VDD = 2.0 V, VDD = 3.0 V, VIL= VSS IIL -10 -20 -14 -40 µA µA Input HIGH current (switched pull-down) VDD = 2.0 V, VDD = 3.0 V, VIH = VDD IIH µA µA Input LOW current (static pull-up) VDD = 2.0 V VDD = 3.0 V, VIL= VSS IIL -30 -80 -50 -160 -98 -320 µA µA Input LOW current (static pull-down) VDD = 2.0 V VDD = 3.0 V, VIH= VDD IIH 160 100 320 µA µA Input leakage current VIL = VSS IIL 100 nA Input leakage current VIH = VDD IIH 100 nA Output LOW current VOL = 0.2 × VDD VDD = 2.0 V VDD = 3.0 V IOL 0.9 1.8 3.6 mA mA Output HIGH current VOH = 0.8 × VDD VDD = 2.0 V VDD = 3.0 V IOH -0.8 -1.7 -3.4 mA mA 27. DC Operating Characteristics (Continued) VSS = 0 V, Tamb = -40°C to +125°C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit

4551F–4BMCU–05/06 ATAM862-4 28. AC Characteristics Supply voltage VDD = 1.8 to 4.0 V, VSS = 0 V, Tamb = 25°C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit Operation Cycle Time System clock cycle VDD = 1.8 to 4.0 V Tamb = -40 to +125°C tSYSCL 500 2000 ns VDD = 2.4 to 4.0 V Tamb = -40 to +125°C tSYSCL 250 2000 ns Timer 2 input Timing Pin T2I Timer 2 input clock fT2I MHz Timer 2 input LOW time Rise/fall time < 10 ns tT2IL 100 ns Timer 2 input HIGH time Rise/fall time < 10 ns tT2IH 100 ns Timer 3 Input Timing Pin T3I Timer 3 input clock fT3I SYSCL/2 MHz Timer 3 input LOW time Rise/fall time < 10 ns tT3IL 2 tSYSCL ns Timer 3 input HIGH time Rise/fall time < 10 ns tT3IH 2 tSYSCL ns Interrupt Request Input Timing Interrupt request LOW time Rise/fall time < 10 ns tIRL 100 ns Interrupt request HIGH time Rise/fall time < 10 ns tIRH 100 ns External System Clock EXSCL at OSC1, ECM = EN Rise/fall time < 10 ns fEXSCL 0.5 MHz EXSCL at OSC1, ECM = DI Rise/fall time < 10 ns fEXSCL 0.02 MHz Input HIGH time Rise/fall time < 10 ns tIH 0.1 µs Reset Timing Power-on reset time VDD > VPOR tPOR 1.5 ms RC Oscillator 1 Frequency fRcOut1 3.8 MHz Stability VDD = 2.0 to 4.0 V Tamb = -40 to +125°C ∆f/f ±50 RC Oscillator 2 – External Resistor Frequency Rext = 180 kΩ fRcOut2 MHz Stability VDD = 2.0 to 4.0 V Tamb = -40 to +125°C ∆f/f ±15 Stabilization time tS µs 4-MHz Crystal Oscillator (Operating Range VDD = 2.2 V to 4.0 V) Frequency fX MHz Start-up time tSQ ms Stability ∆f/f -10 ppm Integrated input/output capacitances (configurable) CIN/COUT programmable CIN COUT 0, 2, 5, 7, 10 or 12 0, 2, 5, 7, 10 or 12 pF pF

4551F–4BMCU–05/06 ATAM862-4 29. Crystal Characteristics Figure 29-1. Crystal Equivalent Circuit 32-kHz Crystal Oscillator (Operating Range VDD = 2.0 V to 4.0 V) Frequency fX 32.768 kHz Start-up time tSQ 0.5 s Stability ∆f/f -10 ppm Integrated input/output capacitances (configurable) CIN/COUT programmable CIN COUT 0, 2, 5, 7, 10 or 12 0, 2, 5, 7, 10 or 12 pF pF External 32-kHz Crystal Parameters Crystal frequency fX 32.768 kHz Serial resistance RS kΩ Static capacitance 1.5 pF Dynamic capacitance fF External 4-MHz Crystal Parameters Crystal frequency fX 4.0 MHz Serial resistance RS 150 W Static capacitance 1.4 pF Dynamic capacitance fF EEPROM Operating current during erase/write cycle IWR 600 1300 µA Endurance Erase-/write cycles Tamb = 125°C ED ED 500000 10000 1000000 20000 Cycles Cycles Data erase/write cycle time For 16-bit access tDEW ms Data retention time Tamb = 125°C tDR tDR 100 Years Years Power-up to read operation tPUR 0.2 ms Power-up to write operation tPUW 0.2 ms Program EEPROM Erase-/write cycles, Tamb = 0 to 40° C nEW 100 1000 Cycles Serial Interface SCL clock frequency fSC_MCL 100 500 kHz 28. AC Characteristics (Continued) Supply voltage VDD = 1.8 to 4.0 V, VSS = 0 V, Tamb = 25°C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit L RS OSCIN OSCOUT Equivalent circuit SCLIN SCLOUT

4551F–4BMCU–05/06 ATAM862-4 30. Emulation The basic function of emulation is to test and evaluate the customer's program and hardware in real time. This therefore enables the analysis of any timing, hardware or software problem. For emulation purposes, all MARC4 controllers include a special emulation mode. In this mode, the internal CPU core is inactive and the I/O buses are available via Port 0 and Port 1 to allow an external access to the on-chip peripherals. The MARC4 emulator uses this mode to control the peripherals of any MARC4 controller (target chip) and emulates the lost ports for the application. The MARC4 emulator can stop and restart a program at specified points during execution, mak- ing it possible for the applications engineer to view the memory contents and those of various registers during program execution. The designer also gains the ability to analyze the executed instruction sequences and all the I/O activities. Figure 30-1. MARC4 Emulation MARC4 target chip CORE (inactive) Port 1 Port 0 Application-specific hardware Peripherals MARC4 emulator Program memory Trace memory Control logic Personal computer CORE MARC4 emulation-CPU I/O control I/O bus Port 0 Port 1 SYSCL/ TCL, TE, NRST Emulation control Emulator target board

4551F–4BMCU–05/06 ATAM862-4 32. Package Information 31. Ordering Information Extended Type Number(1) Program Memory Data-EEPROM Package Delivery ATAM862x-TNQYzf 4 kB Flash 2 × 512 bit SSO24 Taped and reeled ATAM862x-TNSYzf 4 kB Flash 2 × 512 bit SSO24 Tubes Note: 1. x = Hardware revision z = Operating temperature range J (-40°C to +125°C) + lead free f = RF frequency range = 4 (433 MHz) technical drawings according to DIN specifications Dimensions in mm 8.05 7.80 0.15 0.05 0.25 0.65 7.15 1.30 5.7 5.3 4.5 4.3 6.6 6.3 0.15

4551F–4BMCU–05/06 ATAM862-4 33. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4554F-4BMCU-05/06

• Put datasheet in new template
• Page 30: Section “32-kHz Oscillator” changed
• Page 105: Ordering Information changed 4554E-4BMCU-09/04
• Abs. Max. Ratings table (page 11): row “Input voltage” changed
• Abs. Max. Ratings table (page 11): table note 1 changed
• El. Char. table (page 12): row “PA_ENABLE input“ changed
• El. Char. table (page 12): table note 1 changed

4551F–4BMCU–05/06 ATAM862-4 34. Table of Contents 7.1 7.2 7.3 7.4 14.1 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8

4551F–4BMCU–05/06 ATAM862-4 16.9 17.1 19.1 19.2 19.3 21.1 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 22.10 22.11 22.12 23.1 23.2 23.3 23.4 23.5 Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated 23.6 23.7 23.8

4551F–4BMCU–05/06 ATAM862-4 23.9 24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8

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