ATA6620N

ATA6620N ATMEL | Alldatasheet

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Technical content

Features

• Supply Voltage up to 40V  Operating Voltage VS = 5V to 18V  Typically 10 µA Supply Current During Sleep Mode  Typically 40 µA Supply Current in Silent Mode  Linear Low-drop Voltage Regulator: – Normal Mode: V CC = 5V ±2%/50 mA – Silent Mode: V CC = 5V ±7%/50 mA – Sleep Mode: V CC is Switched Off  VCC Undervoltage Detection with Reset Output NRES (10 ms Reset Time)  Voltage Regulator is Short-circuit and Over-temperature Protected  LIN Physical Layer According to LIN Specification Revision 2.0  Wake-up Capability via LIN Bus (90 µs Dominant)  TXD Time-out Timer (9 ms)  60V Load-dump Protection at LIN Pin  Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery  High EMC Level  5V CMOS-compatible I/O Pins to MCU  ESD HBM 6 kV at Pins LIN and VS  Interference and Damage Protection According to ISO/CD7637  Package: SO8 1. Description ATA6620N is a fully integrated LIN transceiver, designed according to the LIN specifi- cation 2.0, with a low-drop voltage regulator (5V/50 mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in LIN Bus systems. ATA6620N is designed to handle the low-speed data com- munication in vehicles (for example, in convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20 kBaud with an RC oscillator for the protocol handling. The bus output is designed to withstand high voltage. Sleep mode (voltage regulator switched off) and Silent mode (communication off; V CC voltage on) guarantee minimized current consumption. LIN Bus Transceiver with Integrated Voltage Regulator ATA6620N 4850H–AUTO–12/07

4850H–AUTO–12/07 ATA6620N Figure 1-1. Block Diagram 2. Pin Configuration Figure 2-1. Pinning SO8 VS NRES7

4 LIN

5V/50 mA/2% Silent Mode Voltage Regulator 5V/50 mA/7% Short Circuit and Overtemperature Protection VS EN GND LIN VCC NRES TXD RXD Table 2-1. Pin Description Pin Symbol Function

1 VS Battery supply

2 EN Enables Normal mode if the input is high

3 GND Ground

4 LIN LIN bus line input/output

5 RXD Receive data output

6 TXD Transmit data input, active low output

7 NRES Output undervoltage reset, low at reset

8 VCC Output voltage regulator 5V/50 mA

4850H–AUTO–12/07 ATA6620N 3. Functional Description

3.1 Physical Layer Compatibility

Since the LIN physical layer is independent from hi gher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer any restrictions.

3.2 Supply Pin (VS)

LIN operating voltage is V S = 5V to 18V. An undervoltage detection is implemented to disable transmission if V S falls below 5V, in order to avoid false bus messages. After switching on V S, the IC starts with the Pre-normal mode and the voltage regulator is switched on (that is, 5V/50 mA output capability). The supply current in Sleep mode is typically 10 µA and 40 µA in Silent mode.

3.3 Ground Pin (GND)

The IC is neutral on the LIN pin in case of GND disconnection. It is able to handle a ground shift up to 3V for supply voltage above 9V at the VS pin.

3.4 Voltage Regulator Output Pin (VCC)

The internal 5V voltage regulator is capable of driving loads with up to 50 mA, supplying the microcontroller and other ICs on the PCB. It is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold V thun.

3.5 Undervoltage R eset Output (NRES)

This push-pull output is supplied from the V CC voltage. If the V CC voltage falls below the under- voltage detection threshold of V thun, NRES switches to low after tres_f ( Figure 4-7 on page 11 ) except the IC is switched into Sleep mode. Even if V CC = 0V the NRES stays low, because it is internally driven from the VS voltage. If VS voltage ramps down, NRES stays low until VS <1 . 5 V and then becomes highly resistive. The implemented undervoltage delay keeps NRES low for t Reset =1 0m s a f t e r VCC reaches its nominal value.

3.6 Bus Pin (LIN)

A low-side driver with internal current limitat ion and thermal shutdown, as well as an internal pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from –40V to +60V. This pin exhibits no re verse current from the LIN bus to VS, even in the case of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible with the LIN proto- col specification. The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled. The output has a short-circuit limitation. This is a self-adapting current limita- tion; that is, during current limitation, as the chip temperature increases, the current decreases.

4850H–AUTO–12/07 ATA6620N

3.7 Input/Output Pin (TXD)

This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resis- tor), the LIN output transistor is turned off and the bus is in the recessive state.

3.8 Dominant Time-o ut Function (TXD)

The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than t DOM > 4 ms, the LIN bus driver is switched to the recessive stat e. To reset this dominant time-out mode, TXD must be switched to high (> 10 µs) before normal data transmission can be started.

3.9 Output Pin (RXD)

This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up structure with typically 5 k Ω to V CC. The AC characteristics are measured with an external load capacitor of 20 pF. The output is short-circuit protected. In unpowered mode (that is, VS = 0V), RXD is switched off.

3.10 Enable Input Pin (EN)

This pin controls the operation mode of the interface. After power up of V S (battery), the IC switches to Pre-normal mode, even if EN is low or unconnected (internal pull-down resistor). If EN is high, the interface is in Normal mode. A falling edge at EN while TXD is still high forces the device to Silent mode. A falling edge at EN while TXD is low forces the device to Sleep mode.

4850H–AUTO–12/07 ATA6620N 4. Mode of Operation Figure 4-1. Mode of Operation

4.1 Normal Mode

This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.0. The V CC voltage regulator operates with a 5V output voltage, with a low toler- ance of ±2% and a maximum output current of 50 mA. If an undervoltage condition occurs, NRES is switched to low and the ATA6620N changes state to Pre-normal mode. All features are available. Pre-normal Mode VCC: 5V/2%/50 mA with undervoltage monitoring Communication: OFF ab Silent Mode VCC: 5V/7%/50 mA with undervoltage monitoring Communication: OFF EN = 1 Go to silent command EN = 0 TXD = 1 Local wake-up event a: VS > 5V b: VS < 4V c: Bus wake-up event d: NRES switches to low b EN = 1 b c + d Normal Mode VCC: 5V/2%/50 mA with undervoltage monitoring Communication: ON Unpowered Mode V Batt = 0 Sleep Mode VCC: switched off Communication: OFF Go to sleep command Local wake-up event EN = 0 TXD = 0 EN = 1 bc d Table 4-1. Mode of Operation Mode of Operation Communication V CC RXD LIN Pre-normal OFF 5V 5V Recessive Normal ON 5V 5V Recessive Silent OFF 5V 5V Recessive Sleep OFF 0V 0V Recessive

4850H–AUTO–12/07 ATA6620N

4.2 Modes of Reduced Current Consumption

4.2.1 Silent Mode

A falling edge at EN while TXD is high switches the IC into Silent mode. The TXD Signal has to be logic high during the Mode Select window (Figure 4-2 on page 6). For EN and TXD either two independent outputs can be used, or two outputs from the same microcontroller port; in the sec- ond case, the mode change is only one command. In Silent mode the transmission path is disabled. Supply current from V Batt is typically IVSsi = 40 µA with no load at the VCC regulator. The overall supply current from V Batt is the result of 40 µA plus the V CC regulator output current IVCCs. The 5V regulator is in low tolerance mode (4.65V to 5.35V) and can source up to 50 mA. In Silent mode the internal slave termination betw een pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typ- ically 10 µA) between pin LIN and pin VS is present. The Silent mode voltage is sufficient to run an external microcontroller on the ECU, for example in Power Down mode. The undervoltage reset is V CCthS < 4.4V. If an undervoltage condition occurs, NRES is switched to low and the ATA6620N changes state to Pre-normal mode. A falling edge at pin LIN followe d by a dominant bus level mainta ined for a certain time period (tbus) results in a remote wake-up request. The device switches from Silent mode to Pre-normal mode, then the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller and a high level at pin TXD(Figure 4-3 on page 7). With EN high, ATA6620N switches directly from Silent- via Pre-normal to Normal mode. Figure 4-2. Switch to Silent Mode EN td = 3.2 µs TXD Silent Mode VCC LIN Mode select window NRES Normal Mode LIN switches directly to recessive mode Delay time silent mode td_sleep = maximum 20 µs

4850H–AUTO–12/07 ATA6620N Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode LIN Bus Bus wake-up filtering time tbus Regulator Wake-up Time VCC EN Node ln silent mode EN High HighRXD Low If undervoltage switch to pre-normal modeNRES Silent mode Pre-normal mode Normal Mode Normal mode Undervoltage detection active Pre-normal Mode VLIN < 0.4 VS HighTXD

4850H–AUTO–12/07 ATA6620N

4.2.2 Sleep Mode

A falling edge at EN while TXD is low switches the IC into Sleep mode. The TXD Signal has to be logic low during the Mode Select window (Figure 4-4). We recommend using the same micro- controller port for EN as for TXD; in this case the mode change is only one command. In Sleep mode the transmission path is disabled. Supply current from V Batt is typically IVSsleep =1 0µ A . T h e VCC regulator is switched off; NRES and RXD are low. The internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. A falling edge at pin LIN followe d by a dominant bus level mainta ined for a certain time period (tbus) results in a remote wake-up request. The device switches from Sleep mode to Pre-normal mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcon- troller and a high level at pin TXD (Figure 4-5 on page 9). With EN high you can switch directly from Silent to Normal mode. In the application where the ATA6620N supplies the microcontroller, the wake-up from Sleep mode is only possible via pin LIN. If the device is switched into Sleep mode, V CC ramps down without generating an undervoltage reset at pin NRES. Figure 4-4. Switch to Sleep Mode EN td = 3.2 µs TXD Sleep Mode VCC Delay time sleep mode td_sleep = maximum 20 µsLIN LIN switches directly to recessive mode Mode select window NRES Normal Mode

4850H–AUTO–12/07 ATA6620N Figure 4-5. LIN Wake-up Diagram from Sleep Mode

4.2.3 Wake Up from Sleep/Silent Mode at an Insufficient Falling Edge at Pin LIN

If the ATA6620N is in Sleep mode or Silent mode and the voltage at the LIN Bus falls to a value lower than VLINL < VS – 3.3V (see “Electrical Characteristics” numbers 9.5 and 9.6) but higher than 0.6 × VS, then a wake up is detected and the circuit switches to pre-normal mode and the internal NMOS- transistor connected to the pin TXD is switched on and pulls down the pin TXD to Ground. The following figure shows the corresponding diagram for the wake-up from silent mode. The wake-up process from Sleep mode works analogue to this. LIN Bus Bus wake-up filtering time tbus On state Off state Regulator wake-up time EN Node in sleep mode Microcontroller start-up time delay EN High Low or floatingRXD Low Low or floatingNRES Reset time Normal ModePre-normal Mode VCC TXD VLIN < 0.4 VS

4850H–AUTO–12/07 ATA6620N Figure 4-6. Wake Up from Silent Mode at an Insufficient Falling Edge at Pin LIN When designing the complete system it has to be considered, that in this case (only in pre-nor- mal mode) the pin TXD of the ATA6620N works as an output.

4.3 Pre-normal Mode

At system power-up the device automatically switches to Pre-normal mode. The voltage regula- tor is switched on (V CC = 5V/50 mA) (see Figure 4-7 on page 11 ) after typically t VCC > 300 µs. The NRES output switches to low for t res = 10 ms and sends a reset to the microcontroller. LIN communication is switched off, and the undervoltage detection is active. A power-down of VBatt (VS < 4.15V) during Silent or Sleep mode switches into Pre-normal mode after powering up the IC. During this mode the TXD pin is an output. LIN Bus Wake-up filtering time t WAKE Regulator Wake-up Time VCC EN Node ln silent mode EN High HighRXD Low If undervoltage switch to pre-normal modeNRES Silent mode Pre-normal mode Normal Mode Normal mode Undervoltage detection active Pre-normal Mode VLIN < VS - 1V and VLIN > 0.6 VS HighTXD Low

4850H–AUTO–12/07 ATA6620N

4.4 Unpowered Mode

If battery voltage is connected to the application circuit ( Figure 4-7), the voltage at the VS pin increases due to the block capacitor. When V S is higher than the V S undervoltage threshold, VSth, the IC-mode changes from Unpowered to Pre-normal mode. The V CC output voltage reaches nominal value after tVCC. This time depends on the VCC capacitor and the load. NRES is low for the reset time delay tReset; no mode change is possible during this time. Figure 4-7. VCC Voltage Regulator: Ramp Up and Undervoltage 5. Fail-safe Features  During a short circuit at LIN, the output limits the output current to I BUS_LIM. Due to the power dissipation, the chip temperature exceeds tLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of thys, switches the output on again. During LIN overtemperature switch-off, the VCC regulator works independently.  There are now reverse currents < 3 µA at pin LIN during loss of VBatt or GND. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition.  During a short circuit at VCC, the output limits the output current to I VCCn. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into Pre–normal mode. If the chip temperature exceeds the value t VCCoff, the VCC output switches off. The chip cools down and after a hysteresis of thys, switches the output on again. Because of Pre-normal mode, the VCC voltage will switch on again although EN is switched off from the microcontroller.The microcontroller can then start with normal operation.  Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.  Pin RXD is set floating if VBatt is disconnected.  Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. VS 5.5V 12V VCC NRES Vthun tres tes_ftVCC

4850H–AUTO–12/07 ATA6620N 7. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Typ. Max. Unit Supply voltage V S VS –0.3 +40 V Pulse time ≤ 500 ms T=2 5 ° C Output current IVCC ≤ 50 mA VS +40 V Pulse time ≤ 2m i n T=2 5 ° C Output current I VCC ≤ 50 mA VS 27 V Logic pins (RXD, TXD, EN, NRES) –0.3 +6.5 V Output current NRES I NRES –2 +2 mA LIN - DC voltage - Transient voltage –40 –150 +60 +100 V V VCC - DC voltage –0.3 +6.5 V ESD (DIN EN 6100–4–2) Pin LIN, V S versus GND according to LIN specification EMC Evaluation V 1.3 –6 +6 kV HBM ESD S5.1 – all pins –3 +3 kV CDM ESD STM 5.3.1–1999 - All pins –1000 +1000 V Junction temperature T j –40 +150 °C Storage temperature T s –55 +150 °C Operating ambient temperature T a –40 +125 °C Thermal resistance junction to ambient (free air) Rthja 145 K/W Special heat sink at GND (pin 3) on PCB R thja 80 K/W Thermal shutdown of VCC regulator T VCCoff 150 160 170 °C Thermal shutdown of LIN output T LINoff 150 160 170 °C Thermal shutdown hysteresis T hys 10 °C

4850H–AUTO–12/07 ATA6620N 8. Electrical Characteristics 5V < VS < 18V, Tamb = –40°C to 125°C No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type*

1 VS Pin

1.1 Nominal DC voltage

range VS V S 5 13.5 18 V A

1.2 Supply current in Sleep

Vlin >V Batt –0 . 5 V VBatt < 14V (25°C to 125°C) VS I VSsleep 10 20 µA A

1.3 Supply current in Silent

Bus recessive; VBatt < 14V (25°C to 125°C) Without load at VCC VS I VSsi 40 50 µA A

1.4 Supply current in

1.5 Supply current in

VCC load current 50 mA VS I VSdom 55 mA A

1.6 Power On Reset

threshold VS POR th 33 . 3 V D

1.7 Power On Reset

threshold hysteresis VS POR hys 0.1 V D

1.8 VS undervoltage

threshold VS V Sth 4.15 4.5 5 V A

1.9 VS undervoltage

threshold hysteresis VS V Sth_hys 0.2 V A

2 RXD Output Pin

2.1 Low level input current

Normal mode; VLIN =0 V VRXD =0 . 4 V RXD I RXD 258 m A A 2.2 Low level output voltage I RXD = 1 mA RXD V RXDL 0.3 V A

2.3 Internal resistor to V CC RXD R RXD 357 k Ω A

3 TXD Input/Output Pin

3.1 Low level voltage input TXD V TXDL –0.3 +1.5 V A 3.2 High level voltage input TXD V TXDH 3.5 VCC + 0.3V VA

3.3 Pull-up resistor V TXD =0 V T X D R TXD 125 250 600 k Ω A

3.4 High level leakage

current VTXD =5 V T X D I TXD –3 +3 µA A

3.5 Low-level output current Pre-normal mode

VTXD = 0.4V to 5V TXD I TXDwake 258 m A A 4E N I n p u t P i n 4.1 Low level voltage input EN V ENL –0.3 +1.5 V A 4.2 High level voltage input EN V ENH 3.5 VCC + 0.3V VA

4.3 Pull-down resistor V EN = 5V EN R EN 125 250 600 k Ω A

4.4 Low level input current V EN = 0V EN I EN –3 +3 µA A

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4850H–AUTO–12/07 ATA6620N

5 NRES Output Pin

5.1 High level output voltage VS ≥ 5.5V; INRES =– 1 m A NRES V NRESH 4.5 V A

5.2 Low level output voltage

VS ≥ 5.5V; INRES =+ 1 m A INRES = +250 µA NRES V NRESL VNRESL 0.2 0.14 V V A A

5.3 Low level output low 10 kΩ to VCC;

VCC =0 . 8 V NRES V NRESLL 0.2 V A 5.4 Undervoltage reset time VVS ≥ 5.5V CNRES =2 0p F NRES t Reset 71 3 m s A

5.5 Reset debounce time for

VVS ≥ 5.5V CNRES =2 0p F NRES t res_f 3µ sA

6 Voltage Regulator VCC Pin in Normal and Pre-normal Mode

6.1 Output voltage V CC 5.5V < VS < 18V (0 mA – 50 mA) VCC V CCnor 4.9 5.1 V A

6.2 Output voltage VCC at

low VS 3.3V < VS < 5.5V VCC V CClow VVS – VD

5.1 V A

6.3 Regulator drop voltage V S > 4.0V, IVCC = –20 mA VCC V D 250 mV A 6.4 Regulator drop voltage V S > 4.0V, IVCC = –50 mA VCC V D 500 mV A 6.5 Regulator drop voltage V S > 3.3V, IVCC = –15 mA VCC V D 200 mV A

6.6 Output current V S > 3V VCC I VCC –50 mA A

6.7 Output current limitation V S > 0V VCC I VCCs –200 –130 mA A

6.8 Load capacity 1Ω < ESR < 5Ω at

100 kHz VCC C load 1.8 2.2 µF D

6.9 VCC undervoltage

VS > 5.5V VCC V thunN 4.4 4.8 V A

6.10 Hysteresis of

VS > 5.5V VCC V hysthun 30 mV A 6.11 Ramp up time VS > 5.5V to VCC > 4.9V CVCC = 4.7 µF No load VCC t VCC 300 µs A

7 Voltage Regulator VCC Pin in Silent Mode

7.1 Output voltage V CC 5.5V < VS < 18V (0 mA – 50 mA) VCC V CCnor 4.65 5.35 V A

7.2 Output voltage VCC at

3.3V < VS < 5.5V (0 mA – 50 mA) VCC V CClow VVS – VD 7.3 Regulator drop voltage V S > 3.3V, IVCC = 15 mA VCC V D 200 mV A 7.4 At VCC undervoltage threshold the state switches back to Pre-normal mode Referred to V CC VS > 5.5 VCC V thunS 3.9 4.4 V A 7.5 Hysteresis of undervoltage threshold Referred to V CC VS > 5.5V VCC V hysthun 40 mV D

7.6 Output current limitation V S > 0V VCC I VCCs –200 –130 mA A

1. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to 125°C No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4850H–AUTO–12/07 ATA6620N LIN Bus Driver: Bus Load Conditions: Load 1 (Small): 1 nF, 1 kΩ; Load 2 (Large): 10 nF, 500Ω; RRXD = 5 kΩ; CRXD = 20 pF 10.5, 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 Kbps

8.1 Driver recessive output

voltage Load1/Load2 LIN V BUSrec 0.9 × VS VS VA

8.2 Driver dominant voltage VVS = 7V

Rload = 500 Ω LIN V _LoSUP 1.2 V A

8.3 Driver dominant voltage VVS = 18V

Rload = 500 Ω LIN V _HiSUP 2VA

8.4 Driver dominant voltage VVS = 7V

Rload = 1000 Ω LIN V _LoSUP_1k 0.6 V A

8.5 Driver dominant voltage VVS = 18V

Rload = 1000 Ω LIN V _HiSUP_1k 0.8 V A

8.6 Pull–up resistor to V S

mandatory LIN R LIN 20 30 60 k Ω A 8.7 Self-adapting current limitation VBUS = VBatt_max Tj = 125°C Tj = 27°C Tj = –40°C LIN I BUS_LIM 100 120 110 170 230 mA mA mA A 8.8 Input leakage current at the receiver including pull–up resistor as specified Input Leakage current Driver off VBUS = 0V VBatt = 12V LIN I BUS_PAS_dom –1 mA A

8.9 Leakage current LIN

8V < VBatt < 18V 8V < VBUS < 18V VBUS ≥ VBatt LIN I BUS_PAS_rec 15 20 µA A 8.10 Leakage current when control unit disconnected from ground. Loss of local ground must not affect communication in the residual network GND Device = VS VBatt = 12V 0V < VBUS < 18V LIN I BUS_NO_gnd –10 +0.5 +10 µA A 8.11 Node has to sustain the current that can flow under this condition. Bus must remain operational under this condition V Batt disconnected VSUP_Device = GND 0V < VBUS < 18V LIN I BUS 0.5 3 µA A

9 LIN Bus Receiver

9.1 Center of receiver

VBUS_CNT = (Vth_dom + Vth_rec)/2 LIN V BUS_CNT 0.475 × VS 0.5 × VS 0.525 × VS VA 9.2 Receiver dominant state V EN = 5V LIN V BUSdom –27 0.4 × VS VA 9.3 Receiver recessive state V EN = 5V LIN V BUSrec 0.6 × VS 40 V A

9.4 Receiver input

hysteresis Vhys = Vth_rec – Vth_dom LIN V BUShys 0.028 × VS 0.1 × VS 0.175 × VS VA 8. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to 125°C No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4850H–AUTO–12/07 ATA6620N

9.5 Wake detection LIN

High level input voltage LIN V LINH VS – 1V V S + 0.3V V A

9.6 Wake detection LIN

Low level input voltage ILIN = typically –3 mA LIN V LINL –27 V S – 3.3V V A

10 Internal Timers

10.1 Dominant time for

wake–up via LIN bus VLIN = 0V t bus 30 90 150 µs A 10.2 Time delay for mode change from Pre-normal into Normal mode via pin EN V EN = 5V t norm 52 0 µ s A 10.3 Time delay for mode change from Normal mode to Sleep mode via pin EN V EN = 0V t sleep 27 1 5 µ s A

10.4 TXD dominant time out

timer VTXD = 0V t dom 61 0 2 0 m s A

10.5 Duty cycle 1

THRec(max) = 0.744 × VS; THDom(max) = 0.581 × VS; VS = 7.0V to 18V; tBit = 50 ms D1 = tbus_rec(min)/(2 × tBit) D1 0.396 A

10.6 Duty cycle 2

THRec(min) = 0.422 × VS; THDom(min) = 0.284 × VS; VS = 7.0V to 18V; tBit = 50ms D2 = tbus_rec(max)/(2 × tBit) D2 0.581 A

10.7 Slope time falling and

tSLOPE_fall tSLOPE_rise 3.5 22.5 µs A 10.8 Time delay for mode change from Silent- into Normal mode via EN VEN = 5V t s_n 51 5 4 0 µ sA

11 Receiver Electrical AC Parameters of the LIN Physical Layer

LIN Receiver, RXD Load Conditions (CRXD): 20 pF; Rpull-up = 2.4 kΩ 11.1 Propagation delay of receiver Switch to Sleep mode (see Figure 8-1 on page 18) trx_pd = max(trx_pdr, trx_pdf)t rx_pd 6µ sA 11.2 Symmetry of receiver propagation delay rising edge minus falling edge trx_sym = trx_pdr – trx_pdf trx_sym –2 +2 µs A 8. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to 125°C No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4850H–AUTO–12/07 ATA6620N Figure 8-1. Definition of Bus Timing Characteristics VS (Transceiver supply of transmitting node) TXD (Input to transmitting Node) RXD (Output of receiving Node1) LIN Bus Signal tBit tBus_dom(max) tBus_dom(min) tBus_rec(min) tBus_rec(max) RXD (Output of receiving Node2) THRec(max) THDom(max) THDom(min) THRec(min) Thresholds of receiving node 1 Thresholds of receiving node 2 trx_pdf(1) trx_pdr(1) trx_pdr(2) trx_pdf(2) tBit tBit

4850H–AUTO–12/07 ATA6620N Figure 8-2. Application Circuit Microcontroller VBAT 10 µF 100 nF 100 nF LIN-BUS 220 pF VS NRES7 5V/50 mA/7% VCC Normal and Pre-normal Mode VCC 22 µF Normal Mode Voltage Regulator 5V/50 mA/2%

4850H–AUTO–12/07 ATA6620N 10. Package Information 9. Ordering Information Extended Type Number Package Remarks ATA6620N-TAQY SO8 LIN system basis chip, Pb-free, 4k, taped and reeled Package: SO 8 Dimensions in mm specifications according to DIN technical drawings Issue: 1; 15.08.06 Drawing-No.: 6.541-5031.01-4 0.2 5±0.2 3.8±0.1 6±0.2 3.7±0.1 4.9±0.1 3.81 0.4 1.27 0.1+0.15 1.4

4850H–AUTO–12/07 ATA6620N 11. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4850H-AUTO-12/07 • Section 3.1 “Physical Layer Compatibility” on page 3 added 4850G-AUTO-10/07 • Section 9 “Ordering Information” on page 20 changed 4850F-AUTO-07/07

• Put datasheet in a new template
• Capital T for time generally changed in a lower case t
• Section 3.4 “Undervoltage Reset Output (NRES) on page 3 changed
• Section 4.2.2 “Sleep Mode” on page 8 changed
• Section 6 “Voltage Regulator” on page 12 changed
• Section 7 “Absolute Maximum Ratings” on page 13 changed
• Section 8 “Electrical Characteristics” numbers 5.2, 5.3 and 6.8 on page 15 changed 4850E-AUTO-04/07
• Put datasheet in a new template
• ATA6620 in ATA6620N renamed
• Figure 1-1 “Block Diagram” on page 2 changed
• Table 2-1 “Pin Description” on page 2 changed
• Section 4-2 “Modes of Reduced Current Consumption” on page 6 changed
• Figure 4-3 “LIN Wake-up Waveform Diagram from Silent Mode” on page 7 changed
• Section 4.2.2 “Sleep Mode” on page 8 changed
• Figure 4-5 “LIN Wake-up Diagram from Sleep Mode” changed
• Section 4.2.3 “Wake-up from Sleep/Silent Mode at an Insufficient Falling Edge at pin LIN” on page 9 added
• Section 4.3 “Pre-normal Mode” on page 10 changed
• Section 8 “Electrical Characteristics” on pages 14 to 17 changed
• Figure 8-2 “Application Circuit” on page 19 changed 4850D-AUTO-02/06
• Section 3.5 “Bus Pin (LIN)” on page 3 changed
• Figure 4-1 “Mode of Operation” on page 4 changed
• Figure 4-3 “LIN Wake-up Waveform Diagram from Silent Mode” on page 6 changed
• Section 4.4 “Pre-normal Mode” on page 7 changed
• Section 6 “Voltage Regulator” on page 10 changed
• Figure 6-1 “Save Operating Area versus V CC Output Current and Supply Voltage VS at Different Ambient Temperatures” on page 10 changed
• Table “Absolute Maximum Ratings” on page 11 changed
• Table “Electrical Characteristics” from pages 12 to 15 changed

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