ATA6020N

ATA6020N ATMEL | Alldatasheet

Document overview

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Technical content

Rev. 4708C–4BMCU–02/04 Features/Benefits

• Programmable System Clock with Prescaler and Three Different Clock Sources
• Very Low Sleep Current (< 1 µA)
• Very Low Power Consumption in Active, Power-down and Sleep Mode
• 2-Kbyte ROM, 256 4-bit RAM
• 12 Bi-directional I/Os
• Up to 6 External/Internal Interrupt Sources
• Synchronous Serial Interface (2-wire, 3-wire)
• Multifunction Timer/Counter with – Watchdog, POR and Brown-out Function – Voltage Monitoring Inclusive Lo_BAT Detection – Flash Controller ATAM893 Available (SSO20) – Code-efficient Instruction Set – High-level Language Programming with qFORTH Compiler

Description

The ATA6020N is a member of Atmel’s 4-bit single-chip microcontroller family. It con- tains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter with modulator function, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with external clock input and integrated RC-oscillators. Figure 1. Block Diagram

2 K x 8 bit

Figure 2. Pinning SSO20 Package

clock generation with integrated RC-oscillators. enables high-level language programming without any loss of efficiency or code density. Figure 3. MARC4 Core

counts. The return stack can also be used as a temporary storage area. definable location and maximum depth. ter. They are shown in the following programming model. tion to fetch 8-bit wide ROM constants. Figure 6. Programming Model

4708C–4BMCU–02/04 RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. Expression Stack Pointer (SP) The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the expression stack. The pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. Every post-decre- ment operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate the start address of the expression stack area. Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically pre-increments if an element is moved onto the stack, or it post- decrements if an element is removed from the stack. The return stack pointer incre- ments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initial- ized via >RP FCh. RAM Address Registers (X and Y) The X and Y registers are used to address any 4-bit item in RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement address- ing mode arrays in RAM can be compared, filled or moved. Top of Stack (TOS) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus. Condition Code Register (CCR) The 4-bit wide condition code register contains the branch, the carry and the interrupt enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. Carry/Borrow (C) The carry/borrow flag indicates that the borrowing or carrying out of the arithmetic logic unit (ALU) occurred during the last arithmetic operation. During shift and rotate opera- tions, this bit is used as a fifth bit. Boolean operations have no effect on the C-flag. Branch (B) The branch flag controls the conditional program branching. Should the branch flag has been set by a previous instruction a conditional branch will cause a jump. This flag is affected by arithmetic, logic, shift, and rotate operations. Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt rou- tines with the exception of the non-maskable reset. After a reset or on executing the DI instruction, the interrupt enable flag is reset thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an EI or SLEEP instruction.

Figure 7. ALU Zero-address Operations more information refer to the “MARC4 Programmer’s Guide”.

Figure 8. Interrupt Handling (i.e., the interrupt service routine is not yet finished). interrupt active register are all reset. cycles depending on the state of the core).

Table 1. Interrupt Priority Table registers. An overview of the possible hardware configurations is shown in Table 2. Table 2. Hardware Interrupts

ing reset by any external circuitry representing a resistor of less than 150 k. necessary RAM variables, stack pointers and peripheral configuration registers. Figure 9. Reset Configuration The ATA6020N has a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed. stopped). In this power-down mode the brown-out detection is disabled.

register description for BOT programming. Figure 10. Brown-out Detection BOT = 1, low brown-out voltage threshold. (3.0 V is the reset value). BOT = 0, high brown-out voltage threshold (4.0 V). exactly the same manner as a reset stimulus from any of the above sources.

Figure 11. Voltage Monitor Table 3. Voltage Monitor Modes

Figure 14. Clock Module Table 4. Clock Modes temperature and voltage range. selected by default after power-on reset.

Figure 17. RC-oscillator 2 stage. Writing to this register triggers the synchronization cycle. Table 6. Core Speed Select

If bit CCS = 0 in the CM-register, the RC-oscillator 1 always stops. mode by carrying out any interrupt or a reset. Table 8. Power-down Modes

1. Osc-Stop = SLEEP and NSTOP and WDL

Table 7. Oscillator Select

Figure 18. Example of I/O Addressing

Table 9. Peripheral Addresses

4-bit wide bitwise-programmable I/O port. pull-ups and programmable interrupt logic. interface to Timer 2, SSI, voltage monitor input and external interrupt input. useful feature for self-testing and for serial bus applications. up/-down transistor mask option. nal test logic thus disabling the application firmware. switches off the pull-down transistors during reset. Figure 19. Bi-directional Port 2

ful feature for self testing and for serial bus applications. then the high nibble (see section “Addressing Peripherals”). Table 10. Port 2 Control Register

additional mode to generate an SSI-interrupt. 24 shows the internal interfaces to bi-directional Port 4. Table 11. Port 5 Control Register

Figure 22. Bi-directional Port 4 Table 12. Port 4 Control Register

Timer 2 and a Synchronous Serial Interface (SSI). prescaler for Timer 2, the serial interface and the watchdog function. Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O). The SSI operates as a two-wire serial interface or as a shift register for modulation. Figure 23. UTCM Block Diagram prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.

Table 13. Timer 1 Control Bits

of Timer 2 are cascadable as a 12-bit timer or as an 8-bit timer with a 4-bit prescaler. The timer can also be configured as an 8-bit timer and a separate 4-bit prescaler. reset or power-on reset occurs. Table 14. Watchdog Time Control Bits

register internal data output to generate Bi-phase- or Manchester-code. output for a programmable count of pulses. The timer has a 4-bit and an 8-bit compare register for programming the time interval, t. tecture enables the timer function for various modes. Timer 2 compare data values. Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). pare register and 4-bit compare register. Figure 26. Timer 2

Table 15. Timer 2 Clock Select Bits Table 16. Timer 2 Duty Cycle Bits

Figure 39. DCG Output Signals Table 17. Timer 2 Mode Select Bits

as SSI clock or as a clock for the next counter stage. This bit allows the programmer to preset the Timer 2 output T2O. Table 18. Timer 2 Output Select Bits

In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0. can generate an interrupt except on the Timer 2 output mode 7. compare register can generate an interrupt. Table 19. Timer 2 Toggle Mask Bits

line (SD) and BP40 as a shift clock line (SC). stage (T2M2 configured in mode 6). which is in turn modulated in one of the timer functional blocks. Figure 40. Block Diagram of the Synchronous Serial Interface

4708C–4BMCU–02/04 General SSI Operation The SSI is comprised essentially of an 8–bit shift register with two associated 8–bit buff- ers - the receive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for intermediate storage of data to be serially output. Both buffers are directly accessable by software. Transferring the parallel buffer data into and out of the shift reg- ister is controlled automatically by the SSI control, so that both single byte transfers or continuous bit streams can be supported. The SSI can generate the shift clock (SC) either from one of several on-chip clock sources or accept an external clock. The external shift clock is output on, or applied to the Port BP40. Selection of an external clock source is performed by the Serial Clock Direction control bit (SCD). In the combinational modes, the required clock is selected by the corresponding timer mode. The SSI can operate in three data transfer modes – synchronous 8-bit shift mode, a 9-bit Multi-Chip Link mode (MCL), containing 8-bit data and 1-bit acknowledge, and a corresponding 8-bit MCL mode without acknowledge. In both MCL modes the data transmission begins after a valid start condition and ends with a valid stop condition. External SSI clocking is not supported in these modes. The SSI should thus generate and have full control over the shift clock so that it can always be regarded as an MCL-bus master device. All directional control of the external data port used by the SSI is handled automatically and is dependent on the transmission direction set by the Serial Data Direction (SDD) control bit. This control bit defines whether the SSI is currently operating in transmit (TX) mode or receive (RX) mode. Serial data is organized in 8-bit telegrams which are shifted with the most significant bit first. In the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see ’’MCL protocol’’). At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register and proceeds immediately to shift data serially out. At the same time, incoming data is shifted into the shift register input. This incoming data is automatically loaded into the receive buffer when the complete telegram has been received. Data can, if required thus be simultaneously received and transmitted. Before data can be transferred, the SSI must first be activated. This is performed by means of the SSI reset control (SIR) bit. All further operation then depends on the data directional mode (TX/RX) and the present status of the SSI buffer registers shown by the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the (empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX mode). The control logic ensures that data shifting is temporarily halted at any time, if the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will then automatically be set back to '1' and data shifting resumed as soon as the applica- tion software loads the new data into the transmit register (in TX mode) or frees the shift register by reading it into the receive buffer (in RX mode). A further activity status (ACT) bit indicates the present status of serial communication. The ACT bit remains high for the duration of the serial telegram or if MCL stop or start conditions are currently being generated. Both the current SRDY and ACT status can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set high.

Figure 41. 8-bit Synchronous Mode must be set in the 8-bit synchronous mode 1. data is lost or overwritten. contents will overwrite the receive buffer.

acknowledge-bit which is never expected or transmitted. multiple bus control and bus contention will be omitted at this point. All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. detecting this affirmative acknowledge then opens a connection to the required slave. Figure 46. MCL Bus Protocol 1 Both data and clock lines remain HIGH. is HIGH defines a START condition. is HIGH defines a STOP condition. HIGH period of the clock signal.

Figure 47. MCL Bus Protocol 2 of waking the controller out of sleep mode. control bits in P4CR register. conventional bi-directional ports. and ceases when deactivated (SIR = 1). OMSK signal and all following data bits are blanked.

Figure 48. SSI Output Masking Function Table 20. Serial Clock Source Select Bits

(synchronous 8-bit mode only). modes for generating bit streams which are not sub–multiples of 8 bit. Table 21. Serial Mode Control Bits

4708C–4BMCU–02/04 Serial Interface Status and Control Register (SISC) Serial Transmit Buffer (STB) – Byte Write The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting with the most significant bit. Serial Receive Buffer (SRB) – Byte Read The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads content into the receive buffer when complete telegram has been received. Primary register address: ’A’hex Bit 3 Bit 2 Bit 1 Bit 0 SISC write RACK SIM IFN Reset value: 1111b SISC read TACK ACT SRDY Reset value: xxxxb RACK Receive ACKnowledge status/control bit for MCL mode RACK = 0, transmit acknowledge in next receive telegram RACK = 1, transmit no acknowledge in last receive telegram TACK Transmit ACKnowledge status/control bit for MCL mode TACK = 0, acknowledge received in last transmit telegram TACK = 1, no acknowledge received in last transmit telegram SIM Serial Interrupt Mask SIM = 1, disable interrupts SIM = 0, enable serial interrupt. An interrupt is generated. IFN Interrupt FuNction IFN = 1, the serial interrupt is generated at the end of the telegram IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes empty/full in transmit/receive mode) SRDY Serial interface buffer ReaDY status flag SRDY = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full SRDY = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty ACT Transmission ACTive status flag ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions are currently in progress. ACT = 0, transmission is inactive Primary register address: ’9’hex STB First write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: xxxxb Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb Primary register address: ’9’hex SRB First read cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb Second read cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: xxxxb

with the timers and shift the data bits into or out of the shift register. Figure 49. Combination Timer 2 and SSI

ure 54 is an example for a 13-bit Bi-phase telegram. Figure 54. Bi-phase Modulation

4708C–4BMCU–02/04 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., VDD). Voltages are given relative to VSS Parameters Symbol Value Unit Supply voltage VDD -0.3 to +6.5 V Input voltage (on any pin) VIN VSS -0.3 VIN VDD +0.3 V Output short circuit duration tshort Indefinite s Operating temperature range Tamb -40 to +85 C Storage temperature range Tstg -40 to +130 C Thermal resistance (SSO20) RthJA 140 K/W Soldering temperature (t 10 s) Tsld 260 C Operating Characteristics VDD = 5 V, VSS = 0 V, Tamb = -40 to 85°C unless otherwise specified Parameters Test Conditions Symbol Min. Typ. Max. Unit Power supply Active current CPU active Rext = 47 k fSYSCL = fRCext /2 fSYSCL = fRCext /4 IDD 330 170 370 190 µA µA Power down current (CPU sleep, RC-oscillator active) Rext = 47 k fSYSCL = fRCext /2 fSYSCL = fRCext /4 fSYSCL = fRCext /16 IPD µA µA µA Sleep current (CPU sleep, RC-oscillator inactive) VDD = 6.5 V ISleep 0.5 0.8 µA VDD = 5.5 V, VSS = 0 V, Tamb = -40 to +85°C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit Active current CPU active Rext = 47 k fSYSCL = fRCext/2 fSYSCL = fRCext/4 IDD 370 190 410 210 µA µA Power down current (CPU sleep, RC oscillator active) Rext = 47 k fSYSCL = fRCext/2 fSYSCL = fRCext/4 fSYSCL = fRCext/16 IPD µA µA µA

4708C–4BMCU–02/04 VSS = 0 V, Tamb = 25°C unless otherwise specified. All Bi-directional Ports VSS = 0 V, Tamb = -40°C to +85°C unless otherwise specified. Note: The pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller: Parameters Test Conditions Symbol Min. Typ. Max. Unit Power-on Reset Threshold Voltage POR threshold voltage BOT = 1 VPOR 2.5 3.0 3.5 V POR threshold voltage BOT = 0 VPOR 3.5 4.0 4.5 V POR hysteresis VPOR mV Voltage Monitor Threshold Voltage VM high threshold voltage VDD > VM, VMS = 1 VMThh 5.0 5.5 V VM high threshold voltage VDD < VM, VMS = 0 VMThh 4.5 5.0 V VM low threshold voltage VDD > VM, VMS = 1 VMThl 4.0 4.5 V VM low threshold voltage VDD < VM, VMS = 0 VMThl 3.5 4.0 V External Input Voltage VMI VMI > VBG, VMS = 1 VVMI 1.25 1.4 V VMI VMI < VBG, VMS = 0 VVMI 1.1 1.25 V Parameters Test Conditions Symbol Min. Typ. Max. Unit Input voltage LOW VDD = 3.5 V to 6.5 V VIL VSS 0.2 VDD V Input voltage HIGH VDD = 3.5V to 6.5 V VIH 0.8 VDD VDD V Input LOW current (dynamic pull-up) VDD = 3.5 V, VIL= VSS VDD = 6.5 V IIL -15 -50 -30 -100 -50 -200 µA µA Input HIGH current (dynamic pull-down) VDD = 3.5 V, VIH = VDD VDD = 6.5 V IIH 100 200 µA µA Input LOW current (static pull-up) VDD = 3.5 V, VIL= VSS VDD = 6.5 V IIL -120 -300 -250 -600 -500 -1200 µA µA Input LOW current (static pull-down) VDD = 3.5 V, VIH= VDD VDD = 6.5 V IIH 120 300 250 600 500 1200 µA µA Output LOW current VOL = 0.2 VDD VDD = 3.5 V, VDD = 6.5 V IOL mA mA Output HIGH current VOH = 0.8 VDD VDD = 3.5 V, VDD = 6.5 V IOH -16 -24 mA mA

4708C–4BMCU–02/04 AC Characteristics Operation Cycle Time VSS = 0 V Supply voltage VDD = 2.5 V to 6.5 V, VSS = 0 V, Tamb = 25°C unless otherwise specified. Parameters Test Conditions Symbol Min. Typ. Max. Unit System clock cycle VDD = 2.5 V to 6.5 V Tamb = -40C to +85C tSYSCL 0.25 100 µs Parameters Test Conditions Symbol Min. Typ. Max. Unit Timer 2 Input Timing Pin T2I Timer 2 input clock fT2I MHz Timer 2 input LOW time Rise/fall time < 10 ns tT2IL 100 ns Timer 2 input HIGH time Rise/fall time < 10 ns tT2IH 100 ns Interrupt Request Input Timing Interrupt request LOW time Rise/fall time < 10 ns tIRL 100 ns Interrupt request HIGH time Rise/fall time < 10 ns tIRH 100 ns External System Clock EXSCL at OSC1 input ECM = EN Rise/fall time < 10 ns fEXSCL 0.5 MHz EXSCL at OSC1 input ECM = DI Rise/fall time < 10 ns fEXSCL 0.02 MHz Input HIGH time Rise/fall time < 10 ns tIH 0.1 µs Reset Timing Power-on reset time VDD >VPOR tPOR 1.5 ms RC-oscillator 1 Frequency fRcOut1 MHz Stability VDD = 3.5V to 5.5 V Tamb = -40C to +85C f/f ±50 Stabilization time VDD = 3.5 V to 5.5 V tS ms RC-oscillator 2 – External Resistor Frequency Rext = 47 k fRcOut2 1.6 MHz Stability VDD = 3.5 V to 5.5 V Tamb = -40C to +85C f/f Stabilization time VDD = 3.5 V to 5.5 V tS ms External resistor Rext 100 k

available via Port 0 and Port 1 to allow an external access to the on-chip peripherals. ler (target chip) and emulates the lost ports for the application. to analyze the executed instruction sequences and all the I/O activities. Figure 73. MARC4 Emulation

4708C–4BMCU–02/04 Please attach this page to the approval form. Option Settings for Ordering Please select the option settings from the list below and insert ROM CRC. Output Input Output Input Port 2 Port 5 BP20 [ CMOS Pull-up BP50 [ CMOS Pull-up Open drain [N] Pull-down Open drain [N] Pull-down Open drain [P] Pull-up static Open drain [P] Pull-up static Pull-down static Pull-down static BP21 [ CMOS Pull-up BP51 [ CMOS Pull-up Open drain [N] Pull-down Open drain [N] Pull-down Open drain [P] Pull-up static Open drain [P] Pull-up static Pull-down static Pull-down static Port 4 BP52 [ CMOS Pull-up BP40 [ CMOS Pull-up Open drain [N] Pull-down Open drain [N] Pull-down Open drain [P] Pull-up static Open drain [P] Pull-up static Pull-down static Pull-down static BP53 [ CMOS Pull-up BP41 [ CMOS Pull-up Open drain [N] Pull-down Open drain [N] Pull-down Open drain [P] Pull-up static Open drain [P] Pull-up static Pull-down static Pull-down static ECM (External Clock Monitor) BP42 [ CMOS Pull-up Enable Open drain [N] Pull-down Disable Open drain [P] Pull-up static Watchdog Pull-down static Softlock BP43 [ CMOS Pull-up Hardlock Open drain [N] Pull-down Used oscillator Open drain [P] Pull-up static Ext. RC Pull-down static Ext. clock

4708C–4BMCU–02/04

Package Information

Ordering Information

Extended Type Number(1) Program Memory Data-EEPROM Package Delivery ATA6020x-yyy-TKQ 2 kB ROM No SSO20 Taped and reeled ATA6020x-yyy-TKS 2 kB ROM No SSO20 Tubes Note: 1. x = Hardware revision yyy = Customer specific ROM-version technical drawings according to DIN specifications Dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15

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