ATA5724P3-TKQY

ATA5723 ATMEL | Alldatasheet

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Technical content

Features

• Frequency Receiving Range of (3 Versions) –f 0 = 312.5 MHz to 317.5 MHz or –f 0 = 431.5 MHz to 436.5 MHz or –f 0 = 868 MHz to 870 MHz  30 dB Image Rejection  Receiving Bandwidth –B IF = 300 kHz for 315 MHz/433 MHz Version –B IF = 600 kHz for 868 MHz Version  Fully Integrated LC-VCO and PLL Loop Filter  Very High Sensitivity with Power Matched LNA – ATA5723/ATA5724: –107 dBm, FSK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3 –113 dBm, ASK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3 – ATA5728: –105 dBm, FSK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3 –111 dBm, ASK, BR_0 (1.0 kBit/s to 1.8 kBit/s), Manchester, BER 10E-3  High System IIP3 – –18 dBm at 868 MHz – –23 dBm at 433 MHz – –24 dBm at 315 MHz  System 1-dB Compression Point – –27.7 dBm at 868 MHz – –32.7 dBm at 433 MHz – –33.7 dBm at 315 MHz  High Large-signal Capability at GSM Band (Blocking –33 dBm at +10 MHz, IIP3 = –24 dBm at +20 MHz)  Logarithmic RSSI Output  XTO Start-up with Negative Resistor of 1.5 kΩ  5V to 20V Automotive Compatible Data Interface  Data Clock Available for Manchester and Bi-phase-coded Signals  Programmable Digital Noise Suppression  Low Power Consumption Due to Configurable Polling  Temperature Range –40°C to +105°C  ESD Protection 2 kV HBM, All Pins  Communication to Microcontroller Possible using a Single Bi-directional Data Line  Low-cost Solution Due to High Integration Level with Minimum External Circuitry Requirements  Supply Voltage Range 4.5V to 5.5V Benefits  Low BOM List Due to High Integration  Use of Low-cost 13 MHz Crystal  Lowest Average Current Consumption for Application Due to Self Polling Feature  Reuse of ATA5743 Software  World-wide Coverage with One PCB Due to 3 Versions are Pin Compatible UHF ASK/FSK Receiver ATA5723 ATA5724 ATA5728 9106E–RKE–07/08

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 1. Description The ATA5723/ATA5724/ATA5728 is a multi-chip PLL receiver device supplied in an SSO20 package. It has been specially developed for the demands of RF low-cost data transmission sys- tems with data rates from 1 kBit/s to 10 kBbit/s in Manchester or Bi-phase code. Its main applications are in the areas of keyless entry systems, tire pressure monitoring systems, teleme- tering, and security technology systems. It can be used in the frequency receiving range of f0 = 312.5 MHz to 317.5 MHz, f 0 = 431.5 MHz to 436.5 MHz or f 0 = 868 MHz to 870 MHz for ASK or FSK data transmission. All the statem ents made below refer to 315 MHz, 433 MHz and 868.3 MHz applications. Figure 1-1. System Block Diagram Micro- controller PLL UHF ASK/FSK Remote control receiver UHF ASK/FSK Remote control transmitter T5750/53/54 ATA5723/ ATA5724/ ATA5728 LNA VCO PLL XTO Power amp. VCO Antenna Demod. IF Amp Control 1 to 5 XTO Antenna

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Figure 1-2. Block Diagram 4. Order f0 = 1 MHz IF Amp. f or :4 f or :3 Polling Circuit and Control Logic Standby Logic Data Interface Sensitivity reduction Loop Filter f :128 or :64 IF Amp. FSK/ASK Demodulator and Data Filter RSSI Limiter out Dem_out XTO LNA CLK POLLING/_ON IC_ACTIVE XTAL1 XTAL2 MODE DATA_CLK DATA FE RSSI Poly-LPF fg = 7 MHz LPF fg = 2.2 MHz CDEM LNAREF LNAGND LNA_IN DVCC DGND AGND AVCC SENS RSSI LC-VCO

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 2. Pin Configuration Figure 2-1. Pinning SSO20 TEST1 RSSI LNA_IN LNAGND AGND LNAREF SENS IC_ACTIVE CDEM AVCC ATA5723/ ATA5724/ ATA5728 MODE DVCC TEST3 TEST2 XTAL2 XTAL1 DATA POLLING/_ON DGND DATA_CLK Table 2-1. Pin Description Pin Symbol Function

1 SENS Sensitivity-control resistor

2 IC_ACTIVE IC condition indicator: Low = sleep mode, High = active mode

3 CDEM Lower cut-off frequency data filter

4 AVCC Analog power supply

5 TEST 1 Test pin, during operation at GND

6 RSSI RSSI output

7 AGND Analog ground

8 LNAREF High-frequency reference node LNA and mixer

9 LNA_IN RF input

10 LNAGND DC ground LNA and mixer

11 TEST 2 Do not connect during operating

12 TEST 3 Test pin, during operation at GND

13 XTAL1 Crystal oscillator XTAL connection 1

14 XTAL2 Crystal oscillator XTAL connection 2

15 DVCC Digital power supply

16 MODE

Selecting 315 MHz/other versions Low: 315 MHz version (ATA5723) High: 433 MHz/868 MHz versions (ATA5724/ATA5728)

17 DATA_CLK Bit clock of data stream

18 DGND Digital ground

19 POLLING/_ON Selects polling or receiving mode; Low: receiving mode, High: polling mode

20 DATA Data output/configuration input

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 3. RF Front-end The RF front-end of the receiver is a low-IF heterodyne configuration that converts the input sig- nal into about 1 MHz IF signal with a typical image rejection of 30 dB. According to Figure Figure 1-2 on page 3 the front-end consists of an LNA (Low Noise Amplifier), LO (Local Oscillator), I/Q mixer, polyphase low-pass filter and an IF amplifier. The PLL generates the drive frequency fLO for the mixer using a fully integrated synthesizer with integrated low noise LC-VCO (Voltage Controlled Oscillator) and PLL-loop filter. The XTO (crys- tal oscillator) generates the reference frequency fREF =f XTO/2 (868 MHz and 433 MHz versions) or fREF =f XTO/3 (315 MHz version). The integrated LC-VCO generates two or four times the mixer drive frequency f VCO. The I/Q signals for the mixer are generated with a divide by two or four circuit (f LO =f VCO/2 for 868 MHz version, f LO =f VCO/4 for 433 MHz and 315 MHz versions). fVCO is divided by a factor of 128 or 64 and fe eds into a phase frequency detector and is com- pared with f REF. The output of the phase frequency detector is fed into an integrated loop filter and thereby generates the control voltage for the VCO. If f LO is determined, f XTO can be calcu- lated using the following formula: fREF =f LO/128 for 868 MHz band, f REF =f LO/64 for 433 MHz bands, f REF =f LO/64 for 315 MHz bands. The XTO is a two-pin oscillator that operates at the series resonance of the quartz crystal with high current but low voltage signal, so that there is only a small voltage at the crystal oscillator frequency at pins XTAL1 and XTAL2. According to Figure 3-1, the crystal should be connected to GND with two capacitors C L1 and C L2 from XTAL1 and XTAL2 respectively. The value of these capacitors are recommended by the crystal supplier. Due to an inductive impedance at steady state oscillation and some PC B parasitics, a lower value of C L1 and C L2 is normally necessary. The value of CLx should be optimized for the individual board layout to achieve the exact value of fXTO and hence of fLO. (The best way is to use a crystal with known load resonance frequency to find the right value for this capacitor.) When designing the system in terms of receiving band- width and local oscillator accuracy, the accuracy of the crystal and the XTO must be considered. Figure 3-1. XTO Peripherals The nominal frequency f LO is determined by the RF input frequency f RF and the IF frequency f IF using the following formula (low-side injection): fLO = fRF – fIF XTAL2 TEST2 TEST3 XTAL1 DVCC VS CL2 CL1

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 To determine fLO, the construction of the IF filter must be considered. The nominal IF frequency is fIF = 950 kHz. To achieve a good accuracy of the filter corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relationship between fIF and fLO. fIF = fLO/318 for the 315 MHz band (ATA5723) fIF = fLO/438 for the 433.92 MHz band (ATA5724) fIF = fLO/915 for the 868.3 MHz band (ATA5728) The relationship is designed to achieve the nominal IF frequency of: fIF = 987 kHz for the 315 MHz and BIF = 300 kHz (ATA5723) fIF = 987 kHz for the 433.92 MHz and BIF = 300 kHz (ATA5724) fIF = 947.8 kHz for the 868.3 MHz and BIF = 600 kHz (ATA5728) The RF input either from an antenna or from an RF generator must be transformed to the RF input pin LNA_IN. The input impedance of this pin is provided in the electrical parameters. The parasitic board inductances and capacitances influence the input matching. The RF receiver ATA5723/ATA5724/ATA5728 exhibits its highest sensitivity if the LNA is power matched. Because of this, matching to a SAW filter, a 50Ω or an antenna is easier. Figure 14-1 on page 32 “Application Circuit” shows a typical input matching network for fRF = 315 MHz, fRF = 433.92 MHz or fRF = 868.3 MHz to 50Ω. The input matching network shown in Table 14-2 on page 32 is the reference network for the parameters given in the electrical characteristics. 4. Analog Signal Processing

4.1 IF Filter

The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is: f IF = 987 kHz for the 315 MHz and BIF = 300 kHz (ATA5723) fIF = 987 kHz for the 433.92 MHz and BIF = 300 kHz (ATA5724) fIF = 947.9 kHz for the 868.3 MHz and BIF = 600 kHz (ATA5728) The nominal bandwidth is 300 kHz for ATA5723 and ATA5724 and 600 kHz for ATA5728.

4.2 Limiting RSSI Amplifier

The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is ΔRRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is approximately 60 dB higher compared to the RF input signal at full sensitivity. The S/N ratio is not affected by the dynamic range of the RSSI amplifier in FSK mode because only the hard limited signal from a high-gain limiting amplifier is used by the demodulator. The output voltage of the RSSI amplifier (VRSSI) is available at pin RSSI. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable input power range PRef is –100 dBm to –55 dBm.

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728

4.3 FSK/ASK Demodulator and Data Filter

The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulat or is set using the bit ASK/_FSK in the OPMODE register. Logic L sets the demodulator to FSK, applying H to ASK mode. In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection refer- ence voltage to a value where a good signal to noise ratio is achieved. This circuit also implements the effective suppression of any kind of in-band noise signals or competing transmit- ters. If the S/N (ratio to suppress in-band noise signals) exceeds about 10 dB the data signal can be detected properly. However, better values are found for many modulation schemes of the competing transmitter. The FSK demodulator is intended to be used for an FSK deviation of 10 kHz ≤Δf ≤100 kHz. The data signal in FSK mode can be detected if the S/N (ratio to suppress in-band noise signals) exceeds about 2 dB. This value is valid for all modulation schemes of a disturber signal. The output signal of the demodulator is filtered by t he data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its pass-band can be adopted to the characteristics of the data signal. The data filter consists of a 1 st order high-pass and a 2nd order low-pass filter. The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following formula: In self-polling mode the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the low-pass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is defined in the OPMODE register (refer to Section 11. “Configur- ing the Receiver” on page 25). The BR_Range must be set in accordance to the baud-rate used. The ATA5723/ATA5724/ATA5728 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V DC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 2 dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (t ee_sig ). These limits are defined in the el ectrical characteristics. They should not be exceeded to main- tain full sensitivity of the receiver. fcu_DF 1

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 5. Receiving Characteristics The RF receiver ATA5723/ATA5724/ATA5728 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectiv- ity and large signal capability. The receiving frequency response without a SAW front-end filter is illustrated in Figure 5-1 “Narrow Band Receiving Frequency Response ATA5724”. This example relates to ASK mode. FSK mode exhibits a simila r behavior. The plots ar e printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 3 dB must be consid- ered, but the overall selectivity is much better. When designing the system in te rms of receiving bandwidth, the LO deviation must be consid- ered as it also determines the IF center frequency. The total LO deviation is calculated, to be the sum of the deviation of the crystal and the XTO deviation of the ATA5723/ATA5724/ATA5728. Low-cost crystals are specified to be within ±90 ppm over tolerance, temperature, and aging. The XTO deviation of the ATA5723/ATA5724/ATA5728 is an additional deviation due to the XTO circuit. This deviation is specified to be ±10 ppm worst case for a crystal with CM = 7 fF. If a crystal of ±90 ppm is used, the total deviation is ±100 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode. Figure 5-1. Narrow Band Receiving Frequency Response ATA5724 -10 -20 -30 -40 -50 -60 -70 (dB) 5.5V -40˚C 4.5V -40˚C 5V 25˚C 5.5V 25˚C 4.5V 105˚C 5.5V 105˚C 5V 105˚C 4.5V 25˚C 5V -40˚C 430 431 432 433 (MHz) Image Rejection versus RF Frequency 434 435 436 437 438

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 6. Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor- responding transmitter. This is achieved using t he polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected, the receiver remains active and trans- fers the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called poll- ing mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, sys- tem response time, data rate etc. The receiver is very flexible with regards to the number of connection wires to the microcon- troller. It can be either operated by a single bi -directional line to save ports to the connected microcontroller or it can be operated by up to five uni-directional ports. 7. Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. This clock cycle TClk is derived from the crystal oscillator (X TO) in combination with a divide by 28 or 30 circuit. According to Section 3. “RF Front-end” on page 5, the frequency of the crystal oscilla- tor (fXTO) is defined by the RF input signal (f RFin) which also defines the operating frequency of the local oscillator (f LO). The basic clock cycle for ATA5724 and ATA5728 is T Clk 28/fXTO giving basic clock cycle is TClk =3 0 / fREF giving TClk = 2.0382 µs for fRF =3 1 5M H z . TClk controls the following application-relevant parameters:  Timing of the polling circuit including bit check  Timing of the analog and digital signal processing  Timing of the register programming  Frequency of the reset marker  IF filter center frequency (fIF0) Most applications are dominated by three transmission frequencies: f Transmit = 315 MHz is mainly used in USA, fTransmit = 868.3 MHz and 433.92 MHz in Europe. All timings are based on TClk. For the aforementioned frequencies, TClk is given as:  Application 315 MHz band (fXTO = 14.71875 MHz, fLO = 314.13 MHz, TClk = 2.0382 µs)  Application 868.3 MHz band (f XTO = 13.55234 MHz, fLO = 867.35 MHz, TClk = 2.066 µs)  Application 433.92 MHz band (f XTO = 13.52875 MHz, fLO = 432.93 MHz, TClk = 2.0696 µs) For calculation of T Clk for applications using other frequency bands, see table in Section 18. “Electrical Characteristics ATA5724, ATA5728” on page 37.

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range), which is defined in the OPMODE register. This clock cycle T XClk is defined by the following formulas: BR_Range = BR_Range0: T XClk = 8 × TClk BR_Range1: T XClk = 4 × TClk BR_Range2: T XClk = 2 × TClk BR_Range3: T XClk = 1 × TClk 8. Polling Mode According to Figure 8-1 on page 12 , the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode the signal processing circuitry is disabled for the time period TSleep while consuming low current of I S =I Soff. During the start-up period, T Startup, all sig- nal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit-by-bit and compared with a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period T Bit-check . This period varies according to each check as it is a statistical process. An average value for TBitcheck is given in the electrical characte ristics. During T Startup and TBit-check, the current consumption is I S =I Son. The condition of the receiver is indicated on pin IC_ACTIVE. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitt er must start the telegram with an adequate preburst. The required length of the preburst depends on the polling parameters T Sleep, TStartup, TBit-check and the start-up time of a connected microcontroller, T Start_microcontroller . Thus, T Bit-check depends on the actual bit rate and the number of bits (NBit-check) to be tested. The following formula indicates how to calculate the preburst length. TPreburst ≥ TSleep + TStartup + TBit-check + TStart_microcontroller

8.1 Sleep Mode

The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the exten- sion factor X Sleep (according to Table 11-8 on page 27 ), and the basic clock cycle T Clk. It is calculated to be: TSleep =S l e e p× XSleep × 1024 × TClk The maximum value of T Sleep is about 60 ms if X Sleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd to “1”. Setting the configuration word Sleep to its maximal value puts the receiver into a permanent sleep mode. The receiver remains in this state until another value for Sleep is programmed into the OPMODE register. This is particularily usef ul when several devices share a single data line. (It can also be used for microcontroller polling: using pin POLLING/_ON, the receiver can be switched on and off.) ISpoll ISoff TSleep ISon TStartup TBit-check+()×+×

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Figure 8-1. Polling Mode Flow Chart Bit-check Mode: The incoming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. Output level on Pin IC_ACTIVE = > high T Bit-check IS = ISon Start-up Mode: The signal processing circuits are enabled. After the start-up time (T Startup) all circuits are in stable condition and ready to receive. Output level on Pin IC_ACTIVE = > high T Startup IS = ISon Receiving Mode: The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via Pin DATA or Polling/_ON. Output level on Pin IC_ACTIVE = > high I S = ISon Sleep Mode: All circuits for signal processing are disabled. Only XTO and Polling logic are enabled. Output level on Pin IC_ACTIVE = > low T Sleep = Sleep × XSleep × 1024 × TClk IS = ISoff Bit Check OK ? 5-bit word defined by Sleep 0 to Sleep 4 in OPMODE register Sleep: Is defined by the selected baud rate range and TClk. The baud-rate range is defined by Baud 0 and Baud 1 in the OPMODE register. T Startup: Basic clock cycle defined by f XTO and Pin MODE TClk: If the bit check fails, the average time period for that check depends on the selected baud-rate range and on T Clk. The baud-rate range is defined by Baud 0 and Baud 1 in the OPMODE register. If the bit check is ok, T Bit-check depends on the number of bits to be checked (NBit-check) and on the data rate used. Depends on the result of the bit checkTBit-check: Extension factor defined by XSleepStd according to Table 11-8 XSleep: OFF Command YES NO

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728

8.2 Bit-check Mode

In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a pro- grammable time window. The maximum number of these edge-to-edge tests, before the receiver switches to receiving mode, is also programmable.

8.3 Configuring the Bit Check

Assuming a modulation scheme that contains tw o edges per bit, two time frame checks verify one bit. This is valid for Manchester, Bi-phase, and most other modulation schemes. The maxi- mum count of bits to be checked can be set to 0, 3, 6, or 9 bits using the variable N Bit-check in the OPMODE register. This implies 0, 6, 12, and 18 edge-to-edge checks respectively. If N Bit-check is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if N Bit-check is set to a lower value. In polling mode, the bit-check time is not dependent on NBit-check. Figure 8-2 shows an example where three bits are tested successfully and the data signal is transferred to pin DATA. Figure 8-2. Timing Diagram for Complete Successful Bit Check According to Figure 8-3, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time t ee is in between the lower bit-check limit T Lim_min and the upper bit-check limit TLim_max, the check continues. If tee is smaller than TLim_min or tee exceeds TLim_max, the bit check is terminated and the receiver switches to sleep mode. Figure 8-3. Valid Time Window for Bit Check IC_ACTIVE Data_out (DATA) Dem_out Bit check TBit-check Start-up mode (Number of checked Bits: 3) Bit check ok 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit1/2 Bit1/2 Bit Start-check mode Receiving mode TStart-up 1/fSig tee TLim_max TLim_min Dem_out

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Figure 8-5. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min) Figure 8-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)

8.4 Duration of the Bit Check

If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit check is a statistical process and TBit-check varies for each check. Therefore, an average value for T Bit-check is given in the electrical characteristics. T Bit-check depends on the selected baud-rate range and on T Clk. A higher baud-rate range causes a lower value for TBit-check resulting in a lower current consumption in polling mode. In the presence of a valid transmitter signal, T Bit-check is dependent on the frequency of that sig- nal, fSig, and the count of the checked bits, NBit-check. A higher value for NBit-check thereby results in a longer period for TBit-check requiring a higher value for the transmitter pre-burst TPreburst.

8.5 Receiving Mode

If the bit check was successful for all bits specified by NBit-check, the receiver switches to receiving mode. According to Figure 8-2 on page 13 , the internal data signal is switched to pin DATA in that case, and the data clock is available after the start bit has been detected (see Figure 9-1 on page 20). A connected microcontroller can be woken up by the negative edge at pin DATA or by the data clock at pin DATA_CLK. The receiver stays in that condition until it is switched back to polling mode explicitly. IC_ACTIVE Bit-check counter Dem_out Bit check TBit-check Sleep mode TSleep Start-up mode (Lim_min = 14, Lim_max = 24) Bit check failed (CV_Lim_ < Lim_min) 8674 5 1112 91 02315634120 1/2 Bit Bit-check mode TStart-up IC_ACTIVE Bit-check counter Dem_out Bit check TBit-check Sleep mode TSleep Start-up mode (Lim_min = 14, Lim_max = 24) Bit check failed (CV_Lim ≥ Lim_max) 23 2421 2219 208674 5 17 18 15 1613 14111291 023715634120 1/2 Bit Bit-check mode TStart-up

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728

8.6 Digital Signal Processing

The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud-rate range (BR_Range). Figure 8-7 illustrates how Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the bit-check counter. Data can change its state only after TXClk has elapsed. The edge-to-edge time period tee of the Data signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to t ee ≥ TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time it limits the max- imum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. The maximum time period for DATA to stay low is limited to T DATA_L_max . This function is employed to ensure a finite response time in programming or switching off the receiver via pin DATA. TDATA_L_max is therefore longer than the maximum time period indicated by the transmitter data stream. Figure 8-9 on page 17 gives an example where Dem_out remains Low after the receiver has switched to receiving mode. Figure 8-7. Synchronization of the Demodulator Output Figure 8-8. Debouncing of the Demodulator Output Data_out (DATA) Clock bit-check counter Dem_out TXClk tee Data_out (DATA) Dem_out teeteetee tDATA_min tDATA_min tDATA_min

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Figure 8-9. Steady L State Limited DATA Output Pattern After Transmission After the end of a data transmission, the receiver remains active. Depending of the bit Noise_Disable in the OPMODE register, the output signal at pin DATA is high or random noise pulses appear at pin DATA (see Section 10. “Digital Noise Suppression” on page 23 ). The edge-to-edge time period tee of the majority of these noise pulses is equal or slightly higher than TDATA_min.

8.7 Switching the Receive r Back to Sleep Mode

The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON. When using pin DATA, this pin must be pulled to low by the connected microcontroller for the period t1. Figure 8-10 on page 18 illustrates the timing of the OFF command (see Figure 13-2 on page 30). The minimum value of t1 depends on the BR_Range. The maximum value for t1 is not limited; however, exceeding the specified value to prevent erasing the reset marker is not rec- ommended. Note also that an internal reset for the OPMODE and the LIMIT register is generated if t1 exceeds the specified values. This item is explained in more detail in the Section 11. “Configuring the Receiver” on page 25 . Setting the receiver to sleep mode via DATA is achieved by programming bit 1 to “1” during the register configuration. Only one sync pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2, and t10. The sleep time T Sleep elapses after the OFF command. Note that the capacitive load at pin DATA is limited (see Section 14. “Data Interface” on page 32). IC_ACTIVE Data_out (DATA) Dem_out Bit check t DATA_L_maxtDATA_min Receiving modeStart-up mode Bit-check mode

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Figure 8-11 “Timing Diagram of the OFF Command using Pin POLLING/_ON” illustrates how to set the receiver back to polling mode using pi n POLLING/_ON. The pin POLLING/_ON must be held to low for the time period t on2. After the positive edge on pin POLLING/_ON and the delay ton3, the polling mode is active and the sleep time TSleep elapses. Using the POLLING/_ON command is faster than using pin DATA; however, this requires the use of an additional connection to the microcontroller. Figure 8-12 “Activating the Receiving Mode using Pin “POLLING/_ON” illustrates how to set the receiver to receiving mode using the pin POLLING/_ON. The pin POLLING/_ON must be held to low. After the delay t on1, the receiver changes from sleep mode to start-up mode regardless of the programmed values for TSleep and NBit-check. As long as POLLING/_ON is held to low, the val- ues for T Sleep and N Bit-check is ignored, but not deleted (see Section 10. “Digital Noise Suppression” on page 23). If the receiver is polled excl usively by a microcontroller, T Sleep must be programmed to 31 (per- manent sleep mode). In this case the receiver remains in sleep mode as long as POLLING/_ON is held to high. 9. Data Clock The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift reg- ister. Using this data clock, a microcontroller can easily synchronize the data stream. This clock can only be used for Manchester and Bi-phase coded signals.

9.1 Generation of the Data Clock

After a successful bit check, the receiver switc hes from polling mode to receiving mode and the data stream is available at pin DATA. In receiving mode, the data clock control logic (Man- chester/Bi-phase demodulator) is active and exam ines the incoming data stream. This is done, as with the bit check, by subsequent time frame checks where the distance between two edges is continuously compared to a programmable time window. As illustrated in Figure 9-1 on page 20, only two distances between two edges in Ma nchester and Bi-phase coded signals are valid (T and 2T). The limits for T are the same as used with the bit check. They can be programmed in the LIMIT-register (Lim_min and Lim_max, see Table 11-10 on page 28 and Table 11-11 on page 28). The limits for 2T are calculated as follows: Lower limit of 2T: Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2 Upper limit of 2T: Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2 (If the result for ’Lim_min_2T’ or ’Lim_max_2T’ is not an integer value, it is rounded up.) The data clock is available, after the data clock control logic has detected the distance 2T (Start bit) and is issued with the delay t Delay after the edge on pin DATA (see Figure 9-1 on page 20). If the data clock control logic detects a timing or logical error (Manchester code violation), as illustrated in Figure 9-2 on page 20 and Figure 9-3 on page 21 , it stops the output of the data clock. The receiver remains in re ceiving mode and starts with the bit check. If the bit check was successful and the start bit has been detected, the data clock control logic starts again with the generation of the data clock (see Figure 9-4 on page 21).

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 10. Digital Noise Suppression After a data transmission, digital noise appears on the data output (see Figure 10-1 “Output of Digital Noise at the End of the Data Stream”). To prevent digital noise keeping the connected microcontroller busy, it can be suppressed in two different ways:  Automatic Noise Suppression  Controlled Noise Suppression by the Microcontroller

10.1 Automatic Noise Suppression

The receiver changes to bit-check mode at the end of a valid data stream if the bit Noise_Disable (Table 11-9 on page 27) in the OPMODE register is set to 1 (default). The digital noise is suppressed, and the level at pin DATA is high. The receiver changes back to receiving mode, if the bit check was successful. This method of noise suppression is recommended if the data stream is Manchester or Bi-phase coded and is active after power on. Figure 10-3 “Occurrence of a Pulse at the End of the Data Stream” illustrates the behavior of the data output at the end of a data stream. If the last period of the data stream is a high period (ris- ing edge to falling edge), a pulse occurs on pin DATA. The length of the pulse depends on the selected baud-rate range. Figure 10-1. Output of Digital Noise at the End of the Data Stream Figure 10-2. Automatic Noise Suppression DATA_CLK Data_out (DATA) DataPreburst Receiving mode, data clock control logic active Receiving mode, data clock control logic active Bit-check mode Bit check ok Receiving mode, bit check active Receiving mode, bit check active Data Digital Noise Digital NoiseDigital NoisePreburst Bit check ok DATA_CLK Data_out (DATA) DataPreburst Receiving mode, data clock control logic active Receiving mode, data clock control logic active Bit-check mode Bit-check mode Bit-check mode Bit check ok DataPreburst Bit check ok

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Figure 10-3. Occurrence of a Pulse at the End of the Data Stream

10.2 Controlled Noise Suppre ssion by the Microcontroller

Digital noise appears at the end of a valid data stream if the bit Noise_Disable (see Table 11-9 on page 27) in the OPMODE register is set to 0. To suppress the noise, the pin POLLING/_ON must be set to low. The receiver remains in receiving mode. The OFF command then causes a change to start-up mode. The programmed sleep time (see Table 11-7 on page 27 ) is not exe- cuted because the level at pin POLLING/_ON is lo w; however, the bit check is active in this case. The OFF command also activates the bit check if the pin POLLING/_ON is held to low. The receiver changes back to receiving mode if the bit check was successful. To activate the polling mode at the end of the data transmission, the pin POLLING/_ON must be set to high. This way of suppressing the noise is recommended if the data stream is not Manchester or Bi-phase coded. Figure 10-4. Controlled Noise Suppression Data_out (DATA) DATA_CLK Dem_out '1' '1' Digital noiseData stream Receiving mode, data clock control logic active Bit-check mode '1' tee < TLim_min or TLim_max < tee < tLim_min_2T or tee > TLim_max_2T Timing error Tpulse Tee POLLING/_ON (DATA_CLK) Serial bi-directional data line DataPreburst Receiving modeReceiving mode Start-up mode Sleep mode Bit-check mode Bit-check mode Bit check ok Data Digital NoiseDigital NoisePreburst OFF-command Bit check ok

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 11. Configuring the Receiver The ATA5723/ATA5724/ATA5728 receiver is configured using two 12-bit RAM registers called OPMODE and LIMIT. The registers can be progr ammed by means of the bidirectional DATA port. If the register content has changed due to a voltage drop, this condition is indicated by a the output pattern called reset marker (RM). If this occurs, the receiver must be reprogrammed. After a Power-On Reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 11-3 on page 25 shows the structure of the registers. According to Table 11-1, bit 1 defines whether the receiver is set back to polling mode using the OFF command (see “Receiving Mode” on page 15) or whether it is programmed. Bit 2 represents the register address. It selects the appropriate register to be pro- grammed. For high programming reliability, bit 15 (Stop bit), at the end of the programming operation, must be set to 0. Table 11-1. Effect of Bit 1 and Bit 2 on Programming the Registers Bit 1 Bit 2 Action 1 x The receiver is set back to polling mode (OFF command) 0 1 The OPMODE register is programmed 0 0 The LIMIT register is programmed Table 11-2. Effect of Bit 15 on Programming the Register Bit 15 Action

0 The values are written into t he register (OPMODE or LIMIT)

1 The values are not written into the register

Table 11-3. Effect of the Configuration Words within the Registers Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 OFF command – OPMODE register – BR_Range N Bit-check Modu- lation Sleep X Sleep Noise Suppression Baud1 Baud0 BitChk1 BitChk0 ASK/ _FSK Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 X SleepStd Noise_ Disable Default values of Bit 3...14 00 0 10 0 0 1 10 0 1 – – LIMIT register – Lim_min Lim_max – Lim_ min5 Lim_ min4 Lim_ min3 Lim_ min2 Lim_ min1 Lim_ min0 Lim_ max5 Lim_ max4 Lim_ max3 Lim_ max2 Lim_ max1 Lim_ max0 0 Default values of Bit 3...14 01 0 10 1 1 0 10 0 1 –

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 The following tables illustrate the effect of the individual configuration words. The default config- uration is highlighted for each word. BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits TLim_min and TLim_max as shown in Table 11-10 on page 28 and Table 11-11 on page 28. Table 11-4. Effect of the configuration word BR_Range BR_Range Baud-rate Range/Extension Factor for Bit-check Limits (XLim)Baud1 Baud0 BR_Range0 (BR_Range0 = 1.0 kBit/s to 1.8 kBit/s) XLim = 8 (default) BR_Range1 (BR_Range1 = 1.8 kBit/s to 3.2 kBit/s) XLim = 4 BR_Range2 (BR_Range2 = 3.2 kBit/s to 5.6 kBit/s) XLim = 2 BR_Range3 (BR_Range3 = 5.6 kBit/s to 10 kBit/s) XLim = 1 Table 11-5. Effect of the Configuration word NBit-check NBit-check Number of Bits to be CheckedBitChk1 BitChk0 00 0 0 1 3 (default) 10 6 11 9 Table 11-6. Effect of the Configuration Bit Modulation Modulation Selected Modulation ASK/_FSK –

0 FSK (default)

1 ASK

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Table 11-7. Effect of the Configuration Word Sleep Sleep Start Value for Sleep Counter (TSleep = Sleep × XSleep × 1024 × TClk)Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 00000 0 (Receiver polls continuously until a valid signal occurs) 00001 If XSleep = 1 TSleep = 2.11 ms for fRF = 868.3 MHz, TSleep = 2.12 ms for fRF = 433.92 MHz TSleep = 2.08 ms for fRF = 315 MHz 00010 2 00011 3 00110 If XSleep = 1 TSleep = 12.69 ms for fRF = 868.3 MHz, TSleep = 12.71 ms for fRF = 433.92 MHz TSleep = 12.52 ms for fRF = 315 MHz 11101 2 9 11110 3 0 1 1 1 1 1 31 (permanent sleep mode) Table 11-8. Effect of the Configuration Bit XSleep XSleep Extension Factor for Sleep Time (TSleep = Sleep × XSleep × 1024 × TClk)XSleepStd 0 1 (default) Table 11-9. Effect of the Configuration Bit Noise Suppression Noise Suppression Suppression of the Digital Noise at Pin DATANoise_Disable

0 Noise suppression is inactive

1 Noise suppression is active (default)

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Note: 1. Lim_min is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 19). Note: 1. Lim_max is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 19). Table 11-10. Effect of the Configuration Word Lim_min Lim_min(1) (Lim_min < 10 is not Applicable) Lower Limit Value for Bit Check Lim_min5 Lim_min4 Lim_min3 Li m_min2 Lim_min1 Lim_min0 (T Lim_min = Lim_min × XLim × TClk) 001010 1 0 001011 1 1 001100 1 2 010101 21 (default, BR_Range0) Lim_min = 347 µs for fRF = 868.3 MHz TLim_min = 347 µs for fRF = 433.92 MHz TLim_min = 342 µs for fRF = 315 MHz) 111101 6 1 111110 6 2 111111 6 3 Table 11-11. Effect of the Configuration Word Lim_max Lim_max(1) (Lim_max < 12 is not applicable) Upper Limit Value for Bit Check Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_ma x1 Lim_max0 (TLim_max = (Lim_max – 1) × XLim × TClk) 001100 1 2 001101 1 3 001110 1 4 101001 41 (default, BR_Range0) Lim_max = 661 µs for fRF = 868.3 MHz TLim_max = 662 µs for fRF = 433.92 MHz TLim_max = 652 µs for fRF = 315 MHz) 111101 6 1 111110 6 2 111111 6 3

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 12. Conservation of the Register Information The ATA5723/ATA5724 uses an integrated power-on reset and brown-out detection circuitry as a mechanism to preserve the RAM register information. According to Figure 12-1, a power-on reset (POR) is generated if the supply voltage V S drops below the threshold voltage VThReset. The default parameters are programmed into the configura- tion registers in that condition. The POR is cancelled after the minimum reset period tRst when VS exceeds VThReset. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. The RM is represented by the fixed frequency f RM at a 50% duty-cycle. RM can be cancelled using a low pulse t1 at pin DATA. The RM has the following characteristics: f RM is lower than the lowest feasible frequency of a data signal. Due to this, RM cannot be misinterpreted by the connected microcontroller.  If the receiver is set back to polling mode using pin DATA, RM cannot be cancelled accidentally if t1 is applied as described in the proposal in Section 13. “Programming the Configuration Register” on page 30. Using this conservation mechanis m, the receiver cannot lose its register information without communicating this condition using the reset marker RM. Figure 12-1. Generation of the Power-on Reset POR Data_out (DATA) X tRst VThresetVS 1/fRM

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack) occurs if the ju st programmed mode word is equivalent to the mode word that was already stored in that regi ster. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. A register can be programmed when the receiver is in both sleep-mode and active mode. During programming, the LNA, LO, low-pass filter, IF-amplifier, and the FSK/MSK demodulator are dis- abled. The t1 pulse is used to start the programming or to switch the receiver back to polling mode (OFF command). (The receiver is switched back to polling mode with the OFF command if bit 1 is set to „1“.) The following convention should be considered for the length of the program- ming start pulse t1: Using a t1 value of t1 (min) < t1 < 5632 TClk (where t1 (min) is the minimum specified value for the relevant BR_Range) when the receiver is active i.e., not in reset mode initiates the program- ming or OFF command. However, if this t1 value is used when the receiver is in reset mode, programming or OFF command is NOT initiated and RM remains present at pin DATA. Note, the RM cannot be deleted when using this t1 value. Using a t1 value of t1 > 7936 ´ TClk, programming or OFF command is initiated when the receiver is in both reset mode and active mode. The registers PMODE and LIMIT are set to the default values and the RM is deleted, if present . This t1 values can be used if the connected microcontroller detects an RM. Addi tionally, this t1 value can generally be used if the receiver operates in default mode. Note that the capacitive load at pin DATA is limited.

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 14. Data Interface The data interface (see Figure 13-2 on page 30) is designed for automotive requirements. It can be connected using the pull-up resistor Rpup up to 20V and is short-circuit-protected. The applicable pull-up resistor R pup depends on the load capacity C L at pin DATA and the selected BR_range (see Table 14-1). Figure 14-1. Application Circuit: fRF = 315 MHz(1), 433.92 MHz or without SAW Filter Note: For 315 MHz application pin MODE must be connected to GND. Table 14-1. Applicable Rpup - BR_range Applicable R pup CL ≤ 1nF B0 1.6 k Ω to 47 kΩ B1 1.6 k Ω to 22 kΩ B2 1.6 k Ω to 12 kΩ B3 1.6 k Ω to 5.6 kΩ CL ≤ 100pF B0 1.6 k Ω to 470 kΩ B1 1.6 k Ω to 220 kΩ B2 1.6 k Ω to 120 kΩ B3 1.6 k Ω to 56 kΩ LNAGND LNA_IN LNAREF AGND RSSI TEST1 AVCC CDEM IC_ACTIVE SENS TEST2 TEST3 XTAL1 XTAL2 DVCC MODE DATA_CLK DGND POLLING/_ON DATA F crystal CL2 GND C16 C17RF_IN VS 1.6 kΩ 56 kΩ to 150 kΩ CL1 DATA_CLK Sensitivity reduction POLLING/_ON DATA C12 10 nF 10% C13 10 nF 10% C14 39 nF 4.7 µF 10% VX = 5V to 20V IC_ACTIVE RSSI ATA5723 ATA5724 ATA5728 Table 14-2. Input Matching to 50Ω RF Frequency (MHz) LNA Matching Crystal Frequency fXTAL (MHz)C16 (pF) C17 (pF) L1 (nH) 315 Not connected 3 39 14.71875 433.92 Not connected 3 20 13.52875 868.3 1 3 6.8 13.55234

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 15. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage V S 6V Power dissipation P tot 1000 mW Junction temperature T j 150 °C Storage temperature T stg –55 +125 °C Ambient temperature T amb –40 +105 °C Maximum input level, input matched to 50Ω Pin_max 10 dBm 16. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 100 K/W

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 17. Electrical Characteristics ATA5723 All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315 MHz unless otherwise specified (For typical values: VS =5 V , Tamb = 25°C). No. Parameter Test Conditions Symbol fRF = 315 MHz

14.71875 MHz Oscillator Variable Oscillator

1 Basic Clock Cycle of the Digital Circuitry

1.1 Basic clock

cycle TClk 2.0382 2.0382 30/f XTO 30/fXTO µs A 1.2 Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 T XClk 16.3057 8.1528 4.0764 2.0382 16.3057 8.1528 4.0764 2.0382 8 × TClk 4 × TClk 2 × TClk 1 × TClk 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs A

2 Polling Mode

2.1 Sleep time (see Figure 8-1, Figure 8-10 and Figure 13-1) Sleep and XSleep are defined in the OPMODE register T Sleep Sleep × XSleep × 1024 × 2.0382 Sleep × XSleep × 1024 × 2.0382 Sleep × XSleep × 1024 × TClk Sleep × XSleep × 1024 × TClk ms A 2.2 Start-up time (see Figure 8-1 and Figure 8-4) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Startup 1827 1044 1044 653 1827 1044 1044 653 896.5 512.5 512.5 320.5 × T Clk 896.5 512.5 512.5 320.5 × T Clk µs µs µs µs µs A 2.3 Time for bit check (see Figure 8-1 Average bit-check time while polling, no RF applied (see Figure 8-5 and Figure 8-6) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Bit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms C 2.4 Time for bit check (see Figure 8-1 Bit-check time for a valid input signal f Sig (see Figure 8-5) NBit-check = 0 NBit-check = 3 NBit-check = 6 NBit-check = 9 TBit-check 1 × TXClk 3/fSig 6/fSig 9/fSig 1 × TXClk 3.5/fSig 6.5/fSig 9.5/fSig 1 × TXClk 3/fSig 6/fSig 9/fSig 1 × TClk 3.5/fSig 6.5/fSig 9.5/fSig ms ms ms ms C

3 Receiving Mode

3.1 Intermediate

IF 987 f IF = fLO/318 kHz A

3.2 Baud-rate

BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 BR_Range0 × 2 µs/T Clk BR_Range1 × 2 µs/TClk BR_Range2 × 2 µs/TClk BR_Range3 × 2 µs/TClk kBit/s kBit/s kBit/s kBit/s A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 3.3 Minimum time period between edges at pin DATA (see Figure 4-2 and Figure 8-8, Figure 8-9) (With the exception of parameter T Pulse) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 tDATA_min 163.06 81.53 40.76 20.38 163.06 81.53 40.76 20.38 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk µs µs µs µs A 3.4 Maximum Low period at pin DATA (see Figure 4-2) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t DATA_L_max 2120 1060 530 265 2120 1060 530 265 130 × T XClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk µs µs µs µs A 3.5 Delay to activate the start-up mode (see Figure 8-12) Ton1 19.36 21.4 9.5 × T Clk 10.5 × TClk µs A 3.6 OFF command at pin POLLING/ _ON (see Figure 8-11) Ton2 16.3 8 × T Clk µs A 3.7 Delay to activate the sleep mode (see Figure 8-11) Ton3 17.32 19.36 8.5 × T Clk 9.5 × TClk µs A 3.8 Pulse on pin DATA at the end of a data stream (see Figure 10-3) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Pulse 16.3 8.15 4.07 2.04 16.3 8.15 4.07 2.04 8 × T Clk 4 × TClk 2 × TClk 1 × TClk 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs C 17. Electrical Characterist ics ATA5723 (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315 MHz unless otherwise specified (For typical values: VS =5 V , Tamb = 25°C). No. Parameter Test Conditions Symbol fRF = 315 MHz *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728

4 Configuration of the Receiver (see Figure 12-1 and Figure 13-1)

4.1 Frequency of the reset marker Frequency is stable within 50 ms after POR f RM 119.78 119.78 (4096 × TClk) (4096 × TClk) Hz A

4.2 Programming

BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR 3310 2242 1708 1441 16175 11479 11479 11479 11479 1624 × T Clk 1100 × TClk 838 × TClk 707 × TClk 7936 × TClk 5632 × TClk 5632 × TClk 5632 × TClk 5632 × TClk µs µs µs µs µs A

4.3 Programming

delay period t2 783 785 384.5 × T Clk 385.5 × TClk µs A

4.4 Synchroniza-

tion pulse t3 261 261 128 × TClk 128 × TClk µs A 4.5 Delay until of the program window starts t4 129 129 63.5 × T Clk 63.5 × TClk µs A

4.6 Programming

window t5 522 522 256 × TClk 256 × TClk µs A

4.7 Time frame

of a bit t6 1044 1044 512 × TClk 512 × TClk µs A

4.8 Programming

pulse t7 130.5 522 64 × TClk 256 × TClk µs C 4.9 Equivalent acknowledge pulse: E_Ack t8 261 261 128 × TClk 128 × TClk µs A

4.10 Equivalent

time window t9 526 526 258 × TClk 258 × TClk µs A 4.11 OFF-bit programming window t10 916 916 449.5 × T Clk 449.5 × TClk µs A

5 Data Clock (see Figure 9-1 and Figure 9-6)

5.1 Minimum delay time between edge at DATA and DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t Delay2 16.3057 8.1528 4.0764 2.0382 1 × T XClk 1 × TXClk 1 × TXClk 1 × TXClk µs µs µs µs C 5.2 Pulse width of negative pulse at pin DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t P_DATA_CLK 65.2 32.6 16.3 8.15 65.2 32.6 16.3 8.15 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk µs µs µs µs A 17. Electrical Characterist ics ATA5723 (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315 MHz unless otherwise specified (For typical values: VS =5 V , Tamb = 25°C). No. Parameter Test Conditions Symbol fRF = 315 MHz *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 18. Electrical Characteri stics ATA5724, ATA5728 All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 868.3 MHz unless otherwise specified (For typical values: VS =5 V , Tamb = 25°C). No. Parameter Test Conditions Symbol fRF = 433.92 MHz

13.52875 MHz Oscillator

fRF = 868.3 MHz,

13.55234 MHz Oscillator Variable Oscillator

6 Basic Clock Cycle of the Digital Circuitry

6.1 Basic clock

cycle TClk 2.0696 2.0696 2.066 2.066 28/f XTO 28/fXTO µs A 6.2 Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 T XClk 16.557 8.278 4.139 2.069 16.557 8.278 4.139 2.069 16.528 8.264 4.132 2.066 16.528 8.264 4.132 2.066 8 × T Clk 4 × TClk 2 × TClk 1 × TClk 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs A

7 Polling Mode

7.1 Sleep time (see Figure 8-1, Figure 8-10 and Figure 13-1) Sleep and XSleep are defined in the OPMODE register T Sleep Sleep × XSleep × 1024 × 2.0696 Sleep × XSleep × 1024 × 2.0696 Sleep × XSleep × 1024 × 2.066 Sleep × XSleep × 1024 × 2.066 Sleep × XSleep × 1024 × TClk Sleep × XSleep × 1024 × TClk ms A 7.2 Start-up time (see Figure 8-1 and Figure 8-4) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Startup 1855 1060 1060 663 1855 1060 1060 663 1852 1058 1058 662 1852 1058 1058 662 896.5 512.5 512.5 320.5 × T Clk 896.5 512.5 512.5 320.5 × T Clk µs µs µs µs µs A 7.3 Time for bit check (see Figure 8-1 Average bit-check time while polling, no RF applied (see Figure 8-8 on page 16 and Figure 8-9 on page 17) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Bit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms C 7.4 Time for bit check (see Figure 8-1 Bit-check time for a valid input signal f Sig (see Figure 8-5 on page 15) N Bit-check = 0 NBit-check = 3 NBit-check = 6 NBit-check = 9 TBit-check 1 × TXClk 3/fSig 6/fSig 9/fSig 1 × TXClk 3.5/fSig 6.5/fSig 9.5/fSig 1 × TXClk 3/fSig 6/fSig 9/fSig 1 × TXClk 3.5/fSig 6.5/fSig 9.5/fSig 1 × TXClk 3/fSig 6/fSig 9/fSig 1 × TClk 3.5/fSig 6.5/fSig 9.5/fSig ms ms ms ms C

8 Receiving Mode

8.1 Intermediate

IF 987 947.9 fIF = fLO/438 for the 433.92 MHz band (ATA5724) fIF = fLO/915 for the 868.3 MHz band (ATA5728) kHz A

8.2 Baud-rate

BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 BR_Range0 × 2 µs/T Clk BR_Range1 × 2 µs/TClk BR_Range2 × 2 µs/TClk BR_Range3 × 2 µs/TClk kBit/s kBit/s kBit/s kBit/s A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 8.3 Minimum time period between edges at pin DATA (see Figure 4-2 and Figure 8-8, Figure 8-9) (With the exception of parameter T Pulse) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t DATA_min 165.5 82.8 41.4 20.7 165.5 82.8 41.4 20.7 165.3 82.6 41.3 20.6 165.3 82.6 41.3 20.6 10 × T XClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk 10 × TXClk µs µs µs µs A 8.4 Maximum Low period at pin DATA (see Figure 4-2) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t DATA_L_max 2152 1076 538 269 2152 1076 538 269 2148 1074 537 268.5 2148 1074 537 268.5 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk 130 × TXClk µs µs µs µs A 8.5 Delay to activate the start-up mode (see Figure 8-12) Clk 10.5 × TClk µs A 8.6 OFF command at pin POLLING/ _ON (see Figure 8-11) Ton2 16.5 16.5 8 × T Clk µs A 8.7 Delay to activate the sleep mode (see Figure 8-11) Clk 9.5 × TClk µs A 8.8 Pulse on pin DATA at the end of a data stream (see Figure 10-3) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Pulse 16.557 8.278 4.139 2.069 16.557 8.278 4.139 2.069 16.528 8.264 4.132 2.066 16.528 8.264 4.132 2.066 8 × T Clk 4 × TClk 2 × TClk 1 × TClk 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs C 18. Electrical Characteristics ATA5724, ATA5728 (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 868.3 MHz unless otherwise specified (For typical values: VS =5 V , Tamb = 25°C). No. Parameter Test Conditions Symbol fRF = 433.92 MHz fRF = 868.3 MHz, *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728

9 Configuration of the Receiver (see Figure 12-1 and Figure 13-1)

9.1 Frequency of the reset marker Frequency is stable within 50 ms after POR f RM 117.9 117.9 118.2 118.2 (4096 × TClk) (4096 × TClk) Hz A

9.2 Programming

BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR 3361 2276 1734 1463 16425 11656 11656 11656 11656 3355 2272 1731 1460 11636 11636 11636 11636 1624 × T Clk 1100 × TClk 838 × TClk 707 × TClk 7936 × TClk 5632 × TClk 5632 × TClk 5632 × TClk 5632 × TClk µs µs µs µs µs A

9.3 Programming

delay period t2 796 798 794 796 384.5 × T Clk 385.5 × TClk µs A

9.4 Synchroniza-

tion pulse t3 265 265 264 264 128 × TClk 128 × TClk µs A 9.5 Delay until of the program window starts t4 131 131 131 131 63.5 × TClk 63.5 × TClk µs A

9.6 Programming

window t5 530 530 529 529 256 × TClk 256 × TClk µs A

9.7 Time frame

of a bit t6 1060 1060 1058 1058 512 × TClk 512 × TClk µs A

9.8 Programming

pulse t7 132 530 132 529 64 × TClk 256 × TClk µs C 9.9 Equivalent acknowledge pulse: E_Ack t8 265 265 264 264 128 × TClk 128 × TClk µs A

9.10 Equivalent

time window t9 534 534 533 533 258 × TClk 258 × TClk µs A 9.11 OFF-bit programming window t10 930 930 929 929 449.5 × TClk 449.5 × TClk µs A

10 Data Clock (see Figure 9-1 and Figure 9-6)

10.1 Minimum delay time between edge at DATA and DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t Delay2 16.557 8.278 4.139 2.069 16.528 8.264 4.132 2.066 1 × T XClk 1 × TXClk 1 × TXClk 1 × TXClk µs µs µs µs C 10.2 Pulse width of negative pulse at pin DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t P_DATA_CLK 66.2 33.1 16.5 8.3 62.2 33.1 16.5 8.3 66.1 33.0 16.5 8.25 66.1 33.0 16.5 8.25 4 × T XClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk 4 × TXClk µs µs µs µs A 18. Electrical Characteristics ATA5724, ATA5728 (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 868.3 MHz unless otherwise specified (For typical values: VS =5 V , Tamb = 25°C). No. Parameter Test Conditions Symbol fRF = 433.92 MHz fRF = 868.3 MHz, *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 19. Electrical Characteristic s ATA5723, ATA5724, ATA5728 All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3 MHz, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type*

11 Current Consumption

11.1 Current consumption

(XTO and polling logic active) ISoff 170 290 µA A IC active (start-up-, bit-check-, receiving mode) Pin DATA = H FSK ASK ISon 8.5 8.0 11.0 10.4 mA mA A 12 LNA, Mixer, Polyphase Low-pass and IF Amplifier (Input Matched According to Figure 14-1 on page 32 Referred to RFIN)

12.1 Third-order intercept point

868 MHz

433 MHz

315 MHz

IIP3 –18 –23 –24 dBm C

12.2 LO spurious emission Required according to I-ETS 300220 IS

LORF –70 –57 dBm A

12.3 System noise figure With power matching |S11| < –10 dB NF 5 dB B

12.4 LNA_IN input impedance

At 868.3 MHz AT 433.92 MHz At 315 MHz ZiLNA_IN (14.15 – j73.53) (19.3 – j113.3) (26.97 – j158.7) Ω Ω Ω C 12.5 1 dB compression point At 868.3 MHz AT 433.92 MHz At 315 MHz IP1db –27.7 –32.7 –33.7 dBm C

12.6 Image rejection Within the complete image band 20 30 dB A

12.7 Maximum input level

BER ≤ 10 -3, FSK mode ASK mode Pin_max –10 –10 dBm dBm C

13 Local Oscillator

13.1 Operating frequency range

431.5 312.5 870 436.5 317.5 MHz MHz MHz A

13.2 Phase noise local oscillator

fosc = 868.3 MHz at 10 MHz fosc = 433.92 MHz at 10 MHz fosc = 315 MHz at 10 MHz L (fm) –140 –143 –143 –130 –133 –133 dBC/Hz B

13.3 Spurious of the VCO At ±f XTO –55 –45 dBC B

13.4 XTO pulling

XTO pulling, appropriate load capacitance must be connected to XTAL, crystal CL1 and CL2 f XTAL = 14.71875 MHz (315 MHz band) fXTAL = 13.52875 MHz (433 MHz band) f XTAL = 13.55234 MHz (868 MHz band) fXTO –10ppm f XTAL +10ppm MHz B

13.5 Series resonance resistor of

the crystal Parameter of the supplied crystal R S 120 Ω B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728

13.6 Static capacitance at pin

Parameter of the supplied crystal and board parasitics CL1 –5% 18 +5% pF B

13.7 Static capacitance at pin

Parameter of the supplied crystal and board parasitics CL2 –5% 18 +5% pF B

13.8 Crystal series resistor Rm at

C0 < 1.8 pF, CL =9p F fXTAL = 14.71875 MHz 1.5 k Ω B C0 < 2.0 pF, CL =9p F fXTAL = 13.52875 MHz fXTAL = 13.55234 MHz 1.5 k Ω B

14 Analog Signal Pr ocessing (Input Matched According to Figure 14-1 on page 32 Referred to RFIN)

14.1 Input sensitivity ASK 300 kHz IF Filter (ATA5723/ATA5724) ASK (level of carrier) BER ≤ 10 -3, 100% Mod fin = 315 MHz/433.92 MHz VS = 5V, Tamb = 25°C fIF = 987 kHz PRef_ASK BR_Range0 –111 –113 –115 dBm B BR_Range1 –109.5 –111.5 –113.5 dBm B BR_Range2 –109 –111 –113 dBm B BR_Range3 –107 –109 –111 dBm B 14.2 Input sensitivity ASK 600 kHz IF Filter (ATA5728) ASK (level of carrier) BER ≤ 10 -3, 100% Mod fin = 868.3 MHz VS = 5V, Tamb = 25°C fIF = 948 kHz PRef_ASK BR_Range0 –109 –111 –113 dBm B BR_Range1 –107.5 –109.5 –111.5 dBm B BR_Range2 –107 –109 –111 dBm B BR_Range3 –105 –107 –109 dBm B 14.3 Sensitivity variation ASK for the full operating range compared to Tamb =2 5 ° C , VS =5 V (ATA5723/ATA5724/ATA5728) 300 kHz and 600 kHz fin = 315 MHz/433.92 MHz/868.3 MHz PASK = PRef_ASK + ΔPRef ΔPRef +2.5 –1.5 dB B 14.4 Sensitivity variation ASK for full operating range including IF filter compared to Tamb =2 5 ° C , VS = 5V 300 kHz version (ATA5723/ATA5724) fin = 315 MHz/433.92 MHz fIF = 987 kHz fIF = –110 kHz to +110 kHz fIF = –140 kHz to +140 kHz PASK = PRef_ASK + ΔPRef ΔPRef +5.5 +7.5 –1.5 –1.5 dB dB B 600 kHz version (ATA5728) fin = 868.3 MHz fIF = 948 kHz fIF = –210 kHz to +210 kHz fIF = –270 kHz to +270 kHz PASK = PRef_ASK + ΔPRef ΔPRef +5.5 +7.5 –1.5 –1.5 dB dB B 19. Electrical Characteristics ATA5723, ATA5724, ATA5728 (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3 MHz, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 14.5 Input sensitivity FSK 300 kHz IF filter (ATA5723/ATA5724) BER ≤ 10 -3 fin = 315 MHz/433.92 MHz VS = 5V, Tamb = 25°C fIF = 987 kHz BR_Range0 df = ±16 kHz df = ±10 kHz to ±30 kHz PRef_FSK –104 –102 –107 –108.5 –108.5 dBm dBm B BR_Range1 df = ±16 kHz df = ±10 kHz to ±30 kHz PRef_FSK –102 –100 –105 –106.5 –106.5 dBm dBm B BR_Range2 df = ±16 kHz df = ±10 kHz to ±30 kHz PRef_FSK –100.5 –98.5 –103.5 –105 –105 dBm dBm B BR_Range3 df = ±16 kHz df = ±10 kHz to ±30 kHz PRef_FSK –98.5 –96.5 –101.5 –103 –103 dBm dBm B 14.6 Input sensitivity FSK 600 kHz IF filter (ATA5728) BER ≤ 10 -3 fin = 868.3 MHz VS = 5V, Tamb = 25°C fIF = 948 kHz BR_Range0 df = ±16 kHz to ±28 kHz df = ±10 kHz to ±100 kHz PRef_FSK –102 –100 –105 –106.5 –106.5 dBm dBm B BR_Range1 df = ±16 kHz ±28 kHz df = ±10 kHz to ±100 kHz P Ref_FSK –100 –98 –103 –104.5 –104.5 dBm dBm B BR_Range2 df = ±18 kHz ±31 kHz df = ±13 kHz to ±100 kHz P Ref_FSK –98.5 –96.5 –101.5 –103 –103 dBm dBm B BR_Range3 df = ±25 kHz ±44 kHz df = ±20 kHz to ±100 kHz P Ref_FSK –96.5 –94.5 –99.5 –101 –101 dBm dBm B 14.7 Sensitivity variation FSK for the full operating range compared to T amb =2 5 ° C , VS = (ATA5723/ATA5724/ATA5728) 300 kHz and 600 kHz versions fin = 315 MHz/433.92 MHz/868.3 MHz PFSK = PRef_FSK + ΔPRef ΔPRef +3 –1.5 dB B 19. Electrical Characteristics ATA5723, ATA5724, ATA5728 (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3 MHz, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 14.8 Sensitivity variation FSK for the full operating range including IF filter compared to T amb = 25°C, VS = 5V 300 kHz version (ATA5723/ATA5724) fin = 315 MHz/433.92 MHz fIF = 987 kHz fIF = –110 kHz to +110 kHz fIF = –140 kHz to +140 kHz fIF = –180 kHz to +180 kHz PFSK = PRef_FSK + ΔPRef ΔPRef +11 dB dB dB B 600 kHz version (ATA5728) fin = 868.3 MHz fIF = 948 kHz fIF = –150 kHz to +150 kHz fIF = –200 kHz to +200 kHz fIF = –260 kHz to +150 kHz PFSK = PRef_FSK + ΔPRef ΔPRef +11 dB dB dB B 14.9 S/N ratio to suppress in-band noise signals. Noise signals may have any modulation scheme ASK mode FSK mode SNR ASK SNRFSK dB dB C

14.10 Dynamic range RSSI amplifier ΔRRSSI 60 dB A

14.11 RSSI output voltage range V RSSI 13 . 5 V A

14.12 RSSI gain G RSSI 20 mV/dB A

14.13 Lower cut-off frequency of the

CDEM = 33 nF fcu_DF 0.11 0.16 0.20 kHz B

14.14 Recommended CDEM for best

BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 CDEM 8.2 nF nF nF nF C 14.15 Edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 t ee_sig 270 156 1000 560 320 180 ms ms ms ms C

14.16 Upper cut-off frequency data

BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 fu 2.8 4.8 8.0 15.0 3.4 6.0 10.0 19.0 4.0 7.2 12.0 23.0 kHz kHz kHz kHz B

14.17 Reduced sensitivity

300 kHz version (ATA5723/ATA5724) R Sense connected from pin SENS to VS, input matched according to Figure 14-1 “Application Circuit, fin = 315 MHz/433.92 MHz, VS = 5V, Tamb = +25°C dBm (peak level) RSense = 56 kΩ PRef_Red –74 –79 –83 dBm B RSense = 100 kΩ PRef_Red –83 –88 –93 dBm B 19. Electrical Characteristics ATA5723, ATA5724, ATA5728 (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3 MHz, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter fcu_DF

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728

14.18 Reduced sensitivity

600 kHz version (ATA5728) RSense connected from pin SENS to VS, input matched according to Figure 14-1 “Application Circuit, fin =8 6 8 . 3M H z , VS = 5V, Tamb = +25°C dBm (peak level) RSense = 56 kΩ PRef_Red –63 –68 –73 dBm B RSense = 100 kΩ PRef_Red –72 –77 –82 dBm B

14.19 Reduced sensitivity variation

RSense = 56 kΩ RSense = 100 kΩ PRed = PRef_Red + ΔPRed ΔPRed dB dB C

14.20 Reduced sensitivity variation

for different values of RSense Values relative to RSense = 56 kΩ RSense = 56 kΩ RSense = 68 kΩ RSense = 82 kΩ RSense = 100 kΩ ΔPRed –3.5 –6.0 –9.0 dB dB dB dB C

14.21 Threshold voltage for reset V

ThRESET 1.95 2.8 3.75 V A

15 Digital Ports

15.1 Data output - Saturation voltage Low - max voltage at pin DATA - quiescent current - short-circuit current - ambient temp. in case of permanent short-circuit Data input - Input voltage Low - Input voltage High I ol ≤ 12 mA Iol = 2 mA Voh = 20V Vol = 0.8V to 20V Voh = 0V to 20V Vol Vol Voh Iqu Iol_lim tamb_sc VIl Vich 0.65 × VS 0.35 0.08 0.8 0.3 0.35 × VS V V V µA mA V V A 15.2 DATA_CLK output - Saturation voltage Low - Saturation voltage High IDATA_CLK = 1mA IDATA_CLK = –1mA V ol Voh VS – 0.4V 0.1 VS – 0.15V 0.4 V V A 15.3 IC_ACTIVE output - Saturation voltage Low - Saturation voltage High IIC_ACTIVE = 1 mA IIC_ACTIVE = –1 mA Vol Voh VS – 0.4 V 0.1 VS – 0.15V 0.4 V V A 15.4 POLLING/_ON input - Low level input voltage - High level input voltage Receiving mode Polling mode V Il VIh 0.8 × VS 0.2 × VS V V A

15.5 MODE pin

• High level input voltage Test input must always be set to High VIh 0.8 × VS V A

15.6 TEST 1 pin

• Low level input voltage Test input must always be set to Low VIl 0.2 × VS V A 19. Electrical Characteristics ATA5723, ATA5724, ATA5728 (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3 MHz, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C) No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

9106E–RKE–07/08 ATA5723/ATA5724/ATA5728 21. Package Information 20. Ordering Information Extended Type Number Package Remarks ATA5723P3-TKQY SSO20 315 MHz version ATA5724P3-TKQY SSO20 433 MHz version ATA5728P6-TKQY SSO20 868 MHz version Dimensions in mm specifications according to DIN technical drawings 6.75-0.25 1120 101 Issue: 1; 10.03.04 Drawing-No.: 6.543-5056.01-4 5.85±0.05 1.3±0.05 0.15 ±0.05 0.65±0.05 5.4±0.2 4.4±0.1 6.45±0.150.25±0.05 0.05+0.1

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