ATA3745

ATA3745 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Supply Voltage 4.5V to 5.5V  Operating Temperature Range –40°C to +85°C  Minimal External Circuitry Requirements, No RF Components on the PC Board Except Matching to the Receiver Antenna  High Sensitivity, Especially at Low Data Rates  Sensitivity Reduction Possible Even While Receiving  Fully Integrated VCO  Low Power Consumption Due to Configurable Self-polling with a Programmable Time Frame Check  Single-ended RF Input for Easy Matching to λ / 4 Antenna or Printed Antenna on PCB  Low-cost Solution Due to High Integration Level  ESD Protection According to MIL-STD 883 (4 KV HBM) Except Pin POUT (2 KV HBM)  High Image Frequency Suppression Due to 1 MHz IF in Conjunction With a SAW Front-end Filter. Up to 40 dB is Thereby Achievable With Newer SAWs  Programmable Output Port for Sensitivity Selection or for Controlling External Periphery  Communication to the Microcontroller Possible via a Single, Bi-directional Data Line  Power Management (Polling) is also Possible by Means of a Separate Pin via the Microcontroller 1. Description The ATA3745 is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with low data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well-suited to operate with At mel’s PLL RF transmitter ATA2745. It can be used in the frequency receiving range of f0 = 310 MHz to 440 MHz for ASK data trans- mission. All the statements made below refer to 433.92 MHz and 315 MHz applications. The main applications of the ATA3745 are in the areas of outside temperature meter- ing, socket control, garage door openers, consumption metering, light/fan or air-conditioning control, jalousies, wire less keyboards, and various other consumer market applications. UHF ASK/FSK Receiver ATA3745 Rev. 4901A–RKE–11/05

4901A–RKE–11/05 ATA3745 Figure 1-1. System Block Diagram Figure 1-2. Block Diagram Demod Data Interf. ATA3745 1...3 ATA2745 Antenna Antenna UHF ASK/FSK Remote control transmitter UHF ASK/FSK Remote control receiver

1 Li cell

µC PLL XTO VCOLNA PLL VCOXTO Encoder ATARx9x Power amp. IF Amp. Demodulator and data filter IF Amp IF Amp 4th Order LPF

3 MHz

DEMOD_OUT Limiter outRSSI Sensitivity reduction Standby logic Polling circuit and control logic FE CLK VCO XTO ÷ 64 f 50 kΩ VS ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN DATA TEST POUT MODE LFGND LFVCC XTO LF DVCC LNA

4901A–RKE–11/05 ATA3745 2. Pin Configuration Figure 2-1. Pinning SO20 NC ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN NC DATA ENABLE TEST POUT MODE DVCC XTO LFGND LF LFVCC Table 2-1. Pin Description Pin Symbol Function

1 NC Not connected

2 ASK ASK high

3 CDEM Lower cut-off frequency data filter

4 AVCC Analog power supply

5 AGND Analog ground

6 DGND Digital ground

7 MIXVCC Power supply mixer

8 LNAGND High-frequency ground LNA and mixer

9 LNA_IN RF input

10 NC Not connected

11 LFVCC Power supply VCO

12 LF Loop filter

13 LFGND Ground VCO

14 XTO Crystal oscillator

15 DVCC Digital power supply

16 MODE Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA), High: 6.76438 MHz (Europe)

17 POUT Programmable output port

18 TEST Test pin, during operation at GND

19 ENABLE Enables the polling mode. Low: polling mode off (sleep mode). High: polling mode on (active mode)

20 DATA Data output/configuration input

4901A–RKE–11/05 ATA3745 3. RF Front End The RF front end of the receiver is a heterodyne co nfiguration that converts the input signal into a 1-MHz IF signal. As shown in the block diagram, the front end consists of an LNA (low noise amplifier), LO (local oscillator), a mixer and an RF amplifier. The LO generates the carrier frequency for the mixe r via a PLL synthesize r. The XTO (crystal oscillator) generates the reference frequency f XTO. The VCO (voltage-controlled oscillator) gen- erates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin LF. fLO is divided by a factor of 64. The divided frequency is compared to f XTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage V LF for the VCO. By means of that configuration, V LF is controlled such that f LO / 64 is equal to f XTO. If fLO is determined, fXTO can be calculated using the following formula: The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. Fig- ure 3-1shows the proper layout, with the crystal connected to GND via a capacitor CL. The value of that capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of f XTO and thereby of f LO. When designing the system in terms of receiving bandwidth, the accuracy of the crystal and XTO must be considered. Figure 3-1. PLL Peripherals The passive loop filter connected to pin LF is designed for a loop bandwidth of B Loop = 100 kHz. This value for B Loop exhibits the best possible noise performance of the LO. Figure 3-1 shows the appropriate loop filter components to achieve the desired loop bandwidth. If the filter compo- nents are changed for any reason, please note that the maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit check may no longe r be possible since f LO can- not settle in time before the bit check starts to evaluate the incoming data stream. Therefore, self polling also does not work in that case. f LO is determined by the RF input frequency f RF and the IF frequency f IF using the following for- mula: fXTO fLO DVCC XTO LF LFVCC LFGND CL C10R1 VS R1 = 820 Ω C9 = 4.7 nF C10 = 1 nF VS fLO fRF fIF–=

4901A–RKE–11/05 ATA3745 To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter’s corner frequencies, the filter is tuned by the crystal frequency f XTO. This means that there is a fixed relation between f IF and fLO that depends on the logic level at pin MODE. This is described by the following formulas: The relation is designed to achi eve the nominal IF frequency of f IF = 1 MHz for most applica- tions. For applications where f RF = 315 MHz, the MODE must be set to “0”. In the case of fRF = 433.92 MHz, the MODE must be set to “1”. For other RF frequencies, f IF is not equal to 1 MHz. fIF is then dependent on the logical level at pin MODE and on fRF. Table 3-1 summarizes the different conditions. The RF input either from an antenna or from a generator must be transformed to the RF input pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The para- sitic board inductances and capacitances also influence the input matching. The RF receiver ATA3745 exhibits its highest sensitivity at t he best signal-to-noise ratio (SNR) in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network, a mirror frequency suppression of ∆PRef = 40 dB can be achieved. There are SAWs ava ilable that exhibit a notch at ∆f = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used. Figure 3-2 on page 6 shows a typical input matching network for f RF = 315 MHz and fRF = 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates an input matching to 50 Ω with- out a SAW. The input matching networks shown in Figure 3-3 on page 6 are the reference networks for the parameters given in the section “Electrical Characteristics” on page 23. Table 3-1. Calculation of LO and IF Frequency Conditions Local Oscillator Fr equency Intermediate Frequency fRF = 315 MHz, MODE = 0 f LO = 314 MHz f IF = 1 MHz fRF = 433.92 MHz, MODE = 1 f LO = 432.92 MHz f IF = 1 MHz

300 MHz < fRF < 365 MHz, MODE = 0

365 MHz < fRF < 450 MHz, MODE = 1

MODE 0 (USA) f IF fLO MODE 1 (Europe) f IF fLO fLO fRF 1 1 fIF fLO fLO fRF 1 1 fIF fLO

4901A–RKE–11/05 ATA3745 4. Analog Signal Processing

4.1 IF Amplifier

The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or fRF = 433.92 MHz is used. For other RF input frequencies, refer to Table 3-1 on page 5 to determine the center frequency. The receiver ATA3745 employs an IF bandwidth of B IF = 600 kHz. This IC can be used together with the ATA2745. SAW transmitters exhibit much higher transmit frequency tolerances com- pared to PLL transmitters. Generally, it is necessary to use B IF = 600 kHz together with such transmitters.

4.2 RSSI Amplifier

The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is ∆RRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best signal-to-noise ratio (SNR) is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the SNR is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity. Since different RF input networks may exhibit slig htly different values for the LNA gain, the sen- sitivity values given in the electrical characteri stics refer to a specific input matching. This matching is illustrated in Figure 3-3 on page 6 and exhibits the best possible sensitivity.

4.3 Demodulator and Data Filter

The signal coming from the RSSI amplifier is conver ted into the raw data signal by the ASK demodulator. In ASK mode, an automatic threshold control (ATC) circuit is employed to set the detection refer- ence voltage to a value where a good SNR is achieved. This circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. If the SNR exceeds 10 dB, the data signal can be detected properly. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the SNR as its band-pass can be adapted to the characteristics of the data signal. The data filter consists of a 1st-order high-pass and a 1st-order low-pass filter. The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following formula: In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high val ues if self polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the section “Electrical Characteristics” on page 23. fcu_DF

4901A–RKE–11/05 ATA3745 The cut-off frequency of the low-pass filter is defined by the selected baud rate range (BR_Range). BR_Range is defined in the OPMODE register (refer to “Configuration of the Receiver” on page 18). BR_Range must be set in accordance to the used baud rate. The ATA3745 is designed to operate with data encoding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-pha se encoding. If other modulation schemes are used, the DC level should always remain within the range of V DC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (t ee_sig ). These limits are defined in the section “Electrical Characteristics” on page 23. They should not be exceeded to maintain full sensitivity of the receiver.

4.4 Receiving Characteristics

The RF receiver ATA3745 can be operated with and without a SAW front end filter. The selectiv- ity with and without a SAW fron t-end filter is illustrated in Figure 4-1 . This example relates to ASK mode of the ATA3745. Note th at the mirror frequency is redu ced by 40 dB. The plots are printed relative to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered. When designing the system in te rms of receiving bandwidth, the LO deviation must be consid- ered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the ATA3745. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the ATA3745 is an additional deviation due to the XTO circuit. This deviation is specified to be ±50 ppm. If a crystal of ±100 ppm is used, the total deviation is ±150 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode. Figure 4-1. Receiving Frequency Response -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 df (MHz) dP (dB) without SAW with SAW

4901A–RKE–11/05 ATA3745 5. Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor- responding transmitter. This is ac hieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time , the bit check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected does the receiver remain active and transfer the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time, resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, sys- tem response time, data rate, etc. Regarding the number of connection wires to the mic rocontroller, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected microcontrol- ler, or it can be operated by up to three uni-directional ports.

5.1 Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry and the analog filtering is derived from one clock. Fig- ure 5-1 shows how this clock cycle T Clk is derived from the cr ystal oscillator (XTO) in combination with a divider. The division factor is controlled by the logical state at pin MODE. As described in “RF Front End” on page 4, the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO). Figure 5-1. Generation of the Basic Clock Cycle Pin MODE can now be set in accordance with the desired clock cycle T Clk. TClk controls the fol- lowing application-relevant parameters:  Timing of the polling circuit including bit check  Timing of analog and digital signal processing  Timing of register programming  Frequency of the reset marker  IF filter center frequency (f IF0) DVCC XTO MODE TClk fXTO 14XTO Divider H: Europe (:14)

4901A–RKE–11/05 ATA3745 Most applications are dominated by two transmission frequencies: f Send = 315 MHz is mainly used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent parameters, the electrical characteristics display three conditions for each parameter.  USA applications (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)  European applications (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)  Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined in the OPMODE register. This clock cycle T XClk is defined by the following for- mulas for further reference:

5.2 Polling Mode

According to Figure 3-2 on page 6 , the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period TSleep while consuming low current of I S = ISoff. During the start-up period, T Startup, all sig- nal processing circuits are enabled and settled. In the following bit check mode, the incoming data stream is analyzed bit by bit looking for a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period TBitcheck. This period varies check by check as it is a statistical process. An average value for T Bitcheck is given in the section “Elec- trical Characteristics” on page 23 . During T Startup and T Bitcheck the current consumption is IS = ISon. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitt er must start the telegram with an adequate preburst. The required length of the preburst is dependent on the polling parameters TSleep, TStar- tup, TBitcheck and the startup time of a connected microcontroller (T Start_µC). TBitcheck thus depends on the actual bit rate and the number of bits (NBitcheck) to be tested. The following formula indicates how to calculate the preburst length. TPreburst ≥ TSleep + TStartup + TBitcheck + TStart_µC BR_Range = BR_Range0: T XClk = 8 × TClk BR_Range1: T XClk = 4 × TClk BR_Range2: T XClk = 2 × TClk BR_Range3: T XClk = 1 × TClk ISpoll ISoff TSleep ISon TStartup TBitcheck+()×+×

4901A–RKE–11/05 ATA3745

5.2.1 Sleep Mode

The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the exten- sion factor X Sleep described in Table 5-8 on page 20 , and the basic clock cycle T Clk . It is calculated to be: In US and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting X Sleep to 8. XSleep can be set to 8 by bit XSleepStd or by bit XSleepTemp, resulting in a different mode of action as described below: XSleepStd = 1 implies the standard extension factor. The sleep time is always extended. XSleepTemp = 1 implies the temporary extension factor. The extended sleep time is used as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 automatically, result- ing in a regular sleep time. This functionality can be used to save current in presence of a modulated disturber similar to an expected trans mitter signal. The connected microcontroller is rarely activated in that condition. If the disturbe r disappears, the receiver switches back to regu- lar polling and is again sensitive to appropriate transmitter signals. Table 5-6 on page 19 shows how the highest register value of Sleep sets the receiver to a per- manent sleep condition. The rece iver remains in that conditi on until another value for Sleep is programmed into the OPMODE register. This func tion is desirable where several devices share a single data line. TSleep Sleep X Sleep× 1024× TClk×=

4901A–RKE–11/05 ATA3745

5.3 Bit Check Mode

In bit check mode, the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a pro- grammable time window. The maximum count of this edge-to-edge test, before the receiver switches to receiving mode, is also programmable.

5.3.1 Configuring the Bit Check

Assuming a modulation scheme that contains 2 ed ges per bit, two time frame checks verify one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N Bitcheck in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If N Bitcheck is set to a higher value, the receiver is less likely to switch to the receiving mode due to noise. In the pres- ence of a valid transmitter signal, the bit check takes less time if N Bitcheck is set to a lower value. In polling mode, the bit check time is not dependent on NBitcheck. Figure 5-3 on page 12 shows an example where 3 bits are tested successfully and the data signal is transferred to pin DATA. Figure 5-4 shows that the time window for the bit check is defined by two separate time limits. If the edge-to-edge time tee is in between the lower bit check limit T Lim_min and the upper bit check limit TLim_max, the check will be continued. If t ee is smaller than T Lim_min or tee exceeds T Lim_max, the bit check will be terminated and the receiver switches to sleep mode. Figure 5-4. Valid Time Window for Bit Check For best noise immunity it is recommended to use a low span between T Lim_min and T Lim_max . This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A good compromise betw een receiver sensitivity and susceptib ility to noise is a time window of ±25% regarding the expected edge-to-edge time t ee. Using preburst patterns that contain vari- ous edge-to-edge time periods, the bit check limits must be programmed according to the required span. The bit check limits are determined by means of the formulas below: TLim_min = Lim_min × TXClk TLim_max = (Lim_max – 1) × TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using the above formulas, Lim_min and Lim_ma x can be determined according to the required TLim_min, TLim_max and TXClk. The time resolution when defining T Lim_min and TLim_max is TXClk. The minimum edge-to-edge time t ee (tDATA_L_min, tDATA_H_min) is defined in Section “Receiving Mode” on page 15. Due to this, the lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63. Dem_out tee TLim_max 1/fSig TLim_min

4901A–RKE–11/05 ATA3745

5.3.2 Duration of the Bit Check

If no transmitter signal is present during the bit check, the output of the demodulator delivers random signals. The bit check is a statistical process and T Bitcheck varies for each check. There- fore, an average value for TBitcheck is given in the section “Electrical Characteristics” on page 23. TBitcheck depends on the selected baud rate range and on T Clk. A higher baud rate range causes a lower value for TBitcheck resulting in lower current consumption in polling mode. In the presence of a valid transmitter signal, T Bitcheck is dependant on the frequency of that sig- nal, fSig and the count of the checked bits, N Bitcheck. A higher value for N Bitcheck thereby results in a longer period for TBitcheck requiring a higher value for the transmitter preburst TPreburst.

5.4 Receiving Mode

If the bit check has been successful for all bits specified by N Bitcheck , the receiver switches to receiving mode. As seen in Figure 5-4 on page 13 , the internal data signal is switched to pin DATA in that case. A connected microcontrol ler can be woken up by the negative edge at pin DATA. The receiver stays in that condition until it is switched back to polling mode explicitly.

5.4.1 Digital Signal Processing

The data from the demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This proc essing depends on the selected baud rate range (BR_Range). Figure 5-8 illustrates how Dem_out is sync hronized by the extended clock cycle TXClk. This clock is also used for the bit check counter. Data can change its state only after T XClk elapsed. The edge-to-edge time period t ee of the Data signal, as a result, is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to t ee ≥ TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time, it limits the max- imum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. T DATA_min is to some extent affected by the preceding edge-to-edge time interval tee as illustrated in Figure 5-9 on page 16 . If tee is in between the specified bit check limits, the following level is frozen for the time period T DATA_min = tmin1; if tee is outside the bit check limits, TDATA_min = tmin2 is the relevant stable time period. The maximum time period for DATA to be low is limited to T DATA_L_max. This function ensures a finite response time during programming or switching off the receiver via pin DATA. T DATA_L_max is thereby longer than the maximum time period indicated by the transmitter data stream. Figure 5-10 on page 16 gives an example where Dem_out remains low after the receiver has switched to receiving mode. Figure 5-8. Synchronization of the Demodulator Output Clock bit check counter DATA Dem_out TXClk tee

4901A–RKE–11/05 ATA3745 Figure 5-9. Debouncing of the Demodulator Output Figure 5-10. Steady L State Limited DATA Output Pattern after Transmission After the end of a data transmission, the rece iver remains active and random noise pulses appear at pin DATA. The edge-to-edge time period t ee of the majority of these noise pulses is equal to or slightly higher than TDATA_min.

5.4.2 Switching the Receiver Back to Sleep Mode

The receiver can be set back to polling mode via pin DATA or via pin ENABLE. When using pin DATA, this pin must be pulled to low for the period t1 by the connected micro- controller. Figure 5-11 on page 17 illustrates the timing of the OFF command (see also Figure 5-15 on page 22). The minimum value of t1 depends on the BR_Range. The maximum value for t1 is not limited, but it is recommended not to exceed the specified value to prevent erasing the reset marker. This item is explained in more detail in “Configuration of the Receiver” on page 18. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 of the OPMODE register to “1”. Only one synchronous pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF command, the sleep time T Sleep elapses. Note that the capacitive load at pin DATA is limited. The resulting time constant t together with an optional external pull-up resistor should not be exceeded, to ensure proper operation. If the receiver is set to polling mode via pin ENABLE, an "L" pulse (TDoze) must be issued at that pin. Figure 5-12 on page 17 illustrates the timing of that command. After the positive edge of this pulse, the sleep time TSleep elapses. The receiver remains in sleep mode as long as ENABLE is held to "L". If the receiver is polled exclusively by a microcontroller, TSleep can be programmed to “0” to enable an instantaneous response time. This command is the faster option than via pin DATA, at the cost of an additional connection to the microcontroller. DATA tmin1Lim_min ≤ CV_Lim < Lim_max Dem_out tee tmin2 tee CV_Lim < Lim_min or CV_Lim ≥ Lim_max Bit check Enable IC DATA Sleep mode Receiving mode tmin2Bit check mode tDATA_L_max Dem_out

4901A–RKE–11/05 ATA3745

5.5 Configuration of the Receiver

The ATA3745 receiver is configured via two 12 -bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register con- tents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 5-2 shows the structure of the registers. Table 5-1 shows the effect of bit 1 and bit 2 in pro- gramming the registers: bit 1 defines if the receiver is set back to polling mode via the OFF command (see “Receiving Mode” on page 15), or if it is programmed. Bit 2 represents the regis- ter address. It selects the appropriate register to be programmed. Table 5-3 on page 19 and the following illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim is used to define the bit check limits T Lim_min and TLim_max as shown in Table 5-3 on page 19. POUT can be used to control the sensitivity of the receiver. In that application, POUT is set to “1” to reduce the sensitivity. This implies that the receiver operates with full sensitivity after a POR. Table 5-1. Effect of Bit 1 and Bit 2 in Programming the Registers Bit 1 Bit 2 Action 1 x The receiver is set back to polling mode (OFF command) 0 1 The OPMODE register is programmed 0 0 The LIMIT register is programmed Table 5-2. Effect of the Configuration Words within the Registers Bit1 Bit2 Bit2 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 OFF Command OPMODE Register 0 1 BR_Range N Bitcheck VPOUT Sleep X Sleep 0 1 Baud1 Baud0 BitChk1 BitChk0 POUT Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 X Sleep Std XSleep Temp ( D e f a u l t ) 0 0 1 0 0 010110 0 LIMIT Register 0 0 Lim_min Lim_max 0 0 Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 ( D e f a u l t ) 0 0 1 1 1 001100 0

4901A–RKE–11/05 ATA3745 Table 5-3. Effect of the Configuration Word BR_Range BR_Range Baud Rate Range/Extension Factor for Bit Check Limits (XLim)Baud1 Baud0 00 BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default) XLim = 8 (Default) 01 BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4 10 BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 11 BR_Range3 (application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1 Table 5-4. Effect of the Configuration Word NBitcheck NBitcheck Number of Bits to be CheckedBitChk1 BitChk0 00 0 01 3 1 0 6 (Default) 11 9 Table 5-5. Effect of the Configuration Bit VPOUT VPOUT Level of the Multi-purpose Output Port POUTPOUT 0 0 (Default) Table 5-6. Effect of the Configuration Word Sleep Sleep Start Value for Sleep Counter (TSleep = Sleep × XSleep × 1024 × TClk)Sleep4 Sleep3 Sleep 2 Sleep1 Sleep0 0 0 0 0 0 0 (Receiver is continuously polling until a valid signal occurs) 00001 1 ( T Sleep ≈ 2 ms for XSleep = 1 in US/European applications) 00010 2 00011 3 01011 1 1 ( U S A : T Sleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default) 11101 2 9 11110 3 0 1 1 1 1 1 31 (Permanent sleep mode)

4901A–RKE–11/05 ATA3745 Table 5-7. Effect of the Configuration Word XSleep XSleep Extension Factor for Sleep Time (TSleep = Sleep × XSleep × 1024 × TClk)XSleepStd XSleepTemp 0 0 1 (Default) 01 8 ( X Sleep is reset to 1 if bit check fails once) 10 8 ( X Sleep is set permanently) 11 8 ( X Sleep is set permanently) Table 5-8. Effect of the Configuration Word Lim_min Lim_min Lower Limit Value for Bit Check Lim_min < 10 is not applicable (T Lim_min = Lim_min × XLim × TClk) 001010 1 0 001011 1 1 001100 1 2 001101 1 3 001110 14 (Default) (USA: T Lim_min = 228 µs, Europe: TLim_min = 232 µs) 111101 6 1 111110 6 2 111111 6 3 Table 5-9. Effect of the Configuration Word Lim_max Lim_max Upper Limit Value for Bit Check Lim_max < 12 is not applicable (T Lim_max = (Lim_max – 1) × XLim × TClk) 001100 1 2 001101 1 3 001110 1 4 011000 24 (Default) (USA: T Lim_max = 375 µs, Europe: TLim_max = 381 µs) 111101 6 1 111110 6 2 111111 6 3

4901A–RKE–11/05 ATA3745

5.5.1 Conservation of the Register Information

The ATA3745 has integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to Figure 5-13, a power-on reset (POR) is generated if the supply voltage V S drops below the threshold voltage VThReset. The default parameters are programmed into the configura- tion registers in that condition. Once V S exceeds V ThReset , the POR is canceled after the minimum reset period t Rst. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displa ys a reset marker (RM) at pin DATA after a reset. The RM is represented by the fixed frequency f RM at a 50% duty cycle. RM can be canceled via an "L" pulse t1 at pin DATA. The RM implies the following characteristics: f RM is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be misinterpreted by the connected microcontroller.  If the receiver is set back to polling mode via pin DATA, RM cannot be canceled by accident if t1 is applied according to the proposal in “Programming the Configuration Register” on page 22. By means of that mechanism, the receiver cannot lose its register information without communi- cating that condition via the reset marker RM. Figure 5-13. Generation of the Power-on Reset Figure 5-14. Timing of the Register Programming VS POR DATA (ATA3745) X VThReset tRst 1/fRM Out1 (microcontroller) DATA (ATA3745) Serial bi-directional data line X Bit 1 ("0") (Start bit) Bit 2 ("1") (Register select) Bit 13 ("0") (Poll8) Bit 14 ("1") (Poll8R) X t1 t2 t3 t6 t8 X X Programming Frame Receiver on Startup mode t9 TSleep

4901A–RKE–11/05 ATA3745

5.5.2 Programming the C onfiguration Register

The configuration registers are programmed seria lly via the bi-directional data line according to Figure 5-14 on page 21 and Figure 5-15. Figure 5-15. One-wire Connection to a Microcontroller To start programming, the serial data line DATA is pulled by the microcontroller to “L” for the time period t1. When DATA has been released, th e receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the pro- gramming window, the individual bits are set. If the microcontroller pulls down pin DATA for the time period t7 during t5, the corresponding bit is set to “0”. If no programming pulse t7 is issued, this bit is set to “1”. All 14 bits are subsequently programmed in this way. The time frame to pro- gram a bit is defined by t6. Bit 14 is followed by the equivalent time window t9. During this window, the equivalent acknowl- edge pulse t8 (E_Ack) occurs if the mode word just programmed is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. Programming of a register is possible both during sleep and active mode of the receiver. During programming, the LNA, LO, low-pass filter, IF amplifier and the demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to “1”, it represents the OFF command, setting the receiver back to polling mode at the same time. For the length of the programming start pulse t1, the following convention should be considered:  t1(min) < t1 < 1535 × T Clk: [t1(min) is the minimum specified value for the relevant BR_Range] Programming (or the OFF command) is initiated if the receiver is not in reset mode. If the receiver is in reset mode, programming (or the OFF command) is not initiated, and the reset marker RM is still present at pin DATA. This pe riod is generally used to switch the receiver to polling mode. In a reset condition, RM is not canceled by accident.  t1 > 5632 × T Clk Programming (or the OFF command) is initiated in any case. RM is cancelled if present. This period is used if the connected microcontroller detected RM. If a configuration register is pro- grammed, this time period for t1 can generally be used. Note that the capacitive load at pin DATA is limited. The resulting ti me constant t together with an optional external pull-up resistor may not be exceeded to ensure proper operation. Internal pull-up resistor Bi-directional data line DATA I/O ATA3745 Microcontroller DATA (ATA3745) Out 1 (microcontroller)

4901A–RKE–11/05 ATA3745 6. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage V S 6V Power dissipation P tot 450 mW Junction temperature T j 150 °C Storage temperature T stg –55 +125 °C Ambient temperature T amb –40 +85 °C Maximum input level, input matched to 50Ω Pin_max 10 dBm 7. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA 100 K/W 8. Electrical Characteristics All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C Parameters Test Conditions Symbol Min. Typ. Max. Unit Current consumption Sleep mode (XTO and polling logic active) ISoff 190 350 µA IC active (startup, bit check, or receiving mode) Pin DATA = H ISon 7.0 8.6 mA LNA Mixer Third-order intercept point LNA/mixer/IF amplifier input matched according to Figure 3-3 on page 6 IIP3 –28 dBm LO spurious emission at RFIn Input matched according to Figure 3-3 on page 6, required according to I-ETS 300220 ISLORF –73 –57 dBm Noise figure LNA and mixer (DSB) Input matching according to Figure 3-3 on page 6 NF 7 dB LNA_IN input impedance at 433.92 MHz at 315 MHz ZiLNA_IN 1.0 || 1.56 1.3 || 1.0 kΩ || pF kΩ || pF 1 dB compression point (LNA, mixer, IF amplifier) Input matched according to Figure 3-3 on page 6, referred to RFin IP1db –40 dBm Maximum input level Input matched according to Figure 3-3 on page 6, BER ≤ 10-3, ASK mode Pin_max –23 dBm

4901A–RKE–11/05 ATA3745 Local Oscillator Operating frequency range VCO f VCO 309 439 MHz Loop bandwidth of the PLL For best LO noise (design parameter) R1 = 820Ω C9 = 4.7 nF C10 = 1 nF BLoop 100 kHz Capacitive load at pin LF The capacitive load at pin LF is limited if bit check is used. The limitation therefore also applies to self polling. CLF_tot 10 nF XTO operating frequency XTO crystal frequency, appropriate load capacitance must be connected to XTAL

6.764375 MHz

4.90625 MHz

fXTO 6.764375 –50 ppm 4.90625 –50 ppm 6.764375 4.90625 6.764375 +50 ppm 4.90625 +50 ppm MHz MHz Series resonance resistor of the crystal fXTO = 6.764 MHz

4.906 MHz RS

Ω Ω Static capacitance at pin XT0 C XT0 6.5 pF Analog Signal Processing Input sensitivity ASK 600-kHz IF filter Input matched according to Figure 5-1 ASK (level of carrier) BER ≤ 10-3, B = 600 kHz fin = 433.92 MHz/315 MHz T = 25° C, VS = 5V fIF = 1 MHz PRef_ASK BR_Range0 –106 –110 –113.5 dBm BR_Range1 –104.5 –108.5 –112 dBm BR_Range2 –104 –108 –111.5 dBm BR_Range3 –102 –106 –109.5 dBm Sensitivity variation ASK for full operating range including IF filter compared to T amb = 25° C, VS = 5V 600-kHz version fin = 433.92 MHz/315 MHz fIF = 0.81 MHz to 1.19 MHz fIF = 0.75 MHz to 1.25 MHz PASK = PRef_ASK + ∆PRef ∆PRef +3 dB dB SNR to suppress in-band noise signals ASK mode SNR ASK 11 dB Dynamic range RSSI ampl. ∆RRSSI 60 dB Lower cut-off frequency of the data filter CDEM = 33 nF fcu_DF 0.11 0.16 0.20 kHz 8. Electrical Characteristics (Continued) All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C Parameters Test Conditions Symbol Min. Typ. Max. Unit fcu_DF

4901A–RKE–11/05 ATA3745 Recommended CDEM for best performance ASK mode BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 CDEM 8.2 nF nF nF nF Maximum edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 tee_sig 1000 560 320 180 µs µs µs µs Minimum edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 tee_sig 270 156 µs µs µs µs Threshold voltage for reset V ThRESET 1.95 2.8 3.75 V Digital Ports Data output - Saturation voltage LOW - Internal pull-up resistor - Maximum time constant - Maximum capacitive load Iol = 1 mA τ = CL (Rpup//RExt) without external pull-up resistor Rext = 5 kΩ VOI RPup τ CL CL 0.08 0.3 2.5 540 V kΩ µs pF pF POUT output - Saturation voltage LOW - Saturation voltage HIGH IPOUT = 1 mA IPOUT = –1 mA VOl VOh VS – 0.3V 0.08 VS – 0.14V 0.3 V V ASK input - High-level input voltage ASK V Ih 0.8 × VS V ENABLE input - Low-level input voltage - High-level input voltage Idle mode Active mode VIl VIh 0.8 × VS 0.2 × VS V V MODE input - Low-level input voltage - High-level input voltage Division factor = 10 Division factor = 14 VIl VIh 0.8 × VS 0.2 × VS V V TEST input - Low-level input voltage Test input must always be set to LOW VIl 0.2 × VS V 8. Electrical Characteristics (Continued) All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C Parameters Test Conditions Symbol Min. Typ. Max. Unit

4901A–RKE–11/05 ATA3745 9. Electrical Characteristics All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C Parameter Test Condition Symbol 6.76438-Mhz Oscillator (Mode 1) 4.90625-Mhz Oscillator (Mode 0) Variable Oscillator Basic Clock Cycle of the Digital Circuitry Basic clock cycle MODE = 0 (USA) MODE = 1 (Europe) TClk 2.0697 2.0383 1 / (f XTO / 10) 1 / (fXTO / 14) µs µs Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 T XClk 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs Polling Mode Sleep time Sleep and X Sleep are defined in the OPMODE register TSleep Sleep × XSleep × 1024 × 2.0697 Sleep × XSleep × 1024 × 2.0383 Sleep × XSleep × 1024 × TClk ms Start-up time BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Startup 1855 1061 1061 663 1827 1045 1045 653 896.5 512.5 512.5 320.5 × TClk µs µs µs µs Time for Bit check Average bit check time while polling BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Bitcheck 0.45 0.24 0.14 0.14 0.47 0.26 0.16 0.15 ms ms ms ms Bit check time for a valid input signal f Sig NBitcheck = 0 NBitcheck = 3 NBitcheck = 6 NBitcheck = 9 TBitcheck 3 / fSig 6 / fSig 9 / fSig 3.5 / fSig 6.5 / fSig 9.5 / fSig 3 / fSig 6 / fSig 9 / fSig 3.5 / fSig 6.5 / fSig 9.5 / fSig TXClk 3.5 / fSig 6.5 / fSig 9.5 / fSig ms ms ms ms Receiving Mode Intermediate frequency MODE = 0 (USA) MODE = 1 (Europe) fIF 1.0 1.0 f XTO × 64 / 314 fXTO × 64 / 432.92 MHz MHz Baud rate range BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 BR_Range0 × 2 ms / TClk BR_Range1 × 2 ms / TClk BR_Range2 × 2 ms / TClk BR_Range3 × 2 ms / TClk kBaud kBaud kBaud kBaud Minimum time period between edges at pin DATA (Figure 5-9 on page 16) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T DATA_min tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 149 182 37.3 45.5 18.6 22.8 147 179 36.7 44.8 18.3 22.4 × TXClk 11 × TXCl 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk µs µs µs µs µs µs µs µs Maximum low period at DATA (Figure 5-10 on page 16) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T DATA_L_max 2169 1085 542 271 2136 1068 534 267 131 × TXClk 131 × TXClk 131 × TXClk 131 × TXClk µs µs µs µs

4901A–RKE–11/05 ATA3745 OFF command at pin ENABLE (Figure 5-12 on page 17) tDoze 3.1 3.05 1.5 × TClk µs Configuration of the Receiver Frequency of the reset marker (Figure 5-13 on page 21) fRM 117.9 119.8 Hz Programming start pulse (Figure 5-11 on page 17, Figure 5-14 on page 21) BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR 2188 1104 561 290 11656 3176 3176 3176 3176 2155 1087 553 286 11479 3128 3128 3128 3128 1057 × T Clk 533 × TClk 271 × TClk 140 × TClk 5632 × TClk 1535 × TClk 1535 × TClk 1535 × TClk 1535 × TClk µs Programming delay period (Figure 5-11 on page 17, Figure 5-14 on page 21) t2 795 798 783 786 384.5 × TClk 385.5 × TClk µs Synchron- ization pulse (Figure 5-11 on page 17, Figure 5-14 on page 21) t3 265 261 128 × TClk µs Delay until the program window starts (Figure 5-11 on page 17, Figure 5-14 on page 21) t4 131 129 63.5 × TClk µs Programming window (Figure 5-11 on page 17, Figure 5-14 on page 21) t5 530 522 256 × TClk µs Time frame of a bit (Figure 5-14 on page 21) t6 1060 1044 512 × TClk µs 9. Electrical Characteristics All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C Parameter Test Condition Symbol 6.76438-Mhz Oscillator (Mode 1) 4.90625-Mhz Oscillator (Mode 0) Variable Oscillator

4901A–RKE–11/05 ATA3745 Programming pulse (Figure 5-11 on page 17, Figure 5-14 on page 21) t7 133 529 131 521 64 × TClk 256 × TClk µs Equivalent acknowledge pulse: E_Ack (Figure 5-14 on page 21) t8 265 261 128 × TClk µs Equivalent time window (Figure 5-14 on page 21) t9 534 526 258 × TClk µs OFF bit programming window (Figure 5-11 on page 17) t10 930 916 449.5 × TClk µs 9. Electrical Characteristics All parameters refer to GND, VS = 5V, Tamb = 25°C, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. The possible operating range refer to different circuit conditions: VS = 4.5V to 5.5V, Tamb = –40°C to +85°C Parameter Test Condition Symbol 6.76438-Mhz Oscillator (Mode 1) 4.90625-Mhz Oscillator (Mode 0) Variable Oscillator

4901A–RKE–11/05 ATA3745 11. Package Information 10. Ordering Information Extended Type Number Package Remarks ATA3745P3-TGQY SO20 Taped and reeled, Pb-free technical drawings according to DIN specifications Dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 11 0

Printed on recycled paper. 4901A–RKE–11/05 © Atmel Corporation 2005 . All rights reserved. Atmel ®, logo and combinations thereof, Everywhere Y ou Are ® and others, are registered trade- marks or trademarks of Atmel Corporation or its subsidiari es. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTOR Y WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICU LAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR I NCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF AT MEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained her ein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. Atmel Corporation Atmel Operations

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