ATA3741

ATA3741 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Minimal External Circuitry Requirements, No RF Components on the PC Board Except Matching to the Receiver Antenna
• High Sensitivity, Especially at Low Data Rates
• Sensitivity Reduction Possible Even While Receiving
• Fully Integrated VCO
• Low Power Consumption Due to Configurable Self Polling with a Programmable Time Frame Check
• Supply Voltage 4.5V to 5.5V
• Operating Temperature Range –40°C to +105°C
• Single-ended RF Input for Easy Adaptation to λ / 4 Antenna or Printed Antenna on PCB
• Low-cost Solution Due to High Integration Level
• ESD Protection According to MIL-STD. 883 (4 KV HBM) Except Pin POUT (2 KV HBM)
• High Image Frequency Suppression due to 1 MHz IF in Conjunction with a SAW Front-end Filter – Up to 40 dB is Thereby Achievable with Newer SAWs
• Programmable Output Port for Sensitivity Selection or for Controlling External Periphery
• Communication to the Microcontroller Possible via a Single, Bi-directional Data Line
• Power Management (Polling) is also Possible by Means of a Separate Pin via the Microcontroller
• 2 Different IF Bandwidth Versions are Available (300 kHz and 600 kHz)

Description

The ATA3741 is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manchester or Bi-phase code. The receiver is well-suited to operate with Atmel's PLL RF transmitter U2741B. Its main applications are in the areas of telemetering, security technology, and keyless-entry systems. It can be used in the frequency receiving range of f0 = 300 MHz to 450 MHz for ASK or FSK data transmission. All the state- ments made below refer to 433.92-MHz and 315-MHz applications. UHF ASK Receiver IC ATA3741 4899B–RKE–10/06

4899B–RKE–10/06 ATA3741 Figure 1-1. System Block Diagram Figure 1-2. Block Diagram Demod Control ATR3741 1...3 U2741B Antenna Antenna UHF ASK/FSK Remote control transmitter UHF ASK/FSK Remote control receiver

1 Li cell

amp. FSK/ASK Demodulator and data filter IF Amp 4th Order LPF

3 MHz

DEMOD_OUT Limiter out RSSI Sensitivity reduction Standby logic Polling circuit and control logic FE CLK VCO XTO ÷ 64 f 50 kΩ VS FSK/ASK CDEM AVCC SENS AGND DGND MIXVCC LNAGND LNA_IN DATA ENABLE TEST POUT MODE LFGND LFVCC XTO LF DVCC LNA LPF

4899B–RKE–10/06 ATA3741 Pin Configuration Figure 2-1. Pinning SO20 SENS FSK/ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN NC DATA ENABLE TEST POUT MODE DVCC XTO LFGND LF LFVCC Table 2-1. Pin Description Pin Symbol Function SENS Sensitivity-control resistor FSK/ASK Selecting FSK/ASK. Low: FSK, High: ASK CDEM Lower cut-off frequency data filter AVCC Analog power supply AGND Analog ground DGND Digital ground MIXVCC Power supply mixer LNAGND High-frequency ground LNA and mixer LNA_IN RF input NC Not connected LFVCC Power supply VCO LF Loop filter LFGND Ground VCO XTO Crystal oscillator DVCC Digital power supply MODE POUT Programmable output port TEST Test pin, during operation at GND ENABLE Enables the polling mode Low: polling mode off (sleep mode) High: polling mode on (active mode) DATA Data output/configuration input

4899B–RKE–10/06 ATA3741 RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1-MHz IF signal. As seen in the block diagram, the front end consists of an LNA (low noise amplifier), LO (local oscillator), a mixer, and an RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) gen- erates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin LF. fLO is divided by a factor of 64. The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF is controlled in a way that fLO / 64 is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. The crystal should be connected to GND via a capacitor CL according to Figure 3-1. The value of the capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO and thereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy of the crystal and XTO must be considered. Figure 3-1. PLL Peripherals The passive loop filter connected to pin LF is designed for a loop bandwidth of BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the LO. Figure 3-1 shows the appropriate loop filter components to achieve the desired loop bandwidth. If the filter compo- nents are changed for any reason, please note that the maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit check may no longer be possible since fLO can- not settle before the bit check starts to evaluate the incoming data stream. Therefore, self polling also will not work . fXTO fLO DVCC XTO LF LFVCC LFGND VS CL C10 R1 = 820Ω C9 = 4.7 nF C10 = 1 nF VS

4899B–RKE–10/06 ATA3741 fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following for- mula: To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter’s corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO that depends on the logic level at pin mode. This is described by the following formulas: The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applica- tions. For applications where fRF = 315 MHz, MODE must be set to “0”. In the case of fRF = 433.92 MHz, MODE must be set to ”1”. For other RF frequencies, fIF is not equal to 1 MHz. fIF is then dependent on the logical level at pin MODE and on fRF. Table 3-1 summarizes the dif- ferent conditions. The RF input either from an antenna or from a generator must be transformed to the RF input pin LNA_IN. The input impedance of LNA_IN is specified in “Electrical Characteristics” on page 23. The parasitic board inductances and capacitances also influence the input matching. The RF receiver ATA3741 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network, a mirror frequency suppression of ∆PRef = 40 dB can be achieved. There are SAWs available that exhibit a notch at ∆f = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used. Figure 3-2 on page 6 shows a typical input matching network for fRF = 315 MHz and fRF = 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates an input matching to 50Ω with- out a SAW. The input matching networks shown in Figure 3-3 are the reference networks for the parameters given in the “Electrical Characteristics” on page 23. fLO fRF fIF MODE 0 (USA) fIF fLO 314 MODE 1 (Europe) fIF fLO 432.92 Table 3-1. Calculation of LO and IF Frequency Conditions Local Oscillator Frequency Intermediate Frequency fRF = 315 MHz, MODE = 0 fLO = 314 MHz fIF = 1 MHz fRF = 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz

300 MHz < fRF < 365 MHz, MODE = 0

365 MHz < fRF < 450 MHz, MODE = 1

432.92 fIF fLO 432.92

4899B–RKE–10/06 ATA3741 Analog Signal Processing 4.1 IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or fRF = 433.92 MHz is used. For other RF input frequencies, refer to Table 3-1 on page 5 to determine the center frequency. The ATA3741 is available with 2 different IF bandwidths. ATA3741-M2, the version with BIF = 300 kHz, is well suited for ASK systems where Atmel’s PLL transmitter U2741B is used. The receiver ATA3741-M3 employs an IF bandwidth of BIF = 600 kHz. This version can be used together with the U2741B in FSK and ASK mode. If used in ASK applications, it allows higher tolerances for the receiver and PLL transmitter crystals. SAW transmitters exhibit much higher transmit frequency tolerances compared to PLL transmitters. Generally, it is necessary to use BIF = 600 kHz together with such transmitters. 4.2 RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best signal-to-noise ratio (SNR) is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the SNR is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity. In FSK mode, the SNR is not affected by the dynamic range of the RSSI amplifier. The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red. VTh_red is determined by the value of the external resistor RSense. RSense is connected between pin SENS and GND or VS. The output of the comparator is fed into the digital control logic. This makes it possible to operate the receiver at lower sensitivity. If RSense is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of RSense, the maximum sensitivity by the SNR of the LNA input. The reduced sensitivity is dependent on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slightly different values for the LNA gain, the sen- sitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 3-3 on page 6 and exhibits the best possible sensitivity. RSense can be connected to VS or GND via a microcontroller or by the digital output port POUT of the ATA3741 receiver IC. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern shown in Figure 4-1 is issued at pin DATA to indicate that the receiver is still active. Figure 4-1. Steady L State Limited DATA Output Pattern DATA tDATA_L_max tmin2

4899B–RKE–10/06 ATA3741 4.3 FSK/ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK. Logic “L” sets the demodulator to FSK, Logic “H” sets it into ASK mode. In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection refer- ence voltage to a value where a good SNR is achieved. This circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. If the SNR exceeds 10 dB, the data signal can be detected properly. The FSK demodulator is intended to be used for an FSK deviation of ∆f ≥20 kHz. Lower values may be used, but the sensitivity of the receiver will be reduced. The minimum usable deviation is dependent on the selected baud rate. In FSK mode, only BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be detected if the SNR exceeds 2 dB. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the SNR as its bandpass can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order high-pass filter and a 1st-order low-pass filter. The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following formula: In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the “Electrical Characteristics” on page 23. The values are slightly different for ASK and FSK mode. The cut-off frequency of the low-pass filter is defined by the selected baud rate range (BR_Range). BR_Range is defined in the OPMODE register (Section “Configuration of the Receiver” on page 17). BR_Range must be set in accordance to the used baud rate. The ATA3741 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the “Electrical Characteristics” on page 23. They should not be exceeded to maintain full sensitivity of the receiver. 4.4 Receiving Characteristics The RF receiver ATA3741 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end filter is illustrated in Figure 4-2 on page 9. This example relates to ASK mode and the 300-kHz bandwidth version of the ATA3741. FSK mode and the 600-kHz version of the receiver exhibit similar behavior. Note that the mirror frequency is reduced by 40 dB. The plots are printed relative to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered. fcu_DF π 30 kΩ CDEM

4899B–RKE–10/06 ATA3741 When designing the system in terms of receiving bandwidth, the LO deviation must be consid- ered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the ATA3741. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the ATA3741 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode. Figure 4-2. Receiving Frequency Response Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a cor- responding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected does the receiver remain active and transfer the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time, resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, sys- tem response time, data rate, etc. Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected microcontrol- ler, or it can be operated by up to three uni-directional ports. 5.1 Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. As seen in Figure 5-1 on page 10, this clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divider. The division factor is controlled by the logical state at pin MODE. The frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO) (See “RF Front End” on page 4). -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 df (MHz) dP (dB) without SAW with SAW

4899B–RKE–10/06 ATA3741 Figure 5-1. Generation of the Basic Clock Cycle Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls the fol- lowing application-relevant parameters:

• Timing of the polling circuit including bit check
• Timing of analog and digital signal processing
• Timing of register programming
• Frequency of the reset marker
• IF filter center frequency (fIF0) Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent parameters, the electrical characteristics display three conditions for each parameter.
• USA Applications (fXTO = 4.90625 MHz, MODE = 0, TClk = 2.0383 µs)
• Europe Applications (fXTO = 6.76438 MHz, MODE = 1, TClk = 2.0697 µs)
• Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined in the OPMODE register. This clock cycle TXClk is defined by the following for- mulas for further reference: BR_Range = BR_Range0: TXClk = 8 × TClk BR_Range1: TXClk = 4 × TClk BR_Range2: TXClk = 2 × TClk BR_Range3: TXClk = 1 × TClk DVCC XTO MODE TClk fXTO XTO Divider :14/:10 L : USA (:10) H: Europe (:14)

4899B–RKE–10/06 ATA3741 5.2 Polling Mode As shown in Figure 3-2 on page 6, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period TSleep while consuming a low current of IS = ISoff. During the start-up period, TStartup, all sig- nal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit by bit against a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period TBitcheck. This period varies check by check as it is a statistical process. An average value for TBitcheck is given in “Electrical Character- istics” on page 23. During TStartup and TBitcheck the current consumption is IS = ISon. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitter must start the telegram with an adequate preburst. The required length of the preburst is dependent on the polling parameters TSleep, TStar- tup, TBitcheck, and the startup time of a connected microcontroller (TStart_µC). TBitcheck thus depends on the actual bit rate and the number of bits (NBitcheck) to be tested. The following formula indicates how to calculate the preburst length. TPreburst ≥ TSleep + TStartup + TBitcheck + TStart_µC 5.2.1 Sleep Mode The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, on the extension factor XSleep according to Figure 5-4 on page 13, and on the basic clock cycle TClk. It is calculated to be: In US and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd or by bit XSleepTemp, resulting in a different mode of action as described below: XSleepStd = 1 implies the standard extension factor. The sleep time is always extended. XSleepTemp = 1 implies the temporary extension factor. The extended sleep time is used as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 automatically, result- ing in a regular sleep time. This functionality can be used to save current in the presence of a modulated disturber similar to an expected transmitter signal. The connected microcontroller is rarely activated in that condition. If the disturber disappears, the receiver switches back to regu- lar polling and is again sensitive to appropriate transmitter signals. As seen in Table 5-6 on page 19, the highest register value of Sleep sets the receiver to a per- manent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line. ISpoll ISoff TSleep ISon TStartup TBitcheck TSleep TStartup TBitcheck TSleep Sleep XSleep 1024 TClk

4899B–RKE–10/06 ATA3741 5.3.2 Duration of the Bit Check If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit check is a statistical process and TBitcheck varies for each check. Therefore, an average value for TBitcheck is given in “Electrical Characteristics”. TBitcheck depends on the selected baud rate range and on TClk. A higher baud rate range causes a lower value for TBitcheck, resulting in lower current consumption in polling mode. In the presence of a valid transmitter signal, TBitcheck is dependent on the frequency of that sig- nal, on fSig, and on the count of the checked bits, NBitcheck. A higher value for NBitcheck thereby results in a longer period for TBitcheck, requiring a higher value for the transmitter preburst TPreburst. 5.4 Receiving Mode If the bit check is successful for all bits specified by NBitcheck, the receiver switches to receiving mode. As seen in Figure 5-3 on page 12, the internal data signal is then switched to pin DATA. A connected microcontroller can be woken up by the negative edge at pin DATA. The receiver stays in that condition until it is explicitly switched back to polling mode. 5.4.1 Digital Signal Processing The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud rate range (BR_Range). Figure 5-8 illustrates how Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the bit-check counter. Data can change its state only after TXClk elapsed. The edge-to-edge time period tee of the Data signal, as a result, is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to tee ≥TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time, it limits the max- imum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. TDATA_min is to some extent affected by the preceding edge-to-edge time interval tee as illustrated in Figure 5-9 on page 16. If tee is in between the specified bit-check limits, the following level is frozen for the time period TDATA_min = tmin1; if tee is outside that bit check limit, TDATA_min = tmin2 is the relevant stable time period. The maximum time period for DATA to be low is limited to TDATA_L_max. This function ensures a finite response time during programming or switching off the receiver via pin DATA. TDATA_L_max is thereby longer than the maximum time period indicated by the transmitter data stream. Figure 5-10 on page 16 gives an example where Dem_out remains low after the receiver has switched to receiving mode. Figure 5-8. Synchronization of the Demodulator Output Clock bit check counter DATA TXClk Dem_out tee

4899B–RKE–10/06 ATA3741 Table 5-3 through Table 5-9 on page 20 illustrate the effect of the individual configuration words. The default configuration is labeled for each word. BR_Range sets the appropriate baud rate range. At the same time, it defines XLim. XLim is used to define the bit check limits TLim_min and TLim_max as shown in Table 5-3. POUT can be used to control the sensitivity of the receiver. In that application, POUT is set to “1” to reduce the sensitivity. This implies that the receiver operates with full sensitivity after a POR. Table 5-2. Effect of the Configuration Words within the Registers Bit1 Bit2 Bit2 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 OFF Command OPMODE Register BR_Range NBitcheck VPOUT Sleep XSleep Baud1 Baud0 BitChk1 BitChk0 POUT Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 XSleep Std XSleep Temp (Default) LIMIT Register Lim_min Lim_max Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 (Default) Table 5-3. Effect of the Configuration Word BR_Range BR_Range Baud Rate Range/Extension Factor for Bit Check Limits (XLim) Baud1 Baud0 BR_Range0 (Application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default) XLim = 8 (Default) BR_Range1 (Application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4 BR_Range2 (Application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 BR_Range3 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1 Table 5-4. Effect of the Configuration Word NBitcheck NBitcheck Number of Bits to be Checked BitChk1 BitChk0 6 (Default)

4899B–RKE–10/06 ATA3741 Table 5-5. Effect of the Configuration Bit VPOUT VPOUT Level of the Multi-purpose Output Port POUT POUT 0 (Default) Table 5-6. Effect of the Configuration Word Sleep Sleep Start Value for Sleep Counter (TSleep = Sleep × XSleep × 1024 × TClk) Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 0 (Receiver polls continuously until a valid signal occurs) 1 (TSleep ≈ 2 ms for XSleep = 1 in US/European applications) 11 (USA: TSleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default) 31 (Permanent sleep mode) Table 5-7. Effect of the Configuration Word XSleep XSleep Extension Factor for Sleep Time (TSleep = Sleep × XSleep × 1024 × TClk) XSleepStd XSleepTemp 1 (Default) 8 (XSleep is reset to 1 if bit check fails once) 8 (XSleep is set permanently) 8 (XSleep is set permanently)

4899B–RKE–10/06 ATA3741 5.5.1 Conservation of the Register Information The ATA3741 has integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. Figure 5-13 on page 21 shows the timing of a power-on reset (POR) generated if the supply volt- age VS drops below the threshold voltage VThReset. The default parameters are programmed into the configuration registers in that condition. Once VS exceeds VThReset, the POR is canceled after the minimum reset period tRst. A POR is also generated when the supply voltage of the receiver is turned on. Table 5-8. Effect of the Configuration Word Lim_min Lim_min Lower Limit Value for Bit Check (TLim_min = Lim_min × XLim × TClk) Lim_min < 10 is not applicable 14 (Default) (USA: TLim_min = 228 µs, Europe: TLim_min = 232 µs) Table 5-9. Effect of the Configuration Word Lim_max Lim_max Upper Limit Value for Bit Check Lim_max < 12 is not applicable (TLim_max = (Lim_max – 1) × XLim × TClk) 24 (Default) (USA: TLim_max = 375 µs, Europe: TLim_max = 381 µs)

4899B–RKE–10/06 ATA3741 Figure 5-15. One-wire Connection to a Microcontroller To start programming, the serial data line DATA is pulled to “L” by the microcontroller for the time period t1. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the pro- gramming window, the individual bits are set. If the microcontroller pulls down pin DATA for the time period t7 during t5, the according bit is set to “0”. If no programming pulse t7 is issued, this bit is set to “1”. All 14 bits are subsequently programmed in this way. The time frame to program a bit is defined by t6. Bit 14 is followed by the equivalent time window t9. During this window, the equivalent acknowl- edge pulse t8 (E_Ack) occurs if the mode word just programmed is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. Programming of a register is possible both during sleep and active mode of the receiver. During programming, the LNA, LO, low-pass filter, IF amplifier and the demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to “1”, it represents the OFF command to set the receiver back to polling mode at the same time. For the length of the programming start pulse t1, the following convention should be considered:

• t1(min) < t1 < 1535 × TClk: [t1(min) is the minimum specified value for the relevant BR_Range] Programming (or the OFF command) is initiated if the receiver is not in reset mode. If the receiver is in reset mode, programming (or the OFF command) is not initiated, and the reset marker RM is still present at pin DATA. This period is generally used to switch the receiver to polling mode. In a reset condition, RM is not canceled by accident.
• t1 > 5632 × TClk Programming (or the OFF command) is initiated in any case. RM is cancelled if present. This period is used if the connected microcontroller detected RM. If a configuration register is pro- grammed, this time period for t1 can generally be used. Note that the capacitive load at pin DATA is limited. The resulting time constant t together with an optional external pull-up resistor should not be exceeded, to ensure proper operation. Internal pull-up resistor Bi-directional data line DATA I/O ATA3741 Microcontroller DATA (ATA3741) Out 1 (microcontroller)

4899B–RKE–10/06 ATA3741 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage VS V Power dissipation Ptot 450 mW Junction temperature Tj 150 Storage temperature Tstg –55 +125 Ambient temperature Tamb –40 +105 Maximum input level, input matched to 50Ω Pin_max dBm Thermal Resistance Parameters Symbol Value Unit Junction ambient RthJA 100 K/W

Electrical Characteristics

All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameter Test Condition Symbol 6.76438-Mhz Oscillator (Mode 1) 4.90625-Mhz Oscillator (Mode 0) Variable Oscillator Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Basic Clock Cycle of the Digital Circuitry Basic clock cycle MODE = 0 (USA) MODE = 1 (Europe) TClk 2.0697 2.0383 1 / (fXTO / 10) 1 / (fXTO / 14) µs µs Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 TXClk 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs Polling Mode Sleep time Sleep and XSleep are defined in the OPMODE register TSleep Sleep × XSleep × 1024 × 2.0697 Sleep × XSleep × 1024 × 2.0383 Sleep × XSleep × 1024 × TClk ms Start-up time BR_Range0 BR_Range1 BR_Range2 BR_Range3 TStartup 1855 1061 1061 663 1827 1045 1045 653 896.5 512.5 512.5 320.5 × TClk µs µs µs µs Time for bit check Average bit check time while polling BR_Range0 BR_Range1 BR_Range2 BR_Range3 TBitcheck 0.45 0.24 0.14 0.14 0.47 0.26 0.16 0.15 ms ms ms ms Bit check time for a valid input signal fSig NBitcheck = 0 NBitcheck = 3 NBitcheck = 6 NBitcheck = 9 TBitcheck 3 / fSig 6 / fSig 9 / fSig 3.5 / fSig 6.5 / fSig 9.5 / fSig 3 / fSig 6 / fSig 9 / fSig 3.5 / fSig 6.5 / fSig 9.5 / fSig TXClk 3.5 / fSig 6.5 / fSig 9.5 / fSig ms ms ms ms

4899B–RKE–10/06 ATA3741 Time frame of a bit (Figure 5-14) 1060 1044 512 × TClk µs Programming pulse (Figure 5-11, Figure 5-14) 133 529 131 521 64 × TClk 256 × TClk µs Equivalent acknowledge pulse: E_Ack (Figure 5-14) 265 261 128 × TClk µs Equivalent time window (Figure 5-14) 534 526 258 × TClk µs OFF bit programming window (Figure 5-11) t10 930 916 449.5 × TClk µs Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameter Test Condition Symbol 6.76438-Mhz Oscillator (Mode 1) 4.90625-Mhz Oscillator (Mode 0) Variable Oscillator Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit Current consumption Sleep mode (XTO and polling logic active) ISoff 190 350 µA IC active (start-up, bit-check, receiving mode) pin DATA = H ISon 7.0 8.6 mA LNA Mixer Third-order intercept point LNA/mixer/IF amplifier input matched according to Figure 3-3 on page 6 IIP3 –28 dBm LO spurious emission at RFIn Input matched according to Figure 3-3, required according to I-ETS 300220 ISLORF –73 –57 dBm Noise figure LNA and mixer (DSB) Input matching according to Figure 3-3 NF dB LNA_IN input impedance At 433.92 MHz At 315 MHz ZiLNA_IN 1.0 || 1.56 1.3 || 1.0 kΩ || pF kΩ || pF 1 dB compression point (LNA, mixer, IF amplifier) Input matched according to Figure 3-3, referred to RFin IP1db –40 dBm Maximum input level Input matched according to Figure 3-3, BER ≤ 10–3, ASK mode Pin_max –28 –20 dBm dBm

4899B–RKE–10/06 ATA3741 Local Oscillator Operating frequency range VCO fVCO 299 449 MHz Phase noise VCO/LO fosc = 432.92 MHz At 1 MHz At 10 MHz L (fm) –93 –113 –90 –110 dBC/Hz dBC/Hz Spurious of the VCO At ±fXTO –55 –47 dBC VCO gain KVCO 190 MHz/V Loop bandwidth of the PLL For best LO noise (design parameter) R1 = 820Ω C9 = 4.7 nF C10 = 1 nF BLoop 100 kHz Capacitive load at pin LF The capacitive load at pin LF is limited if bit check is used. The limitation therefore also applies to self polling. CLF_tot nF XTO operating frequency XTO crystal frequency, appropriate load capacitance must be connected to XTAL

6.764375 MHz

4.90625 MHz

6.764375 –30 ppm 4.90625 –30 ppm 6.764375 4.90625 6.764375 +30 ppm 4.90625 +30 ppm MHz MHz Series resonance resistor of the crystal fXTO = 6.764 MHz

4.906 MHz

Ω Ω Static capacitance of the crystal Cxto 6.5 pF Analog Signal Processing Input sensitivity ASK 300-kHz IF filter Input matched according to Figure 3-3 ASK (level of carrier) BER ≤ 10–3, B = 300 kHz fin = 433.92 MHz/315 MHz T = 25°C, VS = 5V fIF = 1 MHz PRef_ASK Input sensitivity ASK 300-kHz IF filter BR_Range0 –109 –111 –113 dBm Input sensitivity ASK 300-kHz IF filter BR_Range1 –107 –109 –111 dBm Input sensitivity ASK 300-kHz IF filter BR_Range2 –106 –108 –110 dBm Input sensitivity ASK 300-kHz IF filter BR_Range3 –104 –106 –108 dBm Input sensitivity ASK 600-kHz IF filter Input matched according to Figure 3-3 ASK (level of carrier) BER ≤ 10–3, B = 600 kHz fin = 433.92 MHz/315 MHz T = 25°C, VS = 5V fIF = 1 MHz PRef_ASK Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

4899B–RKE–10/06 ATA3741 Input sensitivity ASK 600-kHz IF filter BR_Range0 –108 –110 –112 dBm Input sensitivity ASK 600-kHz IF filter BR_Range1 –106.5 –108.5 –110.5 dBm Input sensitivity ASK 600-kHz IF filter BR_Range2 –106 –108 –110 dBm Input sensitivity ASK 600-kHz IF filter BR_Range3 –104 –106 –108 dBm Sensitivity variation ASK for the full operating range compared to Tamb = 25°C, VS = 5V 300-kHz and 600-kHz version fin = 433.92 MHz/315 MHz fIF = 1 MHz PASK = PRef_ASK + ∆PRef ∆PRef +2.5 –1.5 dB Sensitivity variation ASK for full operating range including IF filter compared to Tamb = 25°C, VS = 5V 300-kHz version fin = 433.92 MHz/315 MHz fIF = 0.88 MHz to 1.12 MHz fIF = 0.85 MHz to 1.15 MHz PASK = PRef_ASK + ∆PRef ∆PRef +5.5 +7.5 –1.5 –1.5 dB dB Sensitivity variation ASK for full operating range including IF filter compared to Tamb = 25°C, VS = 5V 600-kHz version fin = 433.92 MHz/315 MHz fIF = 0.79 MHz to 1.21 MHz fIF = 0.73 MHz to 1.27 MHz PASK = PRef_ASK + ∆PRef ∆PRef +5.5 +7.5 –1.5 –1.5 dB dB Input sensitivity FSK 600-kHz IF filter Input matched according to Figure 3-3, BER ≤ 10–3, B = 600 kHz fin = 433.92 MHz/315 MHz T = 25°C, VS = 5V fIF = 1 MHz PRef_FSK Input sensitivity FSK 600-kHz IF filter BR_Range0 df ≥ ±20 kHz df ≥ ±30 kHz –95.5 –96.5 –97.5 –98.5 –99.5 –100.5 dBm dBm Input sensitivity FSK 600-kHz IF filter BR_Range1 df ≥ ±20 kHz df ≥ ±30 kHz –94.5 –95.5 –96.5 –97.5 –98.5 –99.5 dBm dBm Sensitivity variation FSK for the full operating range compared to Tamb = 25°C, VS = 5V 600-kHz version fin = 433.92 MHz/315 MHz fIF = 1 MHz PFSK = PRef_FSK + ∆PRef ∆PRef +2.5 –1.5 dB Sensitivity variation FSK for full operating range including IF filter compared to Tamb = 25°C, VS = 5V 600-kHz version fin = 433.92 MHz/315 MHz fIF = 0.86 MHz to 1.14 MHz fIF = 0.82 MHz to 1.18 MHz PFSK = PRef_FSK + ∆PRef ∆PRef +5.5 +7.5 –1.5 –1.5 dB dB FSK frequency deviation The sensitivity of the receiver is higher for higher values of ∆fFSK BR_Range0 BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation ∆fFSK kHz kHz SNR to suppress inband noise signals ASK mode FSK mode SNRASK SNRFSK dB dB Dynamic range RSSI ampl. ∆RRSSI dB Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

4899B–RKE–10/06 ATA3741 Lower cut-off frequency of the data filter fcu_DF 0.11 0.16 0.20 kHz Recommended CDEM for best performance ASK mode BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 CDEM 8.2 nF nF nF nF Recommended CDEM for best performance FSK mode BR_Range0 (Default) BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation CDEM nF nF Maximum edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 tee_sig 1000 560 320 180 µs µs µs µs Upper cut-off frequency data filter Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 fu 2.5 4.3 7.6 13.6 3.1 5.4 9.5 17.0 3.7 6.5 11.4 20.4 kHz kHz kHz kHz Minimum edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 tee_sig 270 156 µs µs µs µs Reduced sensitivity RSense connected from pin SENS to VS, input matched according to Figure 3-3 PRef_Red dBm (peak level) Reduced sensitivity RSense = 56 kΩ, fin = 433.92 MHz, (VS = 5V, Tamb = 25°C) At B = 300 kHz At B = 600 kHz –71 –67 –76 –72 –81 –77 dBm dBm Reduced sensitivity RSense = 100 kΩ, fin = 433.92 MHz At B = 300 kHz At B = 600 kHz –80 –76 –85 –81 –90 –86 dBm dBm Reduced sensitivity RSense = 56 kΩ, fin = 315 MHz At B = 300 kHz At B = 600 kHz –72 –68 –77 –73 –82 –78 dBm dBm Reduced sensitivity RSense = 100 kΩ, fin = 315 MHz At B = 300 kHz At B = 600 kHz –81 –77 –86 –82 –91 –87 dBm dBm Reduced sensitivity variation over full operating range RSense = 56 kΩ RSense = 100 kΩ PRed = PRef_Red + DPRed ∆PRed dB dB Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit fcu_DF π 30 kΩ CDEM

4899B–RKE–10/06 ATA3741 Reduced sensitivity variation for different values of RSense Values relative to RSense = 56 kΩ RSense = 56 kΩ RSense = 68 kΩ RSense = 82 kΩ RSense = 100 kΩ RSense = 120 kΩ RSense = 150 kΩ PRed = PRef_Red + ∆PRed ∆PRed –3.5 –6.0 –9.0 –11.0 –13.5 dB dB dB dB dB dB Threshold voltage for reset VThReset 1.95 2.8 3.75 V Digital Ports Data output - Saturation voltage LOW - Internal pull-up resistor - Maximum time constant - Maximum capacitive load Iol = 1 mA t = CL (Rpup//RExt) without external pull-up resistor Rext = 5 kΩ VOI RPup τ CL CL 0.08 0.3 2.5 540 V kΩ µs pF pF POUT output - Saturation voltage LOW - Saturation voltage HIGH IPOUT = 1 mA IPOUT = –1 mA VOl VOh VS – 0.3V 0.08 VS – 0.14V 0.3 V V FSK/ASK input - Low-level input voltage - High-level input voltage FSK selected ASK selected VIl VIh 0.8 × VS 0.2 × VS V V ENABLE input - Low-level input voltage - High-level input voltage Idle mode Active mode VIl VIh 0.8 × VS 0.2 × VS V V MODE input - Low-level input voltage - High-level input voltage Division factor = 10 Division factor = 14 VIl VIh 0.8 × VS 0.2 × VS V V TEST input - Low-level input voltage Test input must always be set to LOW VIl 0.2 × VS V Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

4899B–RKE–10/06 ATA3741 11. Package Information 12. Revision History 10. Ordering Information Extended Type Number Package Remarks ATA3741P2-TGSY SO20 2: IF bandwidth of 300 kHz, tube, Pb-free ATA3741P2-TGQY SO20 2: IF bandwidth of 300 kHz, taped and reeled, Pb-free ATA3741P3-TGSY SO20 3: IF bandwidth of 600 kHz, tube, Pb-free ATA3741P3-TGQY SO20 3: IF bandwidth of 600 kHz, taped and reeled, Pb-free technical drawings according to DIN specifications Dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4899B-RKE-10/06

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