AT94K

AT94K ATMEL | Alldatasheet

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• Monolithic Field Programmable System Level Integrated Circuit (FPSLIC ™ ) – AT40K SRAM-based FPGA with Embedded High-performance RISC AVR ® Core, Extensive Data and Instruction SRAM and JTAG ICE  5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM ™ – 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM – High-performance DSP Optimized FPGA Core Cell – Dynamically Reconfigurable In-System – FPGA Configuration Access Available On-chip from AVR Microcontroller Core to Support Cache Logic ® Designs – Very Low Static and Dynamic Power Consumption – Ideal for Portable and Handheld Applications  Patented AVR Enhanced RISC Architecture – 120+ Powerful Instructions – Most Single Clock Cycle Execution – High-performance Hardware Multiplier for DSP-based Systems – Approaching 1 MIPS per MHz Performance – C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers – Low-power Idle, Power-save and Power-down Modes – 100 µA Standby and Typical 2-3 mA per MHz Active  Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM – Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM – U pt o1 6K b y t e sx8I n t e r n a l1 5n sD a t aS R A M  JTAG (IEEE std. 1149.1 Compliant) Interface – Extensive On-chip Debug Support – Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports)  AVR Fixed Peripherals – Industry-standard 2-wire Serial Interface – Two Programmable Serial UARTs – Two 8-bit Timer/Counters with Separate Prescaler and PWM – One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM  Support for FPGA Custom Peripherals – AVR Peripheral Control – 16 Decoded AVR Address Lines Directly Accessible to FPGA – FPGA Macro Library of Custom Peripherals  16 FPGA Supplied Internal Interrupts to AVR  Up to Four External Interrupts to AVR  8 Global FPGA Clocks – Two FPGA Clocks Driven from AVR Logic – FPGA Global Clock Access Available from FPGA Core  Multiple Oscillator Circuits – Programmable Watchdog Timer with On-chip Oscillator – Oscillator to AVR Internal Clock Circuit – Software-selectable Clock Frequency – Oscillator to Timer/Counter for Real-time Clock  VCC: 3.0V - 3.6V  3.3V 33 MHz PCI-compliant FPGA I/O – 20 mA Sink/Source High-performance I/O Structures – All FPGA I/O Individually Programmable  High-performance, Low-power 0.35µ CMOS Five-layer Metal Process  State-of-the-art Integrated PC-based Software Suite including Co-verification  5V I/O Tolerant 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE AT94K Series Field Programmable System Level Integrated Circuit Rev. 1138F–FPSLI–06/02

2 AT94K Series FPSLIC

code, e.g., 4201 (no ICE support) and 4201J (with ICE support), see Figure 1.

1. FPSLIC devices should be laid out during PCB design to support a split power supply.

http://www.atmel.com/atmel/acrobat/doc2308.pdf. Table 1. The AT94K Series Characteristics

Figure 1. FPSLIC Device Date Code with JTAG ICE Support The AT94K series architecture is shown in Figure 2. Figure 2. AT94K Series Architecture

4 Interrupt Lines

4 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by executing powerful instructions in a single-clock cycle, and allows system designers to optimize power consumption versus processing speed. The AVR core is based on an enhanced RISC archi- tecture that combines a rich instruction set with 32 general-purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code-efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers at the same clock frequency. The AVR executes out of on- chip SRAM. Both the FPGA configuration SRAM and the AVR instruction code SRAM can be automatically loaded at system power-up using Atmel ’s in-system programmable (ISP) AT17 Series EEPROM Configuration Memories. State-of-the-art FPSLIC design tools, System Designer ™ , were developed in conjunction with the FPSLIC architecture to help reduce overall time-to-market by integrating microcontroller development and debug, FPGA development and Place and Route, and complete system co-verification in one easy-to-use software tool.

Rev. 1138F–FPSLI–06/02 FPGA Core The AT40K core can be used for high-performance designs, by implementing a variety of com- pute-intensive arithmetic functions. These include adaptive finite impulse response (FIR) filters, fast Fourier transforms (FFT), convolvers, interpolators, and discrete-cosine transforms (DCT) that are required for video compression and decompression, encryption, convolution and other multimedia applications. Fast, Flexible and Efficient SRAM The AT40K core offers a patented distributed 10 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel ’s macro generator tool. Fast, Efficient Array and Vector Multipliers The AT40K cores patented 8-sided core cell with direct horizontal, vertical and diagonal cell- to-cell connections implements ultra-fast array multipliers without using any busing resources. The AT40K core ’s Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed. Cache Logic Design The AT40K FPGA core is capable of implementing Cache Logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complement- ing the active logic. The AT40K FPGA core can act as a reconfigurable resource within the FPSLIC environment. Automatic Component Generators The AT40K is capable of implementing user-defined, automatically generated, macros; speed and functionality are unaffected by the macro orientation or density of the target device. This enables the fastest, most predictable and efficient FPGA design approach and minimizes design risk by reusing already proven functions. The Automatic Component Generators work seamlessly with industry-standard schematic and synthesis tools to create fast, efficient designs. The patented AT40K architecture employs a symmetrical grid of small yet powerful cells con- nected to a flexible busing network. Independently controlled clocks and resets govern every column of four cells. The FPSLIC device is surrounded on three sides by programmable I/Os. Core usable gate counts range from 5,000 to 40,000 gates and 436 to 2,864 registers. Pin locations are consistent throughout the FPSLIC family for easy design migration in the same package footprint. The Atmel AT40K FPGA core architecture was developed to provide the highest levels of per- formance, functional density and design flexibility. The cells in the FPGA core array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell ’s small size leads to arrays with large numbers of cells. A simple, high-speed busing network provides fast, efficient communication over medium and long distances. The Symmetrical Array At the heart of the Atmel FPSLIC architecture is a symmetrical array of identical cells. The array is continuous from one edge to the other, except for bus repeaters spaced every four cells, see Figure 3. At the intersection of each repeater row and column is a 32 x 4 RAM block accessible by adjacent buses. The RAM can be configured as either a single-ported or dual- ported RAM, with either synchronous or asynchronous operation.

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Figure 3. Busing Network repeater via a programmable pass gate, allowing long on-chip tri-state buses to be created. Local/local turns are implemented through pass gates in the cell-bus interface.

Figure 4. Busing Plane (One of Five)

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Cell Connections Figure 5(a) depicts direct connections between an FPGA cell and its eight nearest neighbors. plane) and five vertical local buses (one per busing plane). Figure 5. Cell Connections gates connected to Vn and Hn. Up to five simultaneous local/local turns are possible. automatically optimizes designs to utilize the cell flexibility.

Figure 6. The Cell

8 X 1 LUT 8 X 1 LUT

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Figure 7. Some Single Cell Modes

3 LUT3 LUT 4 LUT2:1MUX 3 LUT3 LUT

3 LUT3 LUT

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Figure 9. FreeRAM Logic(1)

Figure 10. FreeRAM Example: 128 x 8 Dual-ported RAM (Asynchronous) (1) Note: 1. These layouts can be generated automatically using the Macro Generators.

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generated within the AVR microcontroller core, see Figure 11. column of four cells can be Set/Reset by a (Plane 5) express bus or by the Global Set/Reset. registers are set at power-up. Figure 11. FPGA Clocks from AVR

ious power-down modes of the AVR. running. In Power-down/save mode the XTAL clock input will be off. Power-save mode but will be off in Power-down mode. be running in all sleep modes. Table 2. Clock Activity in Various Modes

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Figure 12. Clocking (for One Column of Cells) Note: 1. T wo on left edge column of the embedded FPGA array only.

Figure 13. Set/Reset (for One Column of Cells) Some of the bus resources on the embedded FPGA core are used as dual-function resources. Table 3 shows which buses are used in a dual-function mode and which bus plane is used.

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Figure 14. Primary I/O Table 3. Dual-function Buses

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Figure 17. Corner I/Os

 Both FPGA and AVR share access to the 15 ns dual-port SRAM. peripherals which are placed and routed inside the FPGA user logic.  Up to 16 decoded address lines are provided into the FPGA.  Up to 16 interrupts are available from the FPGA to the AVR. programmable peripherals is available within the System Designer tool suite. Figure 18. FPGA/AVR Interface: Interrupts and Addressing page 53. The FPGA I/O interrupts are described beginning on page 57.

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Rev. 1138F–FPSLI–06/02 Program and Data SRAM Up to 36 Kbytes of 15 ns dual-port SRAM reside between the FPGA and the AVR. This SRAM is used by the AVR for program instruction and general-purpose data storage. The AVR is connected to one side of this SRAM; the FPGA is connected to the other side. The port con- nected to the FPGA is used to store data without using up bandwidth on the AVR system data bus. The FPGA core communicates directly with the data SRAM (1) block, viewing all SRAM mem- ory space as 8-bit memory. Note: 1. The unused bits for the FPGA-SRAM address must tie to ‘0’because there is no pull-down circuitry. For the AT94K10 and AT94K40, the internal program and data SRAM is divided into three blocks: 10 Kbytes x 16 dedicated program SRAM, 4 Kbytes x 8 dedicated data SRAM and 6 Kbytes x 16 or 12 Kbytes x 8 configurable SRAM, which may be swapped between program and data memory spaces in 2 Kbytes x 16 or 4 Kbytes x 8 partitions. For the AT94K05, the internal program and data SRAM is divided into three blocks: 4 Kbytes 16 dedicated program SRAM, 4 Kbytes x 8 dedicated data SRAM and 6 Kbytes x 16 or 12 Kbytes x 8 configurable SRAM, which may be swapped between program and data memory spaces in 2 Kbytes x 16 or 4 Kbytes x 8 partitions. The addressing scheme for the configurable SRAM partitions prevents program instructions from overwriting data words and vice versa. Once configured (SCR41:40 – See “System Con- trol Register – FPGA/AVR ” on page 30.), the program memory space remains isolated from the data memory space. SCR41:40 controls internal muxes. Write enable signals allow the memory to be safely segmented. Figure 19 shows the FPSLIC configurable allocation SRAM memory.

Figure 19. FPSLIC Configurable Allocation SRAM Memory (1)(2) be programmed by a full device configuration on power-up.

1. The lower portion of the Data memory is not shared between the AVR and FPGA. The AVR

4 Kbytes x 16 (94K05)

2 Kbytes x 16

4 Kbytes x 8

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Designer software suite using the AVR FPGA interface dialog. Figure 20. Internal SRAM Access – Normal Use from the same location from both sides simultaneously. SCR bit 38 controls the polarity of the clock to the SRAM from the AT40K FPGA. This option is used to allow for code (Program Memory) changes.  The A side (port) is accessed by the AVR.  The B side (port) is accessed by the FPGA/Configuration Logic.

16 Address Lines:

16 Kbytes x 8

 Program memory is 16-bit words. addressing scheme is transparent to the AVR PC).  Data memory is 8-bit words. addressing scheme is transparent to AVR data read/write). SRAM2 in 2 x SRAM blocks, see Table 5. Table 4. AVR Program Decode for SRAM 2:7 (16K16)

03 CR41:40 = 00

05 CR41:40 = 00,01

07 CR41:40 = 00,01,10

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 The B side is accessed by the FPGA/Configuration Logic. ignored – you can overwrite anything in the AVR program memory. used in conjunction with the SCR63 system control register bit. ing AVR reset, the FMXOR bit is cleared by the hardware. (and AVR debug mode) read/writes are to be meaningful to the AVR.  AVR data to FPGA addressing is 1:1 mapping. of the partitions in Table 6. Table 5. AVR Data Decode for SRAM 0:17 (16K8)

03 CR41:40 = 11,10,01

05 CR41:40 = 11,10

07 CR41:40 = 11

Table 6. Summary Table for AVR and FPGA SRAM Addressing

Note: 1. Whether these SRAMs are “Data”or “Program”depends on the SCR40 and SCR41 values. addresses, see Table 7 and Table 8. Table 7. AVR PC Addresses

1000 B300

Table 8. Frame Addresses Table 6. Summary Table for AVR and FPGA SRAM Addressing (Continued)

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Figure 21. AVR SRAM Data Memory Write Using “ST”Instruction Figure 22. AVR SRAM Data Memory Read Using “LD”Instruction

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Modes 2 and 3 are reserved and are used for factory test. taken over by the configuration logic for the CHECK pin during both modes. mended defaults are included in the software. Table 9. Configuration Modes Table 10. FPSLIC System Control Register configuration to another FPSLIC device or to an FPGA. SCR3 controls the operation of the CHECK pin and enables the Check Function. configuration during downloads, and can be used as AVR I/O.

tristate all user I/O and isolate the chip. 1 = CCLK Continues After Configuration. connected to another device I/O. 1 = GCK 0:7 Disabled During Internal and External Configuration Download. the connection from the input buffer to the FPGA array. 1 = FCK 0:1 Disabled During Internal and External Configuration Download. connection from the input buffer to the FPGA array. 1 = Enable On-chip Debugger. 1=E n a b l eT A Pa tu s e rF P G AI / OP o r t s . configuration download on the rising edge of CON, if set. 1 = I/O Tri-state During (Internal and External) Configuration Download.

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SCR35 allows the AVR Reset pin to reset the AVR only. SCR36 protects AVR program code from writes by the FPGA. Device Options in System Designer). SCR48 : SCR53 Defaults dependent on package selected. SCR48 : SCR53 Defaults dependent on package selected. SCR48 : SCR53 Defaults dependent on package selected. SCR48 : SCR53 Defaults dependent on package selected. SCR48 : SCR53 Defaults dependent on package selected. SCR48 : SCR53 Defaults dependent on package selected. Side) on page 177 shows exactly which pins are available in each package.

Note: 1. The AS2 bit must be set in the ASSR register.

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Rev. 1138F–FPSLI–06/02 AVR Core and Peripherals  AVR Core  Watchdog Timer/On-chip Oscillator  Oscillator-to-Internal Clock Circuit  Oscillator-to-Timer/Counter for Real-time Clock  16-bit Timer/Counter and Two 8-bit Timer/Counters  Interrupt Unit  Multiplier  UART (0)  UART (1)  I/O Port D (full 8 bits available on 144-pin or higher devices)  I/O Port E The embedded AVR core is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. The embedded AVR core achieves throughputs approaching 1 MIPS per MHz by executing powerful instructions in a single-clock-cycle, and allows the system architect to opti- mize power consumption versus processing speed. The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 x 8 general-purpose working registers. All the 32 x 8 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent register bytes to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The embedded AVR core provides the following features: 16 general-purpose I/O lines, 32 x 8 general-purpose working registers, Real-time Counter (RTC), 3 flexible timer/counters with compare modes and PWM, 2 UARTs, programmable Watchdog Timer with internal oscillator, 2-wire serial port, and three software-selectable Power-saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, two-wire serial port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the oscil- lator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The embedded AVR core is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators and evaluation kits.

Rev. 1138F–FPSLI–06/02 Instruction Set Nomenclature (Summary) The complete “AVR Instruction Set ” document is available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0856.pdf. Status Register (SREG) SREG: Status register C: Carry flag in status register Z: Zero flag in status register N : N e g a t i v ef l a gi ns t a t u sr e g i s t e r V: Two ’s complement overflow indicator S: N ⊕ V, For signed tests H: Half-carry flag in the status register T: Transfer bit used by BLD and BST instructions I: Global interrupt enable/disable flag Registers and Operands Rd: Destination (and source) register in the register file Rr: Source register in the register file R: Result after instruction is executed K: Constant data k: Constant address b: Bit in the register file or I/O register (0 ≤ b ≤ 7) s: Bit in the status register (0 ≤ s ≤ 2) X,Y,Z: Indirect address register (X = R27:R26, Y = R29:R28 and Z = R31:R30) A: I/O location address q: Displacement for direct addressing (0 ≤ q ≤ 63) I/O Registers Stack STACK: Stack for return address and pushed registers SP: Stack Pointer to STACK Flags ⇔: Flag affected by instruction 0: Flag cleared by instruction 1: Flag set by instruction -: Flag not affected by instruction The instructions EIJMP, EICALL, ELPM, GPM, ESPM (from the megaAVR Instruction Set) are not supported in the FPSLIC device.

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Rev. 1138F–FPSLI–06/02 Complete Instruction Set Summary Conditional Branch Summary Test Boolean Mnemonic Complementary Boolean Mnemonic Comment Rd > Rr Z •(N ⊕ V) = 0 BRLT Rd ≤ Rr Z+(N ⊕ V) = 1 BRGE Signed Rd ≥ Rr (N ⊕ V) = 0 BRGE Rd < Rr (N ⊕ V) = 1 BRLT Signed Rd = Rr Z = 1 BREQ Rd ≠ Rr Z = 0 BRNE Signed Rd ≤ Rr Z+(N ⊕ V) = 1 BRGE Rd > Rr Z •(N ⊕ V) = 0 BRLT Signed Rd < Rr (N ⊕ V) = 1 BRLT Rd ≥ Rr (N ⊕ V) = 0 BRGE Signed R d>R r C+Z=0 B R L O R d ≤ R r C+Z=1 B R S H U n s i g n e d Rd ≥ Rr C = 0 BRSH/BRCC Rd < Rr C = 1 BRLO/BRCS Unsigned Rd = Rr Z = 1 BREQ Rd ≠ Rr Z = 0 BRNE Unsigned Rd ≤ R r C+Z=1 B R S H R d>R r C+Z=0 B R L O U n s i g n e d Rd < Rr C = 1 BRLO/BRCS Rd ≥ Rr C = 0 BRSH/BRCC Unsigned Carry C = 1 BRCS No Carry C = 0 BRCC Simple Negative N = 1 BRMI Positive N = 0 BRPL Simple Overflow V = 1 BRVS No Overflow V = 0 BRVC Simple Zero Z = 1 BREQ Not Zero Z = 0 BRNE Simple Instruction Set Summary Mnemonics Operands Description Operation Flags #Clock Arithmetic and Logic Instructions ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H 1 A D C R d ,R r A d dw i t hC a r r y R d ← Rd + Rr + C Z,C,N,V,S,H 1 ADIW Rd, K Add Immediate to Word Rd+1:Rd ← Rd+1:Rd + K Z,C,N,V,S 2 SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1 SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V ,S,H 1 SBC Rd, Rr Subtract with Carry Rd ← R d-R r-C Z , C , N , V , S , H 1 SBCI Rd, K Subtract Immediate with Carry Rd ← R d-K-C Z , C , N , V , S , H 1 SBIW Rd, K Subtract Immediate from Word Rd+1:Rd ← Rd+1:Rd - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V ,S 1 ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S 1 OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V ,S 1 EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V ,S 1 COM Rd One ’s Complement Rd ← $FF - Rd Z,C,N,V ,S 1 NEG Rd T wo ’s Complement Rd ← $00 - Rd Z,C,N,V,S,H 1 SBR Rd, K Set Bit(s) in Register Rd ← Rd v K Z,N,V ,S 1

Rev. 1138F–FPSLI–06/02 CBR Rd, K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S 1 INC Rd Increment Rd ← Rd + 1 Z,N,V ,S 1 DEC Rd Decrement Rd ← Rd - 1 Z,N,V ,S 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V ,S 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V ,S 1 SER Rd Set Register Rd ← $FF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd × Rr (UU) Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd × Rr (SS) Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd × Rr (SU) Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd × Rr)<<1 (UU) Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd × Rr)<<1 (SS) Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd × Rr)<<1 (SU) Z,C 2 Branch Instructions RJMP k Relative Jump PC ← P C+k+1 N o n e 2 IJMP Indirect Jump to (Z) PC(15:0) ← Z None 2 JMP k Jump PC ← k None 3 RCALL k Relative Call Subroutine PC ← P C+k+1 N o n e 3 ICALL Indirect Call to (Z) PC(15:0) ← Z None 3 CALL k Call Subroutine PC ← k None 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3 CP Rd, Rr Compare Rd - Rr Z,C,N,V ,S,H 1 CPC Rd, Rr Compare with Carry Rd - Rr - C Z,C,N,V ,S,H 1 CPI Rd, K Compare with Immediate Rd - K Z,C,N,V,S,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← P C+2o r3 N o n e 1/2/3 SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ← P C+2o r3 N o n e 1/2/3 SBIC A, b Skip if Bit in I/O Register Cleared if(I/O(A,b) = 0) PC ← PC + 2 or 3 None 1 / 2 / 3 SBIS A, b Skip if Bit in I/O Register Set If(I/O(A,b) = 1) PC ← PC + 2 or 3 None 1 / 2 / 3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC+k+1 None 1 / 2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC+k+1 None 1 / 2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1 / 2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1 / 2 BRCS k Branch if Carry Set if (C = 1) then PC ← P C+k+1 N o n e 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← P C+k+1 N o n e 1/2 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clock

38 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 BRSH k Branch if Same or Higher if (C = 0) then PC ← P C+k+1 N o n e 1/2 BRLO k Branch if Lower if (C = 1) then PC ← P C+k+1 N o n e 1/2 BRMI k Branch if Minus if (N = 1) then PC ← P C+k+1 N o n e 1/2 BRPL k Branch if Plus if (N = 0) then PC ← P C+k+1 N o n e 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1 / 2 BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1 / 2 BRHS k Branch if Half-carry Flag Set if (H = 1) then PC ← P C+k+1 N o n e 1/2 BRHC k Branch if Half-carry Flag Cleared if (H = 0) then PC ← P C+k+1 N o n e 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 / 2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1 / 2 BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1 / 2 Data Transfer Instructions MOV Rd, Rr Copy Register Rd ← Rr None 1 MOVW Rd, Rr Copy Register Pair Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LDS Rd, k Load Direct from Data Space Rd ← (k) None 2 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Increment Rd ← (X), X ← X + 1 None 2 LD Rd, -X Load Indirect and Pre-Decrement X ← X-1 ,R d ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Increment Rd ← (Y), Y ← Y + 1 None 2 LD Rd, -Y Load Indirect and Pre-Decrement Y ← Y-1 ,R d ← (Y) None 2 LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Increment Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Decrement Z ← Z-1 ,R d ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← ( Z+q ) N o n e 2 STS k, Rr Store Direct to Data Space Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Increment (X) ← Rr, X ← X + 1 None 2 ST -X, Rr Store Indirect and Pre-Decrement X ← X-1 ,( X ) ← Rr None 2 ST Y , Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Increment (Y) ← Rr, Y ← Y + 1 None 2 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clock

Rev. 1138F–FPSLI–06/02 ST -Y, Rr Store Indirect and Pre-Decrement Y ← Y-1 ,( Y ) ← Rr None 2 STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Increment (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Decrement Z ← Z-1 ,( Z ) ← Rr None 2 STD Z+q, Rr Store Indirect with Displacement (Z + q) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post- Increment Rd ← (Z), Z ← Z + 1 None 3 IN Rd, A In From I/O Location Rd ← I/O(A) None 1 OUT A, Rr Out To I/O Location I/O(A) ← Rr None 1 PUSH Rr Push Register on Stack ST ACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 Bit and Bit-test Instructions LSL Rd Logical Shift Left Rd(n+1) ←Rd(n),Rd(0)←0,C←Rd(7) Z,C,N,V,H 1 LSR Rd Logical Shift Right Rd(n) ←Rd(n+1),Rd(7)←0,C←Rd(0) Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0) ←C,Rd(n+1)←Rd(n),C←Rd(7) Z,C,N,V,H 1 ROR Rd Rotate Right Through Carry Rd(7) ←C,Rd(n)←Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None 1 BSET s Flag Set SREG(s) ← 1S R E G ( s ) 1 BCLR s Flag Clear SREG(s) ← 0S R E G ( s ) 1 SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 2 CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None 2 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1C 1 CLC Clear Carry C ← 0C 1 SEN Set Negative Flag N ← 1N 1 CLN Clear Negative Flag N ← 0N 1 SEZ Set Zero Flag Z ← 1Z 1 CLZ Clear Zero Flag Z ← 0Z 1 SEI Global Interrupt Enable I ← 1I 1 CLI Global Interrupt Disable I ← 0I 1 SES Set Signed Test Flag S ← 1S 1 Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clock

40 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 Pin Descriptions VCC Supply voltage GND Ground PortD (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal programmable pull-up resistors. The Port D output buffers can be programmed to sink/source either 6 or 20 mA (SCR54 – see “System Control Register – FPGA/AVR”on page 30). As inputs, Port D pins that are externally pulled Low will source current if the programmable pull-up resistors are activated. The Port D pins are input with pull-up when a reset condition becomes active, even if the clock is not running. On lower pin count packages Port D may not be available. Check the Pin List for details. PortE (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal programmable pull-up resistors. The Port E output buffers can be programmed to sink/source either 6 or 20 mA (SCR55 – see “System Control Register – FPGA/AVR”on page 30). As inputs, Port E pins that are externally pulled Low will source current if the pull-up resistors are activated. Port E also serves the functions of various special features. See Table 46 on page 149. The Port E pins are input with pull-up when a reset condition becomes active, even if the clock is not running RX0 Input (receive) to UART(0) – See SCR52 TX0 Output (transmit) from UART(0) – See SCR52 RX1 Input (receive) to UART(1) – See SCR53 TX1 Output (transmit) from UART(1) – See SCR53 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. CLS Clear Signed Test Flag S ← 0S 1 SEV Set Two ’s Complement Overflow V ← 1V 1 CLV Clear Two ’s Complement Overflow V ← 0V 1 SET Set T in SREG T ← 1T 1 CLT Clear T in SREG T ← 0T 1 SEH Set Half-carry Flag in SREG H ← 1H 1 CLH Clear Half-carry Flag in SREG H ← 0H 1 NOP No Operation None 1 SLEEP Sleep (See specific description for Sleep) None 1 WDR Watchdog Reset (See specific description for WDR) None 1 BREAK Break For on-chip debug only None N/A Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clock

42 AT94K Series FPSLIC

When not in use, for low static IDD, add a pull-down resistor to XTAL1. Figure 26. No Clock/Oscillator Connections Figure 27. Time Oscillator Connections instruction is being executed, the next instruction is pre-fetched from the program memory. interrupts are executed). The 16-bit stack pointer is read/write accessible in the I/O space. ported in the AVR architecture. vector address, the higher the priority. The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 28 shows the structure of the 32 x 8 general-purpose working registers in the CPU. Figure 28. AVR CPU General-purpose Working Registers between two registers or on a single-register apply to the entire register file. access of the registers, as the X, Y and Z registers can be set to index any register in the file. will return unknown data if accessed. Ghost memory is not implemented.

4 Kbytes $0060 : $0FFF

8 Kbytes $0060 : $1FFF

12 Kbytes $0060 : $2FFF

16 Kbytes $0060 : $3FFF

44 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 X-register, Y-register and Z-register Registers R26..R31 have some added functions to their general-purpose usage. These regis- ters are address pointers for indirect addressing of the SRAM. The three indirect address registers X, Y and Z have functions as fixed displacement, automatic increment and decre- ment (see the descriptions for the different instructions). ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general-purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories – arithmetic, log- ical and bit-functions. Multiplier Unit The high-performance AVR Multiplier operates in direct connection with all the 32 general-pur- pose working registers. This unit performs 8 x 8 multipliers every two clock cycles. See multiplier details on page 106. SRAM Data Memory External data SRAM (or program) cannot be used with the FPSLIC AT94K family. The five different addressing modes for the data memory cover: Direct, Indirect with Displace- ment, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers. The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic Pre-decrement and Post-incre- ment, the address registers X, Y and Z are decremented and incremented. The entire data address space including the 32 general-purpose working registers and the 64 I/O registers are all accessible through all these addressing modes. See the next section for a detailed description of the different addressing modes. Program and Data Addressing Modes The embedded AVR core supports powerful and efficient addressing modes for access to the program memory (SRAM) and data memory (SRAM, Register File and I/O Memory). This sec- tion describes the different addressing modes supported by the AVR architecture. Register Direct, Single-register Rd The operand is contained in register d (Rd). Register Direct, Two Registers Rd and Rr Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. Data Direct A 16-bit data address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. Data Indirect with Displacement Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word.

Rev. 1138F–FPSLI–06/02 Data Indirect Operand address is the contents of the X-, Y- or the Z-register. Data Indirect with Pre-decrement The X-, Y- or the Z-register is decremented before the operation. Operand address is the dec- remented contents of the X, Y or the Z-register. Data Indirect with Post-increment The X-, Y- or the Z-register is incremented after the operation. The operand address is the content of the X-, Y- or the Z-register prior to incrementing. Direct Program Address, JMP and CALL Program execution continues at the address immediate in the instruction words. Indirect Program Addressing, IJMP and ICALL Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Relative Program Addressing, RJMP and RCALL Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047. Memory Access Times and Instruction Execution Timing This section describes the general access timing concepts for instruction execution and inter- nal memory access. The AVR CPU is driven by the XTAL1 input directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 29 shows the parallel instruction fetches and instruction executions enabled by the Har- vard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks and functions per power-unit.

46 AT94K Series FPSLIC

Figure 29. The Parallel Instruction Fetches and Instruction Executions Figure 30. Single Cycle ALU Operation Figure 31. On-chip Data SRAM Access Cycles

Rev. 1138F–FPSLI–06/02 Memory-mapped I/O The I/O space definition of the embedded AVR core is shown in the following table: AT94K Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page $3F ($5F) SREG I T H S V N Z C 51 $3E ($5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 57 $3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 51 $3C ($5C) Reserved $3B ($5B) EIMF INTF3 INTF2 INTF1 INTF0 INT3 INT2 INT1 INT0 62 $3A ($5A) SFTCR FMXOR WDTS DBG SRST 51 $39 ($59) TIMSK TOIE1 OCIE1A OCIE1B TOIE2 TICIE1 OCIE2 TOIE0 OCIE0 62 $38 ($58) TIFR TOV1 OCF1A OCF1B TOV2 ICF1 OCF2 TOV0 OCF0 63 $37 ($57) Reserved $36 ($56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE 110 $35 ($55) MCUR JTRF JTD SE SM1 SM0 PORF WDRF EXTRF 51 $34 ($54) Reserved $33 ($53) TCCR0 FOC0 PWM0 COM01 COM00 CTC0 CS02 CS01 CS00 69 $32 ($52) TCNT0 Timer/Counter0 (8-bit) 70 $31 ($51) OCR0 Timer/Counter0 Output Compare Register 71 $30 ($50) SFIOR PSR2 PSR10 66 $2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM11 PWM10 76 $2E ($4E) TCCR1B ICNC1 ICES1 ICPE CTC1 CS12 CS11 CS10 77 $2D ($4D) TCNT1H Timer/Counter1 - Counter Register High Byte 78 $2C ($4C) TCNT1L Timer/Counter1 - Counter Register Low Byte 78 $2B ($4B) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 79 $2A ($4A) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 79 $29 ($49) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 79 $28 ($48) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 79 $27 ($47) TCCR2 FOC2 PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 69 $26 ($46) ASSR AS2 TCN20B OCR2UB TCR2UB 73 $25 ($45) ICR1H Timer/Counter1 - Input Capture Register High Byte 80 $24 ($44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 80 $23 ($43) TCNT2 Timer/Counter2 (8-bit) 70 $22 ($42) OCR2 Timer/Counter 2 Output Compare Register 71 $21 ($41) WDTCR WDTOE WDE WDP2 WDP1 WDP0 83 $20 ($40) UBRRHI UART1 Baud Rate High Nibble [11..8] UART0 Baud Rate Low Nibble [11..8] 105 $1F ($3F) TWDR 2-wire Serial Data Register 111 $1E ($3E) TWAR 2-wire Serial Address Register 112 $1D ($3D) TWSR 2-wire Serial Status Register 112 $1C ($3C) TWBR 2-wire Serial Bit Rate Register 109 $1B ($3B) FPGAD FPGA Cache Data Register (D7 - D0) 52 $1A ($3A) FPGAZ FPGA Cache Z Address Register (T3 - T0) (Z3 - Z0) 53 $19 ($39) FPGAY FPGA Cache Y Address Register (Y7 - Y0) 53 $18 ($38) FPGAX FPGA Cache X Address Register (X7 - X0) 53 $17 ($37) FISUD FPGA I/O Select, Interrupt Mask/Flag Register D (Reserved on A T94K05) 54, 56

48 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 Note: 1. The On-chip Debug Register (OCDR) is detailed on the “FPSLIC On-chip Debug System”distributed within Atmel and select third-party vendors only under Non-Disclosure Agreement (NDA). Contact fpslic@atmel.com for a copy of this document. The embedded AVR core I/Os and peripherals, and all the virtual FPGA peripherals are placed in the I/O space. The differ- ent I/O locations are directly accessed by the IN and OUT instructions transferring data between the 32 x 8 general- purpose working registers and the I/O space. I/O registers within the address range $00 – $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. When using the I/O specific instructions IN, OUT, the I/O register address $00 – $3F are used, see Figure 32. When addressing I/O registers as SRAM, $20 must be added to this address. All I/O register addresses throughout this document are shown with the SRAM address in parentheses. $16 ($36) FISUC FPGA I/O Select, Interrupt Mask/Flag Register C (Reserved on A T94K05) 54, 56 $15 ($35) FISUB FPGA I/O Select, Interrupt Mask/Flag Register B 54, 56 $14 ($34) FISUA FPGA I/O Select, Interrupt Mask/Flag Register A 54, 56 $13 ($33) FISCR FIADR XFIS1 XFIS0 53 $12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 124 $11 ($31) DDRD DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 124 $10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 124 $0F ($2F) Reserved $0E ($2E) Reserved $0D ($2D) Reserved $0C ($2C) UDR0 UART0 I/O Data Register 101 $0B ($2B) UCSR0A RXC0 TXC0 UDRE0 FE0 OR0 U2X0 MPCM0 101 $0A ($2A) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 CHR90 RXB80 TXB80 103 $09 ($29) UBRR0 UART0 Baud-rate Register 105 $08 ($28) OCDR (Reserved) IDRD Reserved(1) $07 ($27) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 126 $06 ($26) DDRE DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 126 $05 ($25) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 126 $04 ($24) Reserved $03 ($23) UDR1 UART1 I/O Data Register 101 $02 ($22) UCSR1A RXC1 TXC1 UDRE1 FE1 OR1 U2X1 MPCM1 101 $01 ($21) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 CHR91 RXB81 TXB81 103 $00 ($20) UBRR1 UART1 Baud-rate Register 105 AT94K Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page

Figure 32. Memory-mapped I/O is located at memory addresses $20 - $5F. As there are only 6 bits available to refer to the I/O space, the address is shifted down 2 bits. For compatibility with future devices, reserved bits should be written zero if accessed. Reserved I/O memory addresses should never be written. clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

50 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 Status Register – SREG The AVR status register (1) – SREG – at I/O space location $3F ($5F) is defined as: Note: 1. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.  B i t7-I :G l o b a lI n t e r r u p tE n a b l e The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individ- ual interrupt enable control is then performed in separate control registers. If the global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by the hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.  B i t6-T :B i tC o p yS t o r a g e The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and des- tination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.  Bit 5 - H: Half-carry Flag The half-carry flag H indicates a half-carry in some arithmetic operations.  B i t4-S :S i g nB i t ,S=N ⊕ V The S-bit is always an exclusive or between the negative flag N and the two ’s complement overflow flag V.  B i t3-V :T w o’s Complement Overflow Flag The two’s complement overflow flag V supports two ’s complement arithmetics.  B i t2-N :N e g a t i v eF l a g The negative flag N indicates a negative result from an arithmetical or logical operation.  B i t1-Z :Z e r oF l a g The zero flag Z indicates a zero result from an arithmetical or logical operation.  B i t0-C :C a r r yF l a g The carry flag C indicates a carry in an arithmetical or logical operation. Stack Pointer – SP The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). Future versions of FPSLIC may support up to 64K Bytes of memory; therefore, all 16 bits are used. B i t 76543210 $3F ($5F) I THSVNZCS R E G Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 1 51 41 31 21 11 09 8 $3E ($5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH $3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R / WR / WR / WR / WR / WR / WR / WR / W I n i t i a l V a l u e 00000000 00000000

Rev. 1138F–FPSLI–06/02 The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt RETI. Software Control of System Configuration The software control register will allow the software to manage select system level configura- tion bits. Software Control Register – SFTCR  Bits 7..4 - Res: Reserved Bits These bits are reserved in the AT94K and always read as zero.  Bit 3 - FMXOR: Frame Mode XOR (Enable/Disable) This bit is XORed with the System Control Register’s Enable Frame Interface bit. The behavior when this bit is set to 1 is dependent on how the SCR was initialized. If the Enable Frame Interface bit in the SCR is 0, the FMXOR bit enables the Frame Interface when set to 1. If the Enable Frame Interface bit in the SCR is 1, the FMXOR bit disables the Frame Interface when set to 1. During AVR reset, the FMXOR bit is cleared by the hardware.  Bit 2 - WDTS: Software Watchdog Test Clock Select When this bit is set to 1, the test clock signal is selected to replace the AVR internal oscillator into the associated watchdog timer logic. During AVR reset, the WDTS bit is cleared by the hardware.  Bit 1 - DBG: Debug Mode When this bit is set to 1, the AVR can write its own program SRAM. During AVR reset, the DBG bit is cleared by the hardware.  Bit 0 - SRST: Software Reset When this bit is set (one), a reset request is sent to the system configuration external to the AVR. Appropriate reset signals are generated back into the AVR and configuration download is initiated. A software reset will cause the EXTRF bit in the MCUR register to be set (one), which remains set throughout the AVR reset and may be read by the restarted program upon reset complete. The external reset flag is set (one) since the requested reset is issued from the system configuration external to the AVR core. During AVR reset, the SRST bit is cleared by the hardware. B i t 76543210 $3A ($5A) ---- FMXOR WDTS DBG SRST SFTCR Read/Write R R R R R/W R/W R/W R/W I n i t i a l V a l u e 00000000

52 AT94K Series FPSLIC

cleared by hardware during AVR reset. write this bit to the desired value twice within four cycles to change its value. This bit selects between the three available Sleep modes as shown in Table 11. ing a zero to the PORF bit. The bit will not be cleared by the hardware during AVR reset. This bit is set if a watchdog reset occurs. The bit is cleared by writing a logic 0 to the flag. Table 11. Sleep Mode Select

00 I d l e

01 R e s e r v e d

11 P o w e r - s a v e

Rev. 1138F–FPSLI–06/02 FPGA Cache Logic FPGA Cache Data Register – FPGAD The FPGAD I/O Register address is not supported by a physical register; it is simply the I/O address that, if written to, generates the FPGA Cache I/O write strobe. The CACHEIOWE sig- nal is a qualified version of the AVR IOWE signal. It will only be active if an OUT or ST (store to) instruction references the FPGAD I/O address. The FPGAD I/O address is write-sensitive- only; an I/O read to this location is ignored. If the AVR Cache Interface bit in the SCR [BIT62] is set (one), the data being “written”to this address is cached to the FPGA address specified by the FPGAX..Z registers (see below) during the active CACHEIOWE strobe. FPGA Cache Z Address Registers – FPGAX..Z The three FPGA Cache address registers combine to form the 24-bit address, CAC- HEADDR[23:0], delivered to the FPGA cache logic outside the AVR block during a write to the FPGAD I/O Register (see above). FPGA I/O Selection by AVR Sixteen select signals are sent to the FPGA for I/O addressing. These signals are decoded from four I/O registry addresses (FISUA...D) and extended to sixteen with two bits from the FPGA I/O Select Control Register (FISCR). In addition, the FPGAIORE and FPGAIOWE sig- nals are qualified versions of the IORE and IOWE signals. Each will only be active if one of the four base I/O addresses are referenced. It is necessary for the FPGA design to implement any required registers for each select line; each qualified with either the FPGAIORE or FPGAIOWE strobe. Refer to the FPGA/AVR Interface section for more details . Only the FISCR registers physically exist. The FISUA...D I/O addresses for the purpose of FPGA I/O selection are NOT supported by AVR Core I/O space registers; they are simply I/O addresses (available to 1 cycle IN/OUT instructions) which trigger appropriate enabling of the FPGA select lines and the FPGA IORE/IOWE strobes (see Figure 18 on page 21). FPGA I/O Select Control Register – FISCR  Bit 7 - FIADR: FPGA Interrupt Addressing Enable When FIADR is set (one), the four dual-purpose I/O addresses, FISUA..D, are mapped to four physical registers that provide memory space for FPGA interrupt masking and interrupt flag status. When FIADR is cleared (zero), and I/O read or write to one of the four dual-purpose I/O addresses, FISUA..D, will access its associated group of four FPGA I/O select lines. The XFIS1 and XFIS0 bits (see Table 12) further determine which one select line in the accessed group is set (one). A read will assign the FPGA I/O read enable to the AVR I/O read enable (FPGAIORE ← IORE) and a write, the FPGA I/O write enable to the AVR I/O write enable B i t 76543210 $1B ($3B) MSB LSB FPGAD R e a d / W r i t e WWWWWWWW Initial Value N/A N/A N/A N/A N/A N/A N/A N/A B i t 76543210 $18 ($38) FCX7 FCX6 FCX5 FCX4 FCX3 FCX2 FCX1 FCX0 FPGAX $19 ($39) FCY7 FCY6 FCY5 FCY4 FCY3 FCY2 FCY1 FCY0 FPGAY $1A ($3A) FCT3 FCT2 FCT1 FCT0 FCZ3 FCZ2 FCZ1 FCZ0 FPGAZ Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $13 ($33) F I A D R -----X F I S 1 X F I S 0 F I S C R R e a d / W r i t e R / W RRRRRR / W R / W I n i t i a l V a l u e 00000000

54 AT94K Series FPSLIC

FIADR bit will be cleared (zero) during AVR reset. These bits are reserved and always read as zero. will access one of four groups. Table 12 details the FPGA I/O selection scheme. Note: 1. Not available on A T94K05. nals. Each will only be active if one of the four base I/O addresses is accessed. FPGA design to load zeros (8 ’h00) from the D-bus into appropriate registers. Table 12. FPGA I/O Select Line Scheme

I/O select lines and data presented on the 8-bit AVR –FPGA data bus. Note: 1. IOSEL 15..8 are not available on A T94K05. ;which was placed into register FISUD. Table 13. FISCR Register Setups and I/O Select Lines.

56 AT94K Series FPSLIC

Figure 33. Out Instruction – AVR Writing to the FPGA Note: 1. AVR expects Write to be captured by the FPGA upon posedge of the AVR clock. Figure 34. In Instruction – AVR Reading FPGA Notes: 1. AVR captures read data upon posedge of the AVR clock.

1. At the end of an FPGA read cycle, there is a chance for the AVR data bus contention

from AVR DBUS (= FPGA Data Out), this is a “don’tc a r e”situation.

Rev. 1138F–FPSLI–06/02 FPGA I/O Interrupt Control by AVR This is an alternate memory space for the FPGA I/O Select addresses. If the FIADR bit in the FISCR register is set to logic 1, the four I/O addresses, FISUA - FISUD, are mapped to physi- cal registers and provide memory space for FPGA interrupt masking and interrupt flag status. If the FIADR bit in the FISCR register is cleared to a logic 0, the I/O register addresses will be decoded into FPGA select lines. All FPGA interrupt lines into the AVR are negative edge triggered. See page 58 for interrupt priority. Interrupt Control Registers – FISUA..D  Bits 7..4 - FIF3 - 0: FPGA Interrupt Flags 3 - 0 The 16 FPGA interrupt flag bits all work the same. Each is set (one) by a valid negative edge transition on its associated interrupt line from the FPGA. Valid transitions are defined as any change in state preceded by at least two cycles of the old state and succeeded by at least two cycles of the new state. Therefore, it is required that interrupt lines transition from 1 to 0 at least two cycles after the line is stable High; the line must then remain stable Low for at least two cycles following the transition. Each bit is cleared by the hardware when executing the cor- responding interrupt handling vector. Alternatively, each bit will be cleared by writing a logic 1 to it. When the I-bit in the Status Register, the corresponding FPGA interrupt mask bit and the given FPGA interrupt flag bit are set (one), the associated interrupt is executed.  Bits 7..4 - FIF7 - 4: FPGA Interrupt Flags 7 - 4 See Bits 7..4 - FIF3 - 0: FPGA Interrupt Flags 3 - 0 .  Bits 7..4 - FIF11 - 8: FPGA Interrupt Flags 11 - 8 See Bits 7..4 - FIF3 - 0: FPGA Interrupt Flags 3 - 0 . Not available on the AT94K05.  Bits 7..4 - FIF15 - 12: FPGA Interrupt Flags 15 - 12 See Bits 7..4 - FIF3 - 0: FPGA Interrupt Flags 3 - 0 . Not available on the AT94K05.  Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks 3 - 0 (1) The 16 FPGA interrupt mask bits all work the same. When a mask bit is set (one) and the I-bit in the Status Register is set (one), the given FPGA interrupt is enabled. The corresponding interrupt handling vector is executed when the given FPGA interrupt flag bit is set (one) by a negative edge transition on the associated interrupt line from the FPGA. Note: 1. FPGA interrupts 3 - 0 will cause a wake-up from the AVR Sleep modes. These interrupts are treated as low-level triggered in the Power-down and Power-save modes, see “Sleep Modes”on page 66.  Bits 3..0 - FINT7 - 4: FPGA Interrupt Masks 7 - 4 See Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks 3 - 0.  Bits 3..0 - FINT11 - 8: FPGA Interrupt Masks 11 - 8 See Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks 3 - 0. Not available on the AT94K05.  Bits 3..0 - FINT15 - 12: FPGA Interrupt Masks 15 -12 See Bits 3..0 - FINT3 - 0: FPGA Interrupt Masks 3 - 0. Not available on the AT94K05. B i t 76543210 $14 ($34) FIF3 FIF2 FIF1 FIF0 FINT3 FINT2 FINT1 FINT0 FISUA $15 ($35) FIF7 FIF6 FIF5 FIF4 FINT7 FINT6 FINT5 FINT4 FSUB $16 ($36) FIF11 FIF10 FIF9 FIF8 FINT11 FINT10 FINT9 FINT8 FISUC $17 ($37) FIF15 FIF14 FIF13 FIF12 FINT15 FINT14 FINT13 FINT12 FISUD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

58 AT94K Series FPSLIC

together with the I-bit in the status register in order to enable the interrupt. priority levels of the different interrupts. The lower the address the higher the priority level. RESET has the highest priority, and next is FPGA_INT0 – the FPGA Interrupt Request 0 etc. Table 14. Reset and Interrupt Vectors

Table 14. Reset and Interrupt Vectors (Continued)

60 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 The most typical program setup for the Reset and Interrupt Vector Addresses are: Note: 1. Not Available on A T94K05. However, the vector jump table positions must be maintained for appropriate UART and 2-wire serial interrupt jumps. Address Labels Code Comments $0000 jmp RESET Reset Handle: Program Execution Starts Here $0002 jmp FPGA_INT0 ; FPGA Interrupt0 Handle $0004 jmp EXT_INT0 ; External Interrupt0 Handle $0006 jmp FPGA_INT1 ; FPGA Interrupt1 Handle $0008 jmp EXT_INT1 ; External Interrupt1 Handle $000A jmp FPGA_INT2 ; FPGA Interrupt2 Handle $000C jmp EXT_INT2 ; External Interrupt2 Handle $000E jmp FPGA_INT3 ; FPGA Interrupt3 Handle $0010 jmp EXT_INT3 ; External Interrupt3 Handle $0012 jmp TIM2_COMP ; Timer/Counter2 Compare Match Interrupt Handle $0014 jmp TIM2_OVF ; Timer/Counter2 Overflow Interrupt Handle $0016 jmp TIM1_CAPT ; Timer/Counter1 Capture Event Interrupt Handle $0018 jmp TIM1_COMPA ; Timer/Counter1 Compare Match A Interrupt Handle $001A jmp TIM1_COMPB ; Timer/Counter1 Compare Match B Interrupt Handle $001C jmp TIM1_OVF ; Timer/Counter1 Overflow Interrupt Handle $001E jmp TIM0_COMP ; Timer/Counter0 Compare Match Interrupt Handle $0020 jmp TIM0_OVF ; Timer/Counter0 Overflow Interrupt Handle $0022 jmp FPGA_INT4 ; FPGA Interrupt4 Handle $0024 jmp FPGA_INT5 ; FPGA Interrupt5 Handle $0026 jmp FPGA_INT6 ; FPGA Interrupt6 Handle $0028 jmp FPGA_INT7 ; FPGA Interrupt7 Handle $002A jmp UART0_RXC ; UART0 Receive Complete Interrupt Handle $002C jmp UART0_DRE ; UART0 Data Register Empty Interrupt Handle $002E jmp UART0_TXC ; UART0 Transmit Complete Interrupt Handle $0030 jmp FPGA_INT8 ; FPGA Interrupt8 Handle (1) $0032 jmp FPGA_INT9 ; FPGA Interrupt9 Handle (1) $0034 jmp FPGA_INT10 ; FPGA Interrupt10 Handle (1) $0036 jmp FPGA_INT11 ; FPGA Interrupt11 Handle (1) $0038 jmp UART1_RXC ; UART1 Receive Complete Interrupt Handle $003A jmp UART1_DRE ; UART1 Data Register Empty Interrupt Handle $003C jmp UART1_TXC ; UART1 Transmit Complete Interrupt Handle $003E jmp FPGA_INT12 ; FPGA Interrupt12 Handle (1) $0040 jmp FPGA_INT13 ; FPGA Interrupt13 Handle (1) $0042 jmp FPGA_INT14 ; FPGA Interrupt14 Handle (1) $0044 jmp FPGA_INT15 ; FPGA Interrupt15 Handle (1) $0046 jmp TWS_INT ; 2-wire Serial Interrupt RESET: $0048 ldi r16,high(RAMEND) ; Main program start $0049 out SPH,r16 $004A ldi r16,low(RAMEND) $004B out SPL,r16 $004C <instr> xxx

FPGA configuration has entered Idle mode. code can be placed at these locations. The circuit diagram in Figure 35 shows the reset logic. Table 15 defines the timing and electrical parameters of the reset circuitry. Figure 35. Reset Logic

62 AT94K Series FPSLIC

Note: 1. The Power-on Reset will not work unless the supply voltage has been below V POT (falling). – VPOT, regardless of the V CC rise time (see Figure 36 and Figure 37). Figure 36. MCU Start-up, RESET Tied to VCC Figure 37. Watchdog Reset during Operation Table 15. Reset Characteristics (V CC =3 . 3 V )

5 CPU

1 XTAL CYCLE

Low for a period after V CC has been applied, the Power-on Reset period can be extended. R e f e rt oF i g u r e3 8f o rat i m i n ge x a m p l eo nt h i s . Figure 38. MCU Start-up, RESET Controlled Externally MCU after the Time-out period t TOUT has expired. Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t TOUT. Software Reset See “Software Control of System Configuration ”on page 51. in the peripheral control registers. set (one) when a Return from Interrupt instruction (RETI) is executed. bit is set (one), and will be executed by order of priority. when returning from an interrupt routine. This must be handled by software.

64 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 External Interrupt Mask/Flag Register – EIMF  Bits 3..0 - INT3, 2, 1, 0: External Interrupt Request 3, 2, 1, 0 Enable When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The external interrupts are always nega- tive edge triggered interrupts, see “Sleep Modes”on page 66.  Bits 7..4 - INTF3, 2, 1, 0: External Interrupt 3, 2, 1, 0 Flags When a falling edge is detected on the INT3, 2, 1, 0 pins, an interrupt request is triggered. The corresponding interrupt flag, INTF3, 2, 1, 0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT3, 2, 1, 0 in EIMF, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logic 1 to it. Timer/Counter Interrupt Mask Register – TIMSK  Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Inter- rupt Flag Register – TIFR.  Bit 6 - OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt is exe- cuted if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register – TIFR.  Bit 5 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is exe- cuted if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register – TIFR.  Bit 4 - TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter inter- rupt flag register – TIFR.  Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 input capture event interrupt is enabled. The corresponding interrupt is exe- cuted if a capture-triggering event occurs on pin 29, (IC1), i.e., when the ICF1 bit is set in the Timer/Counter interrupt flag register – TIFR. B i t 76543210 $3B ($5B) INTF3 INTF2 INTF1 INTF0 INT3 INT2 INT1 INT0 EIMF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $39 ($39) TOIE1 OCIE1A OCIE1B TOIE2 TICIE1 OCIE2 TOIE0 OCIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

Rev. 1138F–FPSLI–06/02  Bit 2 - OCIE2: Timer/Counter2 Output Compare Interrupt Enable When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter interrupt flag register – TIFR.  Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Inter- rupt Flag Register – TIFR.  Bit 0 - OCIE0: Timer/Counter0 Output Compare Interrupt Enable When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. Timer/Counter Interrupt Flag Register – TIFR  Bit 7 - TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by the hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic 1 to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000.  B i t6-O C F 1 A :O u t p u tC o m p a r eF l a g1 A The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A – Output Compare Register 1A. OCF1A is cleared by the hardware when exe- cuting the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logic 1 to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare Interrupt Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed.  B i t5-O C F 1 B :O u t p u tC o m p a r eF l a g1 B The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B – Output Compare Register 1B. OCF1B is cleared by the hardware when exe- cuting the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a logic 1 to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match Interrupt Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Inter- rupt is executed.  Bit 4 - TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by the hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic 1 to the flag. When the I-bit in SREG, and TOIE2 (Timer/Counter1 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 advances from $00. B i t 76543210 $38 ($58) TOV1 OCF1A OCF1B TOV2 ICF1 OCF2 TOV0 OCF0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

66 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02  Bit 3 - ICF1: Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register – ICR1. ICF1 is cleared by the hard- ware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic 1 to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.  Bit 2 - OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and the data in OCR2 – Output Compare Register 2. OCF2 is cleared by the hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic 1 to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2 Output Compare Interrupt is executed.  Bit 1 - TOV0: Timer/Counter0 Overflow Flag The TOV0 bit is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by the hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic 1 to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 advances from $00.  Bit 0 - OCF0: Output Compare Flag 0 The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and the data in OCR0 – Output Compare Register 0. OCF0 is cleared by the hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic 1 to the flag. When the I-bit in SREG, and OCIE0 (Timer/Counter2 Compare Interrupt Enable), and the OCF0 are set (one), the Timer/Counter0 Output Compare Interrupt is executed. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini- mum. Four clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this four clock-cycle period, the Pro- gram Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is serviced. A return from an interrupt handling routine (same as for a subroutine call routine) takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the Stack, and the Stack Pointer is incremented by 2. When the AVR exits from an inter- rupt, it will always return to the main program and execute one more instruction before any pending interrupt is serviced. Sleep Modes To enter any of the three Sleep modes, the SE bit in MCUR must be set (one) and a SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUR register select which Sleep mode (Idle, Power-down, or Power-save) will be activated by the SLEEP instruction, see T a b l e1 1o np a g e5 2 . In Power-down and Power-save modes, the four external interrupts, EXT_INT0...3, and FPGA interrupts, FPGA INT0...3, are triggered as low level-triggered interrupts. If an enabled inter- rupt occurs while the MCU is in a Sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the reg- ister file, SRAM, and I/O memory are unaltered. If a reset occurs during Sleep mode, the MCU wakes up and executes from the Reset vector

Rev. 1138F–FPSLI–06/02 Idle Mode When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the Idle mode, stopping the CPU but allowing UARTs, Timer/Counters, Watchdog 2-wire Serial and the Interrupt System to continue operating. This enables the MCU to wake-up from external triggered interrupts as well as internal ones like the Timer Overflow and UART Receive Com- plete interrupts. When the MCU wakes up from Idle mode, the CPU starts program execution immediately. Power-down Mode When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the Power-down mode. In this mode, the external oscillator is stopped, while the external inter- rupts and the watchdog (if enabled) continue operating. Only an external reset, a watchdog reset (if enabled), or an external level interrupt can wake-up the MCU. In Power-down and Power-save modes, the four external interrupts, EXT_INT0...3, and FPGA interrupts, FPGA_INT0...3, are treated as low-level triggered interrupts. If a level-triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake-up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock, and if the input has the required level during this time, the MCU will wake-up. The period of the watchdog oscillator is 1 µs (nominal) at 3.3V and 25 °C. The frequency of the watchdog oscillator is voltage dependent. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same time-set bits that define the reset time-out period. The wake-up period is equal to the clock reset period, as shown in Figure 21 on page 89. If the wake-up condition disappears before the MCU wakes up and starts to execute, the inter- rupt causing the wake-up will not be executed. Power-save Mode When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power-save mode. This mode is identical to power-down, with one exception: If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. In addition to the power-down wake-up sources, the device can also wake-up from either Timer Overflow or Output Compare event from Timer/Counter2 if the cor- responding Timer/Counter2 interrupt enable bits are set in TIMSK. To ensure that the part executes the Interrupt routine when waking up, also set the global interrupt enable bit in SREG. When waking up from Power-save mode by an external interrupt, two instruction cycles are executed before the interrupt flags are updated. When waking up by the asynchronous timer, three instruction cycles are executed before the flags are updated. During these cycles, the processor executes instructions, but the interrupt condition is not readable, and the interrupt routine has not started yet. See Table 2 on page 15 for clock activity during Power-down, Power-save and Idle modes.

68 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 JTAG Interface and On-chip Debug System Features  JTAG (IEEE std. 1149.1 Compliant) Interface  AVR I/O Boundary-scan Capabilities According to the JTAG Standard  Debugger Access to: – All Internal Peripheral Units – AVR Program and Data SRAM – The Internal Register File – Program Counter/Instruction – FPGA/AVR Interface  Extensive On-chip Debug Support for Break Conditions, Including – Break on Change of Program Memory Flow – Single Step Break – Program Memory Breakpoints on Single Address or Address Range – Data Memory Breakpoints on Single Address or Address Range – FPGA Hardware Break – Frame Memory Breakpoint on Single Address  On-chip Debugging Supported by AVR Studio version 4 or above Overview The AVR IEEE std. 1149.1 compliant JTAG interface is used for on-chip debugging. The On-Chip Debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third-party vendors only. Figure 39 shows a block diagram of the JTAG interface and the On-Chip Debug system. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (shift register) between the TDI - input and TDO - output. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register. Of the Data Registers, the ID-Register, Bypass Register, and the AVR I/O Boundary-Scan Chain are used for board-level testing. The Internal Scan Chain and Break-Point Scan Chain are used for On-Chip debugging only. The Test Access Port – TAP The JTAG interface is accessed through four of the AVR ’s pins. In JTAG terminology, these pins constitute the Test Access Port - TAP. These pins are:  TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state machine.  TCK: Test Clock. JTAG operation is synchronous to TCK  TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains)  TDO: Test Data Out. Serial output data from Instruction register or Data Register The IEEE std. 1149.1 also specifies an optional TAP signal; TRST - Test ReSeT - which is not provided. When the JTAGEN bit is unprogrammed, these four TAP pins revert to normal operation. When programmed, the input TAP signals are internally pulled High and the JTAG is enabled for Boundary-Scan. System Designer sets this bit by default. For the On-Chip Debug system, in addition the RESET pin is monitored by the debugger to be able to detect external reset sources. The debugger can also pull the RESET pin Low to reset the whole system, assuming only open collectors on reset line are used in the application.

Figure 39. Block Diagram

70 AT94K Series FPSLIC

Figure 40. TAP Controller State Diagram the rising edge at TCK. The initial state after a Power-On Reset is Test-Logic-Reset. As a definition in this document, the LSB is shifted in and out first for all shift registers.

Rev. 1138F–FPSLI–06/02 Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is  At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register - Shift-IR state. While TMS is Low, shift the 4 bit JTAG instructions into the JTAG instruction register from the TDI input at the rising edge of TCK, while the captured IR-state 0x01 is shifts out on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register.  Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the shift register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.  At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register - Shift-DR state. While TMS is Low, upload the selected Data Register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. At the same time, the parallel inputs to the Data Register captured in the Capture-DR state shifts out on the TDO pin.  Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine. As shown in Figure 40 on page 70, the Run-Test/Idle (1) state need not be entered between selecting JTAG instruction and using Data Registers, and some JTAG instructions may select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state. Note: 1. Independent of the initial state of the TAP Controller, the T est-Logic-Reset state can always be entered by holding TMS High for 5 TCK clock periods. Using the Boundary-scan Chain A complete description of the Boundary-Scan capabilities are given in the section “IEEE 1149.1 (JTAG) Boundary-scan ”on page 73. Using the On-chip Debug System As shown in Figure 39, the hardware support for On-Chip Debugging consists mainly of  A scan chain on the interface between the internal AVR CPU and the internal peripheral units  A breakpoint unit  A communication interface between the CPU and JTAG system  A scan chain on the interface between the internal AVR CPU and the FPGA  A scan chain on the interface between the internal Program/Data SRAM and the FPGA All read or modify/write operations needed for implementing the Debugger are done by apply- ing AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O memory mapped location which is part of the communication interface between the CPU and the JTAG system.

72 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 The Breakpoint Unit implements Break on Change of Program Flow, Single Step Break, 2 Pro- gram Memory Breakpoints, and 2 combined break points. Together, the 4 break-points can be configured as either:  4 single Program Memory break points  3 Single Program Memory break point + 1 single Data Memory break point  2 single Program Memory break points + 2 single Data Memory break points  2 single Program Memory break points + 1 Program Memory break point with mask (‘range break point’)  2 single Program Memory break points + 1 Data Memory break point with mask ( ‘range break point’)  1 single Frame Memory break point is available parallel to all the above combinations A list of the On-Chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions”. Atmel supports the On-Chip Debug system with the AVR Studio front-end software for PCs. The details on hardware implementation and JTAG instructions are there- fore irrelevant for the user of the On-Chip Debug system. The JTAG Enable bit must be set (one) in the System Control Register to enable the JTAG Test Access Port. In addition, the On-chip Debug Enable bit must be set (one). The AVR Studio enables the user to fully control execution of programs on an AVR device with On-Chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simula- tor. AVR Studio supports source level execution of Assembly programs assembled with Atmel Corporation’s AVR Assembler and C programs compiled with third-party vendors ’compilers. AVR Studio runs under Microsoft Windows ® 95/98/2000 and Microsoft WindowsNT ®. All necessary execution commands are available in AVR Studio, both on source level and on disassembly level. The user can execute the program, single step through the code either by tracing into or stepping over functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execution, and reset the execution target. In addition, the user can have up to 2 data memory breakpoints, alternatively combined as a mask (range) break-point.

within ATMEL and to selected third-party vendors only. Table 16 lists the instruction opcode. to drive values at their output pins, and observe the input values received from other devices. Printed Circuits Boards by using the 4 TAP signals only. Table 16. JTAG Instruction and Code

74 AT94K Series FPSLIC

instruction with appropriate setting of the Reset Data Register. The EXTEST instruction is used for sampling external pins and loading output pins with data. shot of the AVR’s external pins during normal operation of the part. cleared to enable the JTAG Test Access Port. than the internal chip frequency is possible. The chip clock is not required to run. when the other devices are to be tested. Figure 41 shows the structure of the Device Identification register. Figure 41. The format of the Device Identification Register

devices is listed in Table 18. The manufacturer ID for ATMEL is 0x01F (11 bits). place immediately, see Figure 42. Figure 42. Reset Register See “Boundary-scan Chain ”on page 76 for a complete description. As a definition in this data sheet, the LSB is shifted in and out first for all shift registers. Table 18. JTAG Part Number

76 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 EXTEST; $0 Mandatory JTAG instruction for selecting the Boundary-Scan Chain as Data Register for test- ing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip connections, the interface between the analog and the digital logic is in the scan chain. The contents of the latched outputs of the Boundary-Scan chain are driven out as soon as the JTAG IR-register is loaded by the EXTEST instruction. The active states are:  Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain.  Shift-DR: The Internal Scan Chain is shifted by the TCK input.  Update-DR: Data from the scan chain is applied to output pins. IDCODE; $1 Optional JTAG instruction selecting the 32-bit ID register as Data Register. The ID register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after power-up. The active states are:  Capture-DR: Data in the IDCODE register is sampled into the Boundary-Scan Chain.  Shift-DR: The IDCODE scan chain is shifted by the TCK input. SAMPLE_PRELOAD; $2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-Scan Chain is selected as Data Register. The active states are:  Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain.  Shift-DR: The Boundary-Scan Chain is shifted by the TCK input.  Update-DR: Data from the Boundary-Scan chain is applied to the output latches. However, the output latches are not connected to the pins. AVR_RESET; $C The AVR specific public JTAG instruction for forcing the AVR device into the Reset Mode or releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data Register. Note that the reset will be active as long as there is a logic “1”in the Reset Chain. The output from this chain is not latched. The active state is:  Shift-DR: The Reset Register is shifted by the TCK input. BYPASS; $F Mandatory JTAG instruction selecting the Bypass Register for Data Register. The active states are:  Capture-DR: Loads a logic “0”into the Bypass Register.  Shift-DR: The Bypass Register cell between TDI and TDO is shifted. Boundary-scan Chain The Boundary-Scan chain has the capability of driving and observing the logic levels on the AVR’s digital I/O pins. Scanning the Digital Port Pins Figure 43 shows the boundary-scan cell for bi-directional port pins with pull-up function. The cell consists of a standard boundary-scan cell for the pull-up function, and a bi-directional pin cell that combines the three signals Output Control (OC), Output Data (OD), and Input Data (ID), into only a two-stage shift register.

Figure 43. Boundary-scan Cell For Bi-directional Port Pin with Pull-up Function

1 DQ DQ

78 AT94K Series FPSLIC

Figure 44 shows a simple digital Port Pin as described in the section “I/O Ports”on page 147. The Boundary-Scan details from Figure 43 replaces the dashed box in Figure 44. Figure 44. General Port Pin Schematic Diagram

scan chain read the actual pin value. or the device is in general reset (Resetn or power-on) or configuration download. Figure 45. Observe-only Cell

80 AT94K Series FPSLIC

Output ” bits (active High) in the scan chain are supported by general boundary-scan cells. Figure 46. Boundary-scan Cells for 2-wire Serial Scanning the Clock Pins Figure 47 shows how each oscillator with external connection is supported in the scan chain. oscillator does not have external connections. Figure 47. Boundary-scan Cells for Oscillators and Clock Options

the internal oscillator and the JTAG TCK clock. connecting the oscillator pins from the scan path if not provided. (“Enable Clock”bit is active Low). FF1, and “Pull-up – PXn”corresponds to FF2. Table 19. AVR I/O Boundary Scan – JTAG Instructions $0/$2

82 AT94K Series FPSLIC

Notes: 1. Observe-only scan cell.

1. AVR Reset is High (one) if AVRResetn activated (Low) and enabled or the device is in

general reset (Resetn or power-on) or configuration download. Table 20. Bit EXTEST and SAMPLE_PRELOAD Data Out/In - PXn Defines value driven if enabled . Capture-DR grabs signal on pad. AVR if the output drive is enabled. Enable Output - PXn 1 = output drive enabled . Pull-up - PXn 1 = pull-up disabled . Data Out - TXn Defines value driven if enabled . Capture-DR grabs signal on pad. Enable Output - TXn 1 = output drive enabled . Pull-up - TXn 1 = pull-up disabled . grabs clock enable from the AVR.

84 AT94K Series FPSLIC

grabs clock enable from the AVR. AVR Reset Internal, observe only.

T/C. Timer/Counter2 can optionally be asynchronously clocked from an external oscillator. ing selection from the same 10-bit prescaling timer. Timer/Counter2 has its own prescaler. clock time-base or as a counter with an external pin connection which triggers the counting. Figure 48. Prescaler for Timer/Counter0 and 1 operate with a predictable prescaler.

86 AT94K Series FPSLIC

Figure 49. Timer/Counter2 Prescaler These bits are reserved bits in the FPSLIC and are always read as zero. Timer/Counter2”on page 94 for a detailed description of asynchronous operation. and a reset of this prescaler will affect both timers. This bit will always be read as zero.

88 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 The 8-bit Timer/Counter0 can select the clock source from CK, prescaled CK, or an external pin. The 8-bit Timer/Counter2 can select the clock source from CK, prescaled CK or external TOSC1. Both Timers/Counters can be stopped as described in section “Timer/Counter0 Control Regis- ter – TCCR0”on page 88 and “Timer/Counter2 Control Register – TCCR2”on page 88. The various status flags (overflow and compare match) are found in the Timer/Counter Inter- rupt Flag Register (TIFR). Control signals are found in the Timer/Counter Control Register (TCCR0 and TCCR2). The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask Register – TIMSK. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscil- lator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counters feature both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact-timing functions with infrequent actions. Timer/Counters 0 and 2 can also be used as 8-bit Pulse Width Modulators (PWM). In this mode, the Timer/Counter and the output compare register serve as a glitch-free, stand-alone PWM with centered pulses. See “Timer/Counter 0 and 2 in PWM Mode ” on page 91 for a detailed description on this function. Timer/Counter0 Control Register – TCCR0 Timer/Counter2 Control Register – TCCR2  Bit 7 - FOC0/FOC2: Force Output Compare Writing a logic 1 to this bit forces a change in the compare match output pin PE1 (Timer/Counter0) and PE3 (Timer/Counter2) according to the values already set in COMn1 and COMn0. If the COMn1 and COMn0 bits are written in the same cycle as FOC0/FOC2, the new settings will not take effect until next compare match or Forced Output Compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COMn1 and COMn0 happens as if a Compare Match had occurred, but no interrupt is generated and the Timer/Counters will not be cleared even if CTC0/CTC2 is set. The FOC0/FOC2 bits will always be read as zero. The setting of the FOC0/FOC2 bits has no effect in PWM mode.  Bit 6 - PWM0/PWM2: Pulse Width Modulator Enable When set (one) this bit enables PWM mode for Timer/Counter0 or Timer/Counter2. This mode is described on page 91. B i t 76543210 $33 ($53) FOC0 PWM0 COM01 COM00 CTC0 CS02 CS01 CS00 TCCR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $27 ($47) FOC2 PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 TCCR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

Timer/Counter wraps when it reaches $FF. Refer to page 91 for a detailed description. Timer/Counter2, see Table 22 and Table 23. Table 21. Compare Output Mode Select 01 T o g g l e s t h e O C n (2) output line. 1 0 Clears the OCn (2) output line (to zero). 11 S e t s t h e O C n (2) output line (to one). Table 22. Clock 0 Prescale Select

001 C K

010 C K / 8

011 C K / 6 4

100 C K / 2 5 6

90 AT94K Series FPSLIC

scaled directly from the CK oscillator clock for Timer/Counter0 and PCK2 for Timer/Counter2. These 8-bit registers contain the value of the Timer/Counters. counting in the timer clock cycle following the write operation. Table 23. Clock 2 Prescale Select

001 P C K 2

010 P C K 2 / 8

011 P C K 2 / 3 2

100 P C K 2 / 6 4

101 P C K 2 / 1 2 8

110 P C K 2 / 2 5 6

Output Compare Register to the same value does not generate a compare match. $FF or it acts as an up/down counter. the PE1(OC0/PWM0) or PE3(OC2/PWM2) pin. speed of the up/down counting mode. Control Registers – TCCR0 or TCCR2 respectively. of the COMn1/COMn0 bits in the Timer/Counter Control Registers TCCR0 or TCCR2. nized OCR0 or OCR2 write. See Figure 52 and Figure 53 for examples. Table 24. Compare Mode Select in PWM Mode 0 1 1 Cleared on compare match, down-counting.

92 AT94K Series FPSLIC

Figure 52. Effects of Unsynchronized OCR Latching in Up/Down Mode Figure 53. Effects of Unsynchronized OCR Latching in Overflow Mode. written value always will read out of OCR0 and OCR2. next compare match according to the settings of COMn1/COMn0. This is shown in Table 25. only when the Output Compare Register contains $FF.

These bits are reserved bits in the FPSLIC and are always read as zero. changed the contents of TCNT2, OCR2 and TCCR2 might get corrupted. set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. Table 25. PWM Outputs OCRn = $00 or $FF

94 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 The mechanisms for reading TCNT2, OCR2 and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary stor- age register is read. Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken:  When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2 and TCCR2 might get corrupted. A safe procedure for switching the clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2 and TCCR2. 4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. 5. Enable interrupts, if needed.  The oscillator is optimized for use with a 32.768 kHz watch crystal. An external clock signal applied to this pin goes through the same amplifier having a bandwidth of 256 kHz. The external clock signal should therefore be in the interval 0H z – 1 MHz. The frequency of the clock signal applied to the TOSC1 pin must be lower than one fourth of the CPU main clock frequency.  When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that, e.g., writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the destination register has taken place, an Asynchronous Status Register – ASSR has been implemented.  When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the written register has been updated if Timer/Counter2 is used to wake-up the device. Otherwise, the MCU will go to sleep before the changes have had any effect. This is extremely important if the Output Compare2 interrupt is used to wake-up the device; Output compare is disabled during write to OCR2 or TCNT2. If the write cycle is not finished (i.e., the MCU enters Sleep mode before the OCR2UB bit returns to zero), the device will never get a compare match and the MCU will not wake-up.  If Timer/Counter2 is used to wake-up the device from Power-save mode, precautions must be taken if the user wants to re-enter Power-save mode: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and reentering Power-save mode is less than one TOSC1 cycle, the interrupt will not occur and the device will fail to wake up. If the user is in doubt whether the time before re-entering power-save is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2, TCNT2, or OCR2. 2. Wait until the corresponding Update Busy flag in ASSR returns to zero. 3. Enter Power-save mode.  When asynchronous operation is selected, the 32.768 kHz oscillator for Timer/Counter2 is always running, except in Power-down mode. After a power-up reset or wake-up from power-down, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. Therefore, the contents of all Timer2 registers must be considered lost after a wake-up from power-down, due to the unstable clock signal. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from power-down.  Description of wake-up from Power-save mode when the timer is clocked asynchronously. When the interrupt condition is met, the wake-up process is started on the following cycle

is not synchronized to the processor clock. Timer/Counter1 Figure 54 shows the block diagram for Timer/Counter1. Figure 54. Timer/Counter1 Block Diagram

16 BIT COMPARATOR

96 AT94K Series FPSLIC

tings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register – TIMSK. time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. Figure 55. ICP Pin Schematic Diagram monitored over four samples, and all four must be equal to activate the capture flag.

must be set (one) to control an output pin. The control configuration is shown in Table 26. be read as zero. The setting of the FOC1A bit has no effect in PWM mode. Table 26. Compare 1 Mode Select (1)

98 AT94K Series FPSLIC

ister – ICR1 – on the rising edge of the input capture pin – PE7(ICP). vents unnecessary register copies during normal use of the PE7 port. This bit is reserved in the FPSLIC and will always read zero. wraps when it reaches the TOP value. Refer to page 101 for a detailed description. Table 27. PWM Mode Select

The Clock Select1 bits 2,1 and 0 define the prescaling source of Timer/Counter1. an output. This feature can give the user SW control of the counting. abled during access from the main program and interrupt routines. 16-bit register write operation. Table 28. Clock 1 Prescale Select

100 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 TCNT1 Timer/Counter1 Read When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU and the data of the high byte TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU receives the data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read operation. The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock-cycle after it is preset with the written value. Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BL The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Con- trol and Status register. A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the com- pare event. Since the Output Compare Registers – OCR1A and OCR1B – are 16-bit registers, a tempo- rary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is tempo- rarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and interrupt routines. B i t 1 51 41 31 21 11 09 8 $2B ($4B) MSB OCR1AH $2A ($4A) LSB OCR1AL 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 00000000 B i t 1 51 41 31 21 11 09 8 $29 ($49) MSB OCR1BH $28 ($48) LSB OCR1BL 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 00000000

Rev. 1138F–FPSLI–06/02 Timer/Counter1 Input Capture Register – ICR1H AND ICR1L The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting – ICES1) of the signal at the input capture pin – PE7(ICP) – is detected, the current value of the Timer/Counter1 Register – TCNT1 is transferred to the Input Capture Register – ICR1. In the same cycle, the input capture flag – ICF1 – is set (one). Since the Input Capture Register – ICR1 – is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main pro- gram and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and interrupt routine. Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1A – OCR1A and the Output Compare Register1B – OCR1B, form a dual 8-, 9- or 10-bit, free-run- ning, glitch-free and phase correct PWM with outputs on the PD6(OC1A) and PE5(OC1B) pins. In this mode the Timer/Counter1 acts as an up/down counter, counting up from $0000 to TOP (see Table 29), where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the contents of the 8, 9 or 10 least significant bits (depends of the resolution) of OCR1A or OCR1B, the PD6(OC1A)/PE5(OC1B) pins are set or cleared according to the settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register TCCR1A. Refer to Table 30 for details. Alternatively, the Timer/Counter1 can be configured to a PWM that operates at twice the speed as in the mode described above. Then the Timer/Counter1 and the Output Compare Register1A – OCR1A and the Output Compare Register1B – OCR1B, form a dual 8-, 9- or 10- bit, free-running and glitch-free PWM with outputs on the PE6(OC1A) and PE5(OC1B) pins. As shown in Table 29, the PWM operates at either 8-, 9- or 10-bit resolution. Note the unused bits in OCR1A, OCR1B and TCNT1 will automatically be written to zero by the hardware. For example, bit 9 to 15 will be set to zero in OCR1A, OCR1B and TCNT1 if the 9-bit PWM resolu- tion is selected. This makes it possible for the user to perform read-modify-write operations in any of the three resolution modes and the unused bits will be treated as “don’tc a r e”. B i t 1 51 41 31 21 11 09 8 $25 ($45) MSB ICR1H $24 ($44) LSB ICR1L 76543210 R e a d / W r i t e RRRRRRRR RRRRRRRR I n i t i a l V a l u e 00000000 00000000

102 AT94K Series FPSLIC

Table 29. Timer TOP Values and PWM Frequency Table 30. Compare1 Mode Select in PWM Mode

104 AT94K Series FPSLIC

Notes: 1. In overflow PWM mode, this table is only valid for OCR1X = TOP . interrupts are enabled. This also applies to the Timer Output Compare1 flags and interrupts. and executes from the reset vector. lowed when the watchdog is disabled, see Figure 58. Figure 58. Watchdog Timer Table 31. PWM Outputs OCR1X = $0000 or TOP

10 T O P H

11 T O P L

These bits are reserved bits in the FPSLIC and will always read as zero. description of the WDE bit below for a watchdog disable procedure.

1. In the same operation, write a logic 1 to WDTOE and WDE. A logic 1 must be writ-

ten to WDE even though it is set to one before the disable operation starts.

1. Within the next four clock cycles, write a logic 0 to WDE. This disables the

periods are shown in Table 32. reset, the Watchdog Timer may not start counting from zero. Table 32. Watchdog Timer Prescale Select

106 AT94K Series FPSLIC

To be able to use the multiplier, six new instructions are added to the AVR instruction set. use the multiplier for 16-bit arithmetic. equal to -1. Some issues regarding the use of fractional numbers are discussed. A list of all implementations with key performance specifications is given in Table 33. Table 33. Performance Summary

each of the multiply instructions. value with a constant (5) before storing the result in register pair R17:R16. Note the use of the MOVW instruction. This example is valid for all of the multiply instructions. Figure 59. Valid Register Usage This example shows some special cases of the MUL instruction that are valid.

108 AT94K Series FPSLIC

and IIR (Infinite Impulse Response) filters, PID regulators and FFT (Fast Fourier Transform). Fractional Numbers”on page 111. with a 32-bit result (C = A  B). AH denotes the high byte and AL the low byte of the A operand. tions are used for the remaining bytes. carry propagation must still be done for unsigned numbers. Figure 60. 16-bit Multiplication, General Algorithm

unsigned number, or less than 2 15 if the product is to be used as a signed number. we will get the (correct) result C = |A  B|. Figure 61. 16-bit Multiplication, 16-bit Result range -215 ≤ C ≤ 215 - 1 if signed numbers are used. expanded to do 32-bit multiplication with 32-bit result.

110 AT94K Series FPSLIC

Figure 62. 16-bit Multiplication, 32-bit Result stored in the register pair R17:R16. In this example, the 16-bit result will not be correct.

Figure 63. 16-bit Multiplication, 32-bit Accumulated Result than 2, the result will not be correct. the range [-1, 1> may be represented using this format. -0.609375 (fractional number).

112 AT94K Series FPSLIC

Yes, 1.8125 is higher than or equal to 1. Yes, 1.625 is higher than or equal to 1. Yes, 1.25 is higher than or equal to 1. Yes, 1 is higher than or equal to 1. Table 34. Comparison of Integer and Fractional Formats

Rev. 1138F–FPSLI–06/02 To convert a negative fractional number, first add 2 to the number and then use the same algorithm as already shown. 16-bit fractional numbers use a format similar to that of 8-bit fractional numbers; the high 8 bits have the same format as the 8-bit format. The low 8 bits are only an increase of accuracy of the 8-bit format; while the 8-bit format has an accuracy of ± 2 -8, the16-bit format has an accu- racy of ± 2-16. Then again, the 32-bit fractional numbers are an increase of accuracy to the 16-bit fractional numbers. Note the important difference between integers and fractional num- bers when extra byte(s) are used to store the number: while the accuracy of the numbers is increased when fractional numbers are used, the range of numbers that may be represented is extended when integers are used. As mentioned earlier, using signed fractional numbers in the range [-1, 1> has one main advantage to integers: when multiplying two numbers in the range [-1, 1>, the result will be in the range [-1, 1], and an approximation (the highest byte(s)) of the result may be stored in the same number of bytes as the factors, with one exception: when both factors are -1, the prod- uct should be 1, but since the number 1 cannot be represented using this number format, the FMULS instruction will instead place the number -1 in R1:R0. The user should therefore assure that at least one of the operands is not -1 when using the FMULS instruction. The 16-bit x 16-bit fractional multiply also has this restriction. Example 5 – Basic Usage 8-bit x 8-bit = 16-bit Signed Fractional Multiply This example shows an assembly code that reads the port E input value and multiplies this value with a fractional constant (-0.625) before storing the result in register pair R17:R16. in r16,PINE ; Read pin values ldi r17,$B0 ; Load -0.625 into r17 fmuls r16,r17 ; r1:r0 = r17 * r16 movw r17:r16,r1:r0; Move the result to the r17:r16 ; register pair Note that the usage of the FMULS (and FMUL) instructions is very similar to the usage of the MULS and MUL instructions. Example 6 – Multiply- accumulate Operation The example below uses data from the ADC. The ADC should be configured so that the for- mat of the ADC result is compatible with the fractional two ’s complement format. For the ATmega83/163, this means that the ADLAR bit in the ADMUX I/O register is set and a differ- ential channel is used. The ADC result is normalized to one. ldi r23,$62 ; Load highbyte of ; fraction 0.771484375 ldi r22,$C0 ; Load lowbyte of ; fraction 0.771484375 in r20,ADCL ; Get lowbyte of ADC conversion in r21,ADCH ; Get highbyte of ADC conversion callfmac16x16_32 ;Call routine for signed fractional ; multiply accumulate The registers R19:R18:R17:R16 will be incremented with the result of the multiplication of 0.771484375 with the ADC conversion result. In this example, the ADC result is treated as a signed fraction number. We could also treat it as a signed integer and call it “mac16x16_32 ” instead of “fmac16x16_32”. In this case, the 0.771484375 should be replaced with an integer.

114 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 Implementations mul16x16_16 Description Multiply of two 16-bit numbers with a 16-bit result. Usage R17:R16 = R23:R22  R21:R20 Statistics Cycles: 9 + ret Words: 6 + ret Register usage: R0, R1 and R16 to R23 (8 registers) (1) Note: 1. Full orthogonality, i.e., any register pair can be used as long as the result and the two oper- ands do not share register pairs. The routine is non-destructive to the operands. mul16x16_16: mul r22, r20 ; al * bl movw r17:r16, r1:r0 mul r23, r20 ; ah * bl add r17, r0 mul r21, r22 ; bh * al add r17, r0 ret mul16x16_32 Description Unsigned multiply of two 16-bit numbers with a 32-bit result. Usage R19:R18:R17:R16 = R23:R22  R21:R20 Statistics Cycles: 17 + ret Words: 13 + ret Register usage: R0 to R2 and R16 to R23 (11 registers) (1) Note: 1. Full orthogonality, i.e., any register pair can be used as long as the result and the two oper- ands do not share register pairs. The routine is non-destructive to the operands. mul16x16_32: clr r2 mul r23, r21 ; ah * bh movw r19:r18, r1:r0 mul r22, r20 ; al * bl movw r17:r16, r1:r0 mul r23, r20 ; ah * bl add r17, r0 adc r18, r1 adc r19, r2 mul r21, r22 ; bh * al add r17, r0 adc r18, r1 adc r19, r2 ret

Rev. 1138F–FPSLI–06/02 muls16x16_32 Description Signed multiply of two 16-bit numbers with a 32-bit result. Usage R19:R18:R17:R16 = R23:R22  R21:R20 Statistics Cycles: 19 + ret Words: 15 + ret Register usage: R0 to R2 and R16 to R23 (11 registers) (1) Note: 1. The routine is non-destructive to the operands. muls16x16_32: clr r2 muls r23, r21 ; (signed)ah * (signed)bh movw r19:r18, r1:r0 mul r22, r20 ; al * bl movw r17:r16, r1:r0 mulsu r23, r20 ; (signed)ah * bl sbc r19, r2 ; Sign extend add r17, r0 adc r18, r1 adc r19, r2 mulsu r21, r22 ; (signed)bh * al sbc r19, r2 ; Sign Extend add r17, r0 adc r18, r1 adc r19, r2 ret mac16x16_32 Description Signed multiply-accumulate of two 16-bit numbers with a 32-bit result. Usage R19:R18:R17:R16 += R23:R22  R21:R20 Statistics Cycles: 23 + ret Words: 19 + ret Register usage: R0 to R2 and R16 to R23 (11 registers) mac16x16_32: ; Register Usage Optimized clr r2 muls r23, r21 ; (signed)ah * (signed)bh add r18, r0 adc r19, r1 mul r22, r20 ; al * bl add r16, r0 adc r17, r1 adc r18, r2 adc r19, r2

116 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 mulsu r23, r20 ; (signed)ah * bl sbc r19, r2 add r17, r0 adc r18, r1 adc r19, r2 mulsu r21, r22 ; (signed)bh * al sbc r19, r2 ; Sign extend add r17, r0 adc r18, r1 adc r19, r2 ret mac16x16_32_method_B: ; uses two temporary registers (r4,r5), Speed / Size Optimized ; but reduces cycles/words by 1 clr r2 muls r23, r21 ; (signed)ah * (signed)bh movw r5:r4,r1:r0 mul r22, r20 ; al * bl add r16, r0 adc r17, r1 adc r18, r4 adc r19, r5 mulsu r23, r20 ; (signed)ah * bl sbc r19, r2 ; Sign extend add r17, r0 adc r18, r1 adc r19, r2 mulsu r21, r22 ; (signed)bh * al sbc r19, r2 ; Sign extend add r17, r0 adc r18, r1 adc r19, r2 ret

Rev. 1138F–FPSLI–06/02 fmuls16x16_32 Description Signed fractional multiply of two 16-bit numbers with a 32-bit result. Usage Statistics Cycles: 20 + ret Words: 16 + ret Register usage: R0 to R2 and R16 to R23 (11 registers) (1) Note: 1. The routine is non-destructive to the operands. fmuls16x16_32: clr r2 fmuls r23, r21 ; ( (signed)ah * (signed)bh ) << 1 movw r19:r18, r1:r0 fmul r22, r20 ; ( al * bl ) << 1 adc r18, r2 movw r17:r16, r1:r0 fmulsu r23, r20 ; ( (signed)ah * bl ) << 1 sbc r19, r2 ; Sign extend add r17, r0 adc r18, r1 adc r19, r2 fmulsu r21, r22 ; ( (signed)bh * al ) << 1 sbc r19, r2 ; Sign extend add r17, r0 adc r18, r1 adc r19, r2 ret fmac16x16_32 Description Signed fractional multiply-accumulate of two 16-bit numbers with a 32-bit result. Usage Statistics Cycles: 25 + ret Words: 21 + ret Register usage: R0 to R2 and R16 to R23 (11 registers) fmac16x16_32: ; Register usage optimized clr r2 fmuls r23, r21 ; ( (signed)ah * (signed)bh ) << 1 add r18, r0 adc r19, r1 fmul r22, r20 ; ( al * bl ) << 1 adc r18, r2 adc r19, r2 add r16, r0

118 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 adc r17, r1 adc r18, r2 adc r19, r2 fmulsu r23, r20 ; ( (signed)ah * bl ) << 1 sbc r19, r2 add r17, r0 adc r18, r1 adc r19, r2 fmulsu r21, r22 ; ( (signed)bh * al ) << 1 sbc r19, r2 add r17, r0 adc r18, r1 adc r19, r2 ret fmac16x16_32_method_B ; uses two temporary registers (r4,r5), speed/Size optimized ; but reduces cycles/words by 2 clr r2 fmuls r23, r21 ; ( (signed)ah * (signed)bh ) << 1 movw r5:r4,r1:r0 fmul r22, r20 ; ( al * bl ) << 1 adc r4, r2 add r16, r0 adc r17, r1 adc r18, r4 adc r19, r5 fmulsu r23, r20 ; ( (signed)ah * bl ) << 1 sbc r19, r2 add r17, r0 adc r18, r1 adc r19, r2 fmulsu r21, r22 ; ( (signed)bh * al ) << 1 sbc r19, r2 add r17, r0 adc r18, r1 adc r19, r2 ret Comment on Implementations All 16-bit x 16-bit = 32-bit functions implemented here start by clearing the R2 register, which is just used as a “dummy” register with the “a d dw i t hc a r r y”(ADC) and “subtract with carry ” (SBC) operations. These operations do not alter the contents of the R2 register. If the R2 reg- ister is not used elsewhere in the code, it is not necessary to clear the R2 register each time these functions are called, but only once prior to the first call to one of the functions.

and the functionality is described in general for the two UARTs. Figure 64. UART Transmitter(1)

120 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Reg- ister, UDRn. Data is transferred from UDRn to the Transmit shift register when:  A new character has been written to UDRn after the stop bit from the previous character has been shifted out. The shift register is loaded immediately.  A new character has been written to UDRn before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDRn to the shift register. At this time the UDREn (UART Data Register Empty) bit in the UART Control and Status Register, UCSRnA, is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the data is transferred from UDRn to the 10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If a 9-bit data word is selected (the CHR9n bit in the UART Control and Status Register, UCSRnB is set), the TXB8 bit in UCSRnB is transferred to bit 9 in the Transmit shift register. On the Baud-rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXDn pin. Then follows the data, LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has been written to the UDRn during the transmission. During loading, UDREn is set. If there is no new data in the UDRn register to send when the stop bit is shifted out, the UDREn flag will remain set until UDRn is written again. When no new data has been written, and the stop bit has been present on TXDn for one bit length, the TX Complete flag, TXCn, in UCSRnA is set. The TXENn bit in UCSRnB enables the UART transmitter when set (one). When this bit is cleared (zero), the PE0 (UART0) or PE2 (UART1) pin can be used for general I/O. When TXENn is set, the UART Transmitter will be connected to PE0 (UART0) or PE2 (UART1), which is forced to be an output pin regardless of the setting of the DDE0 bit in DDRE (UART0) or DDE2 in DDRE (UART1).

Data Reception Figure 65 shows a block diagram of the UART Receiver. Figure 65. UART Receiver(1) rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition.

122 AT94K Series FPSLIC

shift register as they are sampled. Sampling of an incoming character is shown in Figure 66. Note that the description above is not valid when the UART transmission speed is doubled. See “Double Speed Transmission ”on page 128 for a detailed description. Figure 66. Sampling Received Data sion”on page 128 for a detailed description. should always check the FEn bit to detect Framing Errors. register when data is transferred to UDRn. baud-rate is High or CPU load is High. (UART0) or PORTE3 (UART1) bit can still be used to control the pull-up resistor on the pin.

Rev. 1138F–FPSLI–06/02 Multi-processor Communication Mode The Multi-processor Communication Mode enables several Slave MCUs to receive data from a Master MCU. This is done by first decoding an address byte to find out which MCU has been addressed. If a particular Slave MCU has been addressed, it will receive the following data bytes as normal, while the other Slave MCUs will ignore the data bytes until another address byte is received. For an MCU to act as a Master MCU, it should enter 9-bit transmission mode (CHR9n in UCS- RnB set). The 9-bit must be one to indicate that an address byte is being transmitted, and zero to indicate that a data byte is being transmitted. For the Slave MCUs, the mechanism appears slightly different for 8-bit and 9-bit Reception mode. In 8-bit Reception mode (CHR9n in UCSRnB cleared), the stop bit is one for an address byte and zero for a data byte. In 9-bit Reception mode (CHR9n in UCSRnB set), the 9-bit is one for an address byte and zero for a data byte, whereas the stop bit is always High. The following procedure should be used to exchange data in Multi-processor Communication mode: 1. All Slave MCUs are in Multi-processor Communication Mode (MPCMn in UCSRnA is set). 2. The Master MCU sends an address byte, and all Slaves receive and read this byte. In the Slave MCUs, the RXCn flag in UCSRnA will be set as normal. 3. Each Slave MCU reads the UDRn register and determines if it has been selected. If so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte. 4. For each received data byte, the receiving MCU will set the receive complete flag (RXCn in UCSRnA. In 8-bit mode, the receiving MCU will also generate a framing error (FEn in UCSRnA set), since the stop bit is zero. The other Slave MCUs, which still have the MPCMn bit set, will ignore the data byte. In this case, the UDRn register and the RXCn, FEn, or flags will not be affected. 5. After the last byte has been transferred, the process repeats from step 2. UART Control UART0 I/O Data Register – UDR0 UART1 I/O Data Register – UDR1 The UDRn register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDRn, the UART Receive Data register is read. B i t 76543210 $0C ($2C) MSB LSB UDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $03 ($23) MSB LSB UDR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000

124 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 UART0 Control and Status Registers – UCSR0A UART1 Control and Status Registers – UCSR1A  Bit 7 - RXC0/RXC1: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDRn. The bit is set regardless of any detected framing errors. When the RXCIEn bit in UCS- RnB is set, the UART Receive Complete interrupt will be executed when RXCn is set (one). RXCn is cleared by reading UDRn. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDRn in order to clear RXCn, otherwise a new interrupt will occur once the interrupt routine terminates.  Bit 6 - TXC0/TXC1: UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift reg- ister has been shifted out and no new data has been written to UDRn. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIEn bit in UCSRnB is set, setting of TXCn causes the UART Transmit Complete interrupt to be executed. TXCn is cleared by the hardware when executing the corresponding interrupt handling vector. Alternatively, the TXCn bit is cleared (zero) by writing a logic 1 to the bit.  Bit 5 - UDRE0/UDRE1: UART Data Register Empty This bit is set (one) when a character written to UDRn is transferred to the Transmit shift regis- ter. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIEn bit in UCSRnB is set, the UART Transmit Complete interrupt will be exe- cuted as long as UDREn is set and the global interrupt enable bit in SREG is set. UDREn is cleared by writing UDRn. When interrupt-driven data transmittal is used, the UART Data Reg- ister Empty Interrupt routine must write UDRn in order to clear UDREn, otherwise a new interrupt will occur once the interrupt routine terminates. UDREn is set (one) during reset to indicate that the transmitter is ready.  B i t4-F E 0 / F E 1 :F r a m i n gE r r o r This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incoming character is zero. The FEn bit is cleared when the stop bit of received data is one. B i t 76543210 $0B ($2B) RXC0 TXC0 UDRE0 FE0 OR0 - U2X0 MPCM0 UCSR0A Read/Write R R/W R R R R R/W R/W I n i t i a l V a l u e 00100000 B i t 76543210 $02 ($22) RXC1 TXC1 UDRE1 FE1 OR1 - U2X1 MPCM1 UCSR1A Read/Write R R/W R R R R R/W R/W I n i t i a l V a l u e 00100000

Rev. 1138F–FPSLI–06/02  Bit 3 - OR0/OR1: OverRun This bit is set if an Overrun condition is detected, i.e., when a character already present in the UDRn register is not read before the next character has been shifted into the Receiver Shift register. The ORn bit is buffered, which means that it will be set once the valid data still in UDRn is read. The ORn bit is cleared (zero) when data is received and transferred to UDRn.  Bit 2 - Res: Reserved Bit This bit is reserved in the AT94K and will always read as zero.  Bits 1 - U2X0/U2X1: Double the UART Transmission Speed When this bit is set (one) the UART speed will be doubled. This means that a bit will be trans- mitted/received in eight CPU clock periods instead of 16 CPU clock periods. For a detailed description, see “Double Speed Transmission ”on page 128”.  Bit 0 - MPCM0/MPCM1: Multi-processor Communication Mode This bit is used to enter Multi-processor Communication Mode. The bit is set when the Slave MCU waits for an address byte to be received. When the MCU has been addressed, the MCU switches off the MPCMn bit, and starts data reception. For a detailed description, see “Multi-processor Communication Mode ”on page 123. UART0 Control and Status Registers – UCSR0B UART1 Control and Status Registers – UCSR1B  Bit 7 - RXCIE0/RXCIE1: RX Complete Interrupt Enable When this bit is set (one), a setting of the RXCn bit in UCSRnA will cause the Receive Com- plete interrupt routine to be executed provided that global interrupts are enabled.  Bit 6 - TXCIE0/TXCIE1: TX Complete Interrupt Enable When this bit is set (one), a setting of the TXCn bit in UCSRnA will cause the Transmit Com- plete interrupt routine to be executed provided that global interrupts are enabled.  Bit 5 - UDRIE0/UDREI1: UART Data Register Empty Interrupt Enable When this bit is set (one), a setting of the UDREn bit in UCSRnA will cause the UART Data Register Empty interrupt routine to be executed provided that global interrupts are enabled.  Bit 4 - RXEN0/RXEN1: Receiver Enable This bit enables the UART receiver when set (one). When the receiver is disabled, the TXCn, ORn and FEn status flags cannot become set. If these flags are set, turning off RXENn does not cause them to be cleared. B i t 76543210 $0A ($2A) RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 CHR90 RXB80 TXB80 UCSR0B Read/Write R/W R/W R/W R/W R/W R/W R R/W I n i t i a l V a l u e 00000010 B i t 76543210 $01 ($21) RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 CHR91 RXB81 TXB81 UCSR1B Read/Write R/W R/W R/W R/W R/W R/W R R/W I n i t i a l V a l u e 00000010

126 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02  Bit 3 - TXEN0/TXEN1: Transmitter Enable This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDRn has been completely transmitted.  Bit 2 - CHR90/CHR91: 9-bit Characters When this bit is set (one) transmitted and received characters are 9-bit long plus start and stop bits. The 9-bit is read and written by using the RXB8n and TXB8n bits in UCSRnB, respec- tively. The 9th data bit can be used as an extra stop bit or a parity bit.  Bit 1 - RXB80/RXB81: Receive Data Bit 8 When CHR9n is set (one), RXB8n is the 9th data bit of the received character.  Bit 0 - TXB80/TXB81: Transmit Data Bit 8 When CHR9n is set (one), TXB8n is the 9th data bit in the character to be transmitted. Baud-rate Generator The baud-rate generator is a frequency divider which generates baud-rates according to the following equation (1):  BAUD = Baud-rate  fCK = Crystal Clock Frequency  UBR = Contents of the UBRRHI and UBRRn Registers, (0 - 4095) Note: 1. This equation is not valid when the UART transmission speed is doubled. See “Double Speed Transmission”on page 128 for a detailed description. For standard crystal frequencies, the most commonly used baud-rates can be generated by using the UBR settings in Table 35. UBR values which yield an actual baud-rate differing less than 2% from the target baud-rate, are bold in the table. However, using baud-rates that have more than 1% error is not recommended. High error ratings give less noise resistance. BAUD fCK

Table 35. UBR Settings at Various Crystal Frequencies the 4 most significant bits of the UART0 baud register.

128 AT94K Series FPSLIC

UBRRn stores the 8 least significant bits of the UART baud-rate register. register as they are sampled. Sampling of an incoming character is shown in Figure 67. Figure 67. Sampling Received Data when the Transmission Speed is Doubled Note: 1. This equation is only valid when the UART transmission speed is doubled. Table 36 for the UBR settings at various crystal frequencies in double UART speed mode.

Table 36. UBR Settings at Various Crystal Frequencies in Double UART Speed Mode

130 AT94K Series FPSLIC

nected to them. Various communication configurations can be designed using this bus. Figure 68. 2-wire Serial Bus Configuration Figure 69. 2-wire Serial Bus Timing Diagram The block diagram of the 2-wire Serial Bus interface is shown in Figure 70.

Figure 70. Block diagram of the 2-wire Serial Bus Interface Address Register (TWAR, used in Slave mode).

132 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02  Bits 7..0 - 2-wire Serial Bit-rate Register TWBR selects the division factor for the bit-rate generator. The bit-rate generator is a fre- quency divider which generates the SCL clock frequency in the Master modes according to the following equation:  Bit-rate = SCL frequency  f CK = CPU Clock frequency  TWBR = Contents of the 2-wire Serial Bit Rate Register Both the receiver and the transmitter can stretch the Low period of the SCL line when waiting for user response, thereby reducing the average bit rate. T h e2 - w i r eS e r i a lC o n t r o lR e g i s t e r– TWCR  Bit 7 - TWINT: 2-wire Serial Interrupt Flag This bit is set by the hardware when the 2-wire Serial Interface has finished its current job and expects application software response. If the I-bit in the SREG and TWIE in the TWCR regis- ter are set (one), the MCU will jump to the interrupt vector at address $0046. While the TWINT flag is set, the bus SCL clock line Low period is stretched. The TWINT flag must be cleared by software by writing a logic 1 to it. Note that this flag is not automatically cleared by the hard- ware when executing the interrupt routine. Also note that clearing this flag starts the operation of the 2-wire Serial Interface, so all accesses to the 2-wire Serial Address Register – TWAR, 2-wire Serial Status Register – TWSR, and 2-wire Serial Data Register – TWDR must be com- plete before clearing this flag.  Bit 6 - TWEA: 2-wire Serial Enable Acknowledge Flag TWEA flag controls the generation of the acknowledge pulse. If the TWEA bit is set, the ACK pulse is generated on the 2-wire Serial Bus if the following conditions are met:  The device’s own Slave address has been detected  A general call has been received, while the TWGCE bit in the TWAR is set  A data byte has been received in Master Receiver or Slave Receiver mode By setting the TWEA bit Low the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by setting the TWEA bit again.  Bit 5 - TWSTA: 2-wire Serial Bus START Condition Flag The TWSTA flag is set by the CPU when it desires to become a Master on the 2-wire Serial Bus. The 2-wire serial hardware checks if the bus is available, and generates a Start condition on the bus if the bus is free. However, if the bus is not free, the 2-wire Serial Interface waits until a STOP condition is detected, and then generates a new Start condition to claim the bus Master status. B i t 76543210 $36 ($56) TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE TWCR Read/Write R/W R/W R/W R/W R R/W R R/W I n i t i a l V a l u e 00000000 Bit-rate fCK

Rev. 1138F–FPSLI–06/02  Bit 4 - TWSTO: 2-wire Serial Bus STOP Condition Flag TWSTO is a stop condition flag. In Master mode, setting the TWSTO bit in the control register will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is exe- cuted on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. No stop condition is generated on the bus then, but the 2-wire Serial Interface returns to a well-defined unaddressed Slave mode.  Bit 3 - TWWC: 2-wire Serial Write Collision Flag Set when attempting to write to the 2-wire Serial Data Register – TWDR when TWINT is Low. This flag is updated at each attempt to write the TWDR register.  Bit 2 - TWEN: 2-wire Serial Interface Enable Flag The TWEN bit enables 2-wire serial operation. If this flag is cleared (zero), the bus outputs SDA and SCL are set to high impedance state and the input signals are ignored. The interface is activated by setting this flag (one).  Bit 1 - Res: Reserved Bit This bit is reserved in the AT94K and will always read as zero.  Bit 0 - TWIE: 2-wire Serial Interrupt Enable When this bit is enabled and the I-bit in SREG is set, the 2-wire Serial Interrupt will be acti- vated for as long as the TWINT flag is High. The TWCR is used to control the operation of the 2-wire Serial Interface. It is used to enable the 2-wire Serial Interface, to initiate a Master access, to generate a receiver acknowledge, to generate a stop condition, and control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. The 2-wire Serial Status Register – TWSR  Bits 7..3 - TWS: 2-wire Serial Status These 5 bits reflect the status of the 2-wire Serial Logic and the 2-wire Serial Bus.  Bits 2..0 - Res: Reserved Bits These bits are reserved in the AT94K and will always read as zero TWSR is read only. It contains a status code which reflects the status of the 2-wire Serial Logic and the 2-wire Serial Bus. There are 26 possible status codes. When TWSR contains $F8, no relevant state information is available and no 2-wire Serial Interrupt is requested. A valid status code is available in TWSR one CPU clock cycle after the 2-wire Serial Interrupt flag (TWINT) is set by the hardware and is valid until one CPU clock cycle after TWINT is cleared by software. Table 40 to Table 44 give the status information for the various modes. B i t 76543210 $1D ($3D) TWS7 TWS6 TWS5 TWS4 TWS3 - - - TWSR R e a d / W r i t e RRRRRRRR I n i t i a l V a l u e 11111000

134 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 T h e2 - w i r eS e r i a lD a t aR e g i s t e r– TWDR  Bits 7..0 - TWD: 2-wire Serial Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial Bus. In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the 2-wire Serial Interface is not in the pro- cess of shifting a byte. This occurs when the 2-wire Serial Interrupt flag (TWINT) is set by the hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from Power-down Mode, or Power-save Mode by the 2-wire Serial Interrupt. For example, in the case of the lost bus arbitration, no data is lost in the tran- sition from Master-to-Slave. Receiving the ACK flag is controlled by the 2-wire Serial Logic automatically, the CPU cannot access the ACK bit directly. The 2-wire Serial (Slave) Address Register – TWAR  Bits 7..1 - TWA: 2-wire Serial Slave Address Register These seven bits constitute the Slave address of the 2-wire Serial Bus interface unit.  Bit 0 - TWGCE: 2-wire Serial General Call Recognition Enable Bit This bit enables, if set, the recognition of the General Call given over the 2-wire Serial Bus. The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the 2-wire Serial Interface will respond when programmed as a Slave trans- mitter or receiver, and not needed in the Master modes. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address comparator that looks for the Slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. B i t 76543210 $1F ($3F) MSB LSB TWDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 11111111 B i t 76543210 $1E ($3E) MSB LSB TWGCE TWAR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 11111110

In Figure 71 to Figure 74, circles are used to indicate that the 2-wire Serial Interrupt flag is set. Transfer is suspended until the 2-wire Serial Interrupt flag is cleared by software. the following serial transfer are given in Table 40 to Table 44. cleared by writing a logic 1 to the flag. Table 37. TWCR: Master Transmitter Mode Initialization

136 AT94K Series FPSLIC

Master Receiver mode by loading TWDR with SLA+R. writing a logic 1 to the TWSTO bit in the TWCR register. Master Transmitter mode by loading TWDR with SLA+W. call address ($00), otherwise it will ignore the general call address. Table 38. TWAR: Slave Receiver Mode Initialization Table 39. TWCR: Slave Receiver Mode Initialization

Rev. 1138F–FPSLI–06/02 If the TWEA bit is reset during a transfer, the 2-wire Serial Interface will return a “Not Acknowl- edged”(1) to SDA after the next received data byte. While TWEA is reset, the 2-wire Serial Interface does not respond to its own Slave address. However, the 2-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the 2-wire Serial Interface from the 2- wire serial bus. In ADC Noise Reduction Mode, Power-down Mode and Power-save Mode, the clock system to the 2-wire Serial Interface is turned off. If the Slave Receiver mode is enabled, the interface can still acknowledge a general call and its own Slave address by using the 2-wire serial bus clock as a clock source. The part will then wake up from sleep and the 2-wire Serial Interface will hold the SCL clock Low during the wake up and until the TWCINT flag is cleared. Note that the 2-wire Serial Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep Modes. Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 74). The transfer is initialized as in the Slave Receiver mode. When TWAR and TWCR have been initialized, the 2-wire Serial Interface waits until it is addressed by its own Slave address (or the general call address if enabled) followed by the data direction bit which must be “1” (read) for the 2-wire Serial Interface to operate in the Slave Transmitter mode. After its own Slave address and the read bit have been received, the 2-wire Serial Interrupt flag is set and a valid status code can be read from TWSR. The status code is used to deter- mine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 43. The Slave Transmitter mode may also be entered if arbitration is lost while the 2-wire Serial Interface is in the Master mode (see state $B0). If the TWEA bit is reset during a transfer, the 2-wire Serial Interface will transmit the last byte of the transfer and enter state $C0 or state $C8. the 2-wire Serial Interface is switched to the not addressed Slave mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives all “1”as serial data. While TWEA is reset, the 2-wire Serial Inter- face does not respond to its own Slave address. However, the 2-wire serial bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the 2-wire Serial Interface from the 2- wire serial bus. Miscellaneous States There are two status codes that do not correspond to a defined 2-wire Serial Interface state: Status $F8 and Status $00, see Table 44. Status $F8 indicates that no relevant information is available because the 2-wire Serial Inter- rupt flag (TWINT) is not set yet. This occurs between other states, and when the 2-wire Serial Interface is not involved in a serial transfer. Status $00 indicates that a bus error has occurred during a 2-wire serial transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the TWSTO flag must set and TWINT must be cleared by writing a logic 1 to it. This causes the 2-wire Serial Interface to enter the not addressed Slave mode and to clear the TWSTO flag (no other bits in TWCR are affected). The SDA and SCL lines are released and no STOP con- dition is transmitted.

138 AT94K Series FPSLIC

Table 40. Status Codes for Master Transmitter Mode

Figure 71. Formats and States in the Master Transmitter Mode

140 AT94K Series FPSLIC

Table 41. Status Codes for Master Receiver Mode

Figure 72. Formats and States in the Master Receiver Mode

142 AT94K Series FPSLIC

Table 42. Status Codes for Slave Receiver Mode

Table 42. Status Codes for Slave Receiver Mode (Continued)

144 AT94K Series FPSLIC

Figure 73. Formats and States in the Slave Receiver Mode

Table 43. Status Codes for Slave Transmitter Mode

146 AT94K Series FPSLIC

Figure 74. Formats and States in the Slave Transmitter Mode Table 44. Status Codes for Miscellaneous States

Rev. 1138F–FPSLI–06/02 I/O Ports All AVR ports have true read-modify-write functionality when used as general I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). PortD PortD is an 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for the PortD, one each for the Data Regis- ter – PORTD, $12($32), Data Direction Register – DDRD, $11($31) and the Port D Input Pins – PIND, $10($30). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. The PortD output buffers can sink 20 mA. As inputs, PortD pins that are externally pulled Low will source current if the pull-up resistors are activated. PortD Data Register – PORTD PortD Data Direction Register – DDRD PortD Input Pins Address – PIND The PortD Input Pins address – PIND – is not a register, and this address enables access to the physical value on each PortD pin. When reading PORTD, the PortD Data Latch is read, and when reading PIND, the logical values present on the pins are read. PortD as General Digital I/O PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is con- figured as an input pin. If PDn is set (one) when configured as an input pin the MOS pull-up resistor is activated. To switch the pull-up resistor off the PDn has to be cleared (zero) or the pin has to be configured as an output pin. The port pins are input with pull-up when a reset condition becomes active, even if the clock is not running, see Table 45. B i t 76543210 $12 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 11111111 B i t 76543210 $11 DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I n i t i a l V a l u e 00000000 B i t 76543210 $10 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND R e a d / W r i t e RRRRRRRR Initial Value Pull1 Pull1 Pull1 Pull1 Pull1 Pull1 Pull1 Pull1

148 AT94K Series FPSLIC

Figure 75. PortD Schematic Diagram PortE PortE is an 8-bit bi-directional I/O port with internal pull-up resistors. Data Direction Register are read/write. will source current if the pull-up resistors are activated. All PortE pins have alternate functions as shown in Table 46. Table 45. DDDn

according to the alternate function description. and when reading PINE, the logical values present on the pins are read. Table 46. PortE Pins Alternate Functions Controlled by SCR and AVR I/O Registers

150 AT94K Series FPSLIC

condition becomes active, even if the clock is not running. UART0 forces this pin to be an input, a logic 1 in PORTE0 will turn on the internal pull-up. UART1 pins are enabled by setting bit SCR53 in the FPSLIC System Control Register. UART1 forces this pin to be an input, a logic 1 in PORTE2 will turn on the internal pull-up. up MOS resistors can be activated as described above. ter. INT0 is controlled by SCR48. INT1 is controlled by SCR49. INT2 is controlled by SCR50. INT3 is controlled by SCR51. to PE7 nor as an input as alternate INT3. Table 47. DDEn if external pulled Low (default).

Figure 76. PortE Schematic Diagram (Pin PE0)

152 AT94K Series FPSLIC

Figure 77. PortE Schematic Diagram (Pin PE1)

Figure 78. PortE Schematic Diagram (Pin PE2)

154 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 PortE Schematic Diagram (Pin PE3) PE3 DATA BUS GTS DL SCR(53) RL WL DDE3 Q D R PORTE3 Q D R RESET RESET WD RD RP GTS: Global Tri-State DL: Configuration Download WL: Write PORTE WD: Write DDRE RL: Read PORTE Latch RD: Read DDRE RP: Read PORTE Pin RX1D: UART 1 Receive Data SCR: System Control Register OC2/PMW2: Timer/Counter 2 Output Compare COM2*: Timer/Counter2 Control Bits RX1 RX1D SCR(53) MOS PULL-UP OC2/PMW21 COM20 COM21 MOS PULL-UP RESET DL

Figure 79. PortE Schematic Diagram (Pin PE4)

156 AT94K Series FPSLIC

Figure 80. PortE Schematic Diagram (Pin PE5)

Figure 81. PortE Schematic Diagram (Pin PE6)

158 AT94K Series FPSLIC

Figure 82. PortE Schematic Diagram (Pin PE7)

Rev. 1138F–FPSLI–06/02 AC & DC Timing Characteristics Notes: 1. For AL parts only 2. Minimum voltage of -0.5V DC which may undershoot to -2.0V for pulses of less than 20 ns. Absolute Maximum Ratings*(1) Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. Exposure to Abso- lute Maximum Rating conditions for extended periods of time may affect device reliability. Voltage (2) on Any Pin DC and AC Operating Range – 3.3V Operation AT94K Commercial AT94K Industrial Operating Temperature (Case) 0 °C-7 0 °C- 4 0 °C-8 5 °C VCC Power Supply 3.3V ± 0.3V 3.3V ± 0.3V Input Voltage Level (CMOS) High (VIHC) 70% - 100% V CC 70% - 100% VCC Low (VILC) 0 - 30% V CC 0 - 30% VCC

160 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 Notes: 1. Complete FPSLIC device with static FPGA core (no clock in FPGA active). 2. “Maximum”is the highest value where the pin is guaranteed to be read as Low. 3. “Minimum”is the lowest value where the pin is guaranteed to be read as High. 4. 54 mA for A T94K05 devices. DC Characteristics – 3.3V Operation – Commercial/Industrial (Preliminary) TA =- 4 0°Ct o8 5°C, VCC = 2.7V to 3.6V (unless otherwise noted (1)) Symbol Parameter Conditions Minimum (3) Typical Maximum (2) Units VIH High-level Input Voltage CMOS 0.7 V CC – 5.5 V VIH1 Input High-voltage XTAL 0.7 V CC (3) – VCC +0 . 5 V VIH2 Input High-voltage RESET 0.85 VCC (3) – VCC +0 . 5 V VIL Low-level Input Voltage CMOS -0.3 – 30% VCC V VIL1 Input Low-voltage XTAL -0.5 – 0.1(2) V VOH High-level Output Voltage IOH =4m A VCC =V CC Minimum 2.1 –– V IOH =1 2m A VCC =3 . 0 V 2.1 –– V IOH =1 6m A VCC =3 . 0 V 2.1 –– V VOL Low-level Output Voltage IOL =- 4m A VCC =3 . 0 V –– 0.4 V IOL =- 1 2m A VCC =3 . 0 V –– 0.4 V IOL =- 1 6m A VCC =3 . 0 V –– 0.4 V RRST Reset Pull-up 100 – 500 k Ω RI/O I/O Pin Pull-up 35 – 120 k Ω IIH High-level Input Current VIN =V CC Maximum –– 10 µA With Pull-down, VIN =V CC 75 150 300 µA IIL Low-level Input Current VIN =V SS -10 –– µA With Pull-up, VIN =V SS -300 -150 -75 µA IOZH High-level Tri-state Output Leakage Current Without Pull-down, VIN =V CC Maximum 10 µA With Pull-down, VIN =V CC Maximum 75 150 300 µA IOZL Low-level Tri-state Output Leakage Current Without Pull-up, VIN =V SS -10 µ A With Pull-up, VIN =V SS -300 -150 -75 µA ICC Standby Current Consumption Standby, Unprogrammed – 0.6 0.5 m A Power Supply Current Active, VCC =3 V(1) 25 MHz – 80(4) – mA Idle, VCC =3 V(1) –– 1.0 m A Power-down, VCC =3 V(1) WDT Enable – 60 500 µA Power-down, VCC =3 V(1) WDT Disable – 30 200 µA Power-save, VCC =3 V(1) WDT Disable – 50 400 µA FPGA Core Current Consumption – 2 – mA/MHz CIN Input Capacitance All Pins –– 10 pF

time requires more current than a slow ramp-up time. Notes: 1. This specification applies to Commercial and Industrial grade products only.

1. Devices are guaranteed to initialize properly at 50% of the minimum current listed above. A

larger capacity power supply may result in a larger initialization current.

1. Ramp-up time is measured from 0 V DC to 3.6 V DC. Peak current required lasts less than 2

ms, and occurs near the internal power on reset threshold voltage. Table 48. Power-On Power Supply Requirements (1)

162 AT94K Series FPSLIC

a read cycle if WE remains Low during rising edge of ME. Figure 83. SRAM Read Cycle Timing Diagram Figure 84. SRAM Write Cycle Timing Diagram inverted (ME = ~FrameClock). Selecting the non-inverted phase assigns ME = FrameClock.

Table 49. SRAM Read Cycle Timing Numbers Table 50. SRAM Write Cycle Timing Numbers

164 AT94K Series FPSLIC

XTAL2 output pin. Remember that XT AL2 is inverted in comparison to XT AL1. Table 51. FPSLIC Interface Timing Information (1)

Figure 85. External Clock Drive Waveforms Table 52. External Clock Drive, V CC =3 . 0 Vt o3 . 6 V

166 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 AC Timing Characteristics – 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V CC = 3.00V, temperature = 70 °C Minimum times based on best case: V CC = 3.60V, temperature = 0 °C Maximum delays are the average of t PDLH and tPDHL. Cell Function Parameter Path -25 Units Notes Core

2 Input Gate t

PD (Maximum) x/y -> x/y 2.9 ns 1 Unit Load 3 Input Gate t PD (Maximum) x/y/z -> x/y 2.8 ns 1 Unit Load 3 Input Gate t PD (Maximum) x/y/w -> x/y 3.4 ns 1 Unit Load 4 Input Gate t PD (Maximum) x/y/w/z -> x/y 3.4 ns 1 Unit Load Fast Carry t PD (Maximum) y -> y 2.3 ns 1 Unit Load Fast Carry t PD (Maximum) x -> y 2.9 ns 1 Unit Load Fast Carry t PD (Maximum) y -> x 3.0 ns 1 Unit Load Fast Carry t PD (Maximum) x -> x 2.3 ns 1 Unit Load Fast Carry t PD (Maximum) w -> y 3.4 ns 1 Unit Load Fast Carry t PD (Maximum) w -> x 3.4 ns 1 Unit Load Fast Carry t PD (Maximum) z -> y 3.4 ns 1 Unit Load Fast Carry t PD (Maximum) z -> x 2.4 ns 1 Unit Load DFF t PD (Maximum) q -> x/y 2.8 ns 1 Unit Load DFF t setup (Minimum) x/y -> clk –– – DFF t hold (Minimum) x/y -> clk –– – DFF t PD (Maximum) R -> x/y 3.2 ns 1 Unit Load DFF t PD (Maximum) S -> x/y 3.0 ns 1 Unit Load DFF t PD (Maximum) q -> w 2.7 ns – incremental -> L t PD (Maximum) x/y -> L 2.4 ns – Local Output Enable t PZX (Maximum) oe -> L 2.8 ns 1 Unit Load Local Output Enable t PXZ (Maximum) oe -> L 2.4 ns

Rev. 1138F–FPSLI–06/02 AC Timing Characteristics – 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V CC = 3.0V, temperature = 70 °C Minimum times based on best case: V CC = 3.6V, temperature = 0 °C Maximum delays are the average of t PDLH and tPDHL. All input IO characteristics measured from a V IH of 50% of V DD at the pad (CMOS threshold) to the internal V IH of 50% of VDD. All output IO characteristics are measured as the average of t PDLH and tPDHL to the pad VIH of 50% of VDD. Cell Function Parameter Path -25 Units Notes Repeaters Repeater t PD (Maximum) L -> E 2.2 ns 1 Unit Load Repeater t PD (Maximum) E -> E 2.2 ns 1 Unit Load Repeater t PD (Maximum) L -> L 2.2 ns 1 Unit Load Repeater t PD (Maximum) E -> L 2.2 ns 1 Unit Load Repeater t PD (Maximum) E -> IO 1.4 ns 1 Unit Load Repeater t PD (Maximum) L -> IO 1.4 ns 1 Unit Load All input IO characteristics measured from a V IH of 50% of V DD at the pad (CMOS threshold) to the internal V IH of 50% of VDD. All output IO characteristics are measured as the average of t PDLH and tPDHL to the pad VIH of 50% of VDD. Cell Function Parameter Path -25 Units Notes IO Input t PD (Maximum) pad -> x/y 1.9 ns No Extra Delay Input t PD (Maximum) pad -> x/y 5.8 ns 1 Extra Delay Input t PD (Maximum) pad -> x/y 11.5 ns 2 Extra Delays Input t PD (Maximum) pad -> x/y 17.4 ns 3 Extra Delays Output, Slow t PD (Maximum) x/y/E/L -> pad 9.1 ns 50 pf Load Output, Medium t PD (Maximum) x/y/E/L -> pad 7.6 ns 50 pf Load Output, Fast t PD (Maximum) x/y/E/L -> pad 6.2 ns 50 pf Load Output, Slow t PZX (Maximum) oe -> pad 9.5 ns 50 pf Load Output, Slow t PXZ (Maximum) oe -> pad 2.1 ns 50 pf Load Output, Medium t PZX (Maximum) oe -> pad 7.4 ns 50 pf Load Output, Medium t PXZ (Maximum) oe -> pad 2.7 ns 50 pf Load Output, Fast t PZX (Maximum) oe -> pad 5.9 ns 50 pf Load Output, Fast t PXZ (Maximum) oe -> pad 2.4 ns 50 pf Load

168 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 AC Timing Characteristics – 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V CC = 3.0V, temperature = 70 °C Minimum times based on best case: V CC = 3.6V, temperature = 0 °C Maximum delays are the average of t PDLH and tPDHL. Clocks and Reset Input buffers are measured from a V IH of 1.5V at the input pad to the internal V IH of 50% of VCC. Maximum times for clock input buffers and internal drivers are measured for rising edge delays only. Cell Function Parameter Path Device -25 Units Notes Global Clocks and Set/Reset GCK Input Buffer t PD (Maximum) pad -> clock pad -> clock A T94K05 A T94K10 A T94K40 1.2 1.5 1.9 ns ns Rising Edge Clock FCK Input Buffer t PD (Maximum) pad -> clock pad -> clock A T94K05 A T94K10 A T94K40 0.7 0.8 0.9 ns ns Rising Edge Clock Clock Column Driver t PD (Maximum) clock -> colclk clock -> colclk A T94K05 A T94K10 A T94K40 1.3 1.8 2.5 ns ns Rising Edge Clock Clock Sector Driver t PD (Maximum) colclk -> secclk colclk -> secclk A T94K05 A T94K10 A T94K40 1.0 1.0 1.0 ns ns Rising Edge Clock GSRN Input Buffer t PD (Maximum) colclk -> secclk colclk -> secclk A T94K05 A T94K10 A T94K40 5.4 8.2 ns ns Global Clock to Output t PD (Maximum) clock pad -> out clock pad -> out A T94K05 A T94K10 A T94K40 12.6 13.4 14.5 ns ns Rising Edge Clock Fully Loaded Clock Tree Rising Edge DFF 20 mA Output Buffer 50 pf Pin Load Fast Clock to Output t PD (Maximum) clock pad -> out clock pad -> out A T94K05 A T94K10 A T94K40 12.1 12.7 13.5 ns ns Rising Edge Clock Fully Loaded Clock Tree Rising Edge DFF 20 mA Output Buffer 50 pf Pin Load

Rev. 1138F–FPSLI–06/02 CMOS buffer delays are measured from a V IH of 1/2 V CC at the pad to the internal V IH at A. The input buffer load is con- stant. Buffer delay is to a pad voltage of 1.5V with one output switching. Parameter based on characterization and simulation; not tested in production. An FPGA power calculation is available in Atmel ’s System Designer software (see also page 160). AC Timing Characteristics – 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V CC = 3.0V, temperature = 70 °C Minimum times based on best case: V CC = 3.6V, temperature = 0 °C Cell Function Parameter Path -25 Units Notes Async RAM Write t WECYC (Minimum) cycle time 12.0 ns – Write t WEL (Minimum) we 5.0 ns Pulse Width Low Write t WEH (Minimum) we 5.0 ns Pulse Width High Write t setup (Minimum) wr addr setup-> we 5.3 ns Write t hold (Minimum) wr addr hold -> we 0.0 ns – Write t setup (Minimum) din setup -> we 5.0 ns Write t hold (Minimum) din hold -> we 0.0 ns – Write t hold (Minimum) oe hold -> we 0.0 ns Write/Read t PD (Maximum) din -> dout 8.7 ns rd addr = wr addr Read t PD (Maximum) rd addr -> dout 6.3 ns Read t PZX (Maximum) oe -> dout 2.9 ns – Read t PXZ (Maximum) oe -> dout 3.5 ns Sync RAM Write t CYC (Minimum) cycle time 12.0 ns Write t CLKL (Minimum) clk 5.0 ns – Write t CLKH (Minimum) clk 5.0 ns Pulse Width High Write t setup (Minimum) we setup-> clk 3.2 ns Write t hold (Minimum) we hold -> clk 0.0 ns – Write t setup (Minimum) wr addr setup-> clk 5.0 ns Write t hold (Minimum) wr addr hold -> clk 0.0 ns – Write t setup (Minimum) wr data setup-> clk 3.9 ns Write t hold (Minimum) wr data hold -> clk 0.0 ns – Write/Read t PD (Maximum) din -> dout 8.7 ns rd addr = wr addr Write/Read t PD (Maximum) clk -> dout 5.8 ns rd addr = wr addr Read t PD (Maximum) rd addr -> dout 6.3 ns Read t PZX (Maximum) oe -> dout 2.9 ns – Read t PXZ (Maximum) oe -> dout 3.5 ns

170 AT94K Series FPSLIC

FPSLIC devices should be laid out to support a split power supply for both AL and AX families. AT94SAL/AX Devices ”application note, available on the Atmel web site. Table 53. Part and Package Combinations Available Table 54. AT94K JTAG ICE Pin List

96 FPGA I/O

192 FPGA I/O

384 FPGA I/O

Table 55. AT94K Pin List AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

Table 55. AT94K Pin List (Continued) AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

172 AT94K Series FPSLIC

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

174 AT94K Series FPSLIC

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

176 AT94K Series FPSLIC

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

178 AT94K Series FPSLIC

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

180 AT94K Series FPSLIC

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

182 AT94K Series FPSLIC

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. VDD is core high voltage. Please refer to the “Designing in Split Power Supply Support

for AT94KAL/AX and AT94SAL/AX Devices ”application note.

1. Unbonded pins are No Connects.

184 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02

Ordering Information

Usable Gates Speed Grade Ordering Code Package Operation Range 5,000 -25 MHz A T94K05AL-25AJC A T94K05AL-25AQC A T94K05AL-25BQC A T94K05AL-25DQC 84J 100A 144L1 208Q1 Commercial (0°C-7 0 °C) A T94K05AL-25AJI A T94K05AL-25AQI A T94K05AL-25BQI A T94K05AL-25DQI 84J 100A 144L1 208Q1 Industrial (-40°C-8 5 °C) 10,000 -25 MHz A T94K10AL-25AJC A T94K10AL-25AQC A T94K10AL-25BQC A T94K10AL-25DQC 84J 100A 144L1 208Q1 Commercial (0°C-7 0 °C) A T94K10AL-25AJI A T94K10AL-25AQI A T94K10AL-25BQI A T94K10AL-25DQI 84J 100A 144L1 208Q1 Industrial (-40°C-8 5 °C) 40,000 -25 MHz A T94K40AL-25BQC A T94K40AL-25DQC 144L1 208Q1 Commercial (0°C-7 0 °C) A T94K40AL-25BQI A T94K40AL-25DQI 144L1 208Q1 Industrial (-40°C-8 5 °C) Package Type 84J 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100A 100-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 144L1 144-lead, Low Profile Plastic Gull Wing Quad Flat Package (LQFP) 208Q1 208-lead, Plastic Gull Wing Quad Flat Package (PQFP)

Rev. 1138F–FPSLI–06/02 Packaging Information 84J – PLCC

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC) B84J 10/04/01 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A B1 D2/E2 B e E1 E D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 30.099 – 30.353 D1 29.210 – 29.413 Note 2 E 30.099 – 30.353 E1 29.210 – 29.413 Note 2 D2/E2 27.686 – 28.702 B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP

186 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 100A – TQFP San Jose, CA 95131 TITLE DRAWING NO. R REV. 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) C100A 10/5/2001 PIN 1 IDENTIFIER 0˚~7˚ PIN 1 L C A1 A2 A D e E1 E B A –– 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.17 – 0.27 C 0.09 – 0.20 L 0.45 – 0.75 e 0.50 TYP Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE

Rev. 1138F–FPSLI–06/02 144L1 – LQFP San Jose, CA 95131 TITLE DRAWING NO. R REV. 144L1 A 11/30/01 144L1, 144-lead (20 x 20 x 1.4 mm Body), Low Profile Plastic Quad Flat Pack (LQFP) Bottom View Side View Top View NT YRU CO XX e D E b COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages. 5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. A1 is defined as the distance from the seating place to the lowest point on the package body. A1 0.05 0.15 6 A2 1.35 1.40 1.45 D 22.00 BSC D1 20.00 BSC 2, 3 E 22.00 BSC E1 20.00 BSC 2, 3 e 0.50 BSC b 0.17 0.22 0.27 4, 5 L1 1.00 REF Notes:

188 AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02 208Q1 – PQFP San Jose, CA 95131 TITLE DRAWING NO. R REV. 208Q1, 208-lead (28 x 28 mm Body, 2.6 Form Opt.), Plastic Quad Flat Pack (PQFP) 208Q1 A 11/30/01 A1A1 b D E e Side View Bottom View Top View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.25 0.50 A2 3.20 3.40 3.60 D 30.60 BSC D1 28.00 BSC 2, 3 E 30.60 BSC E1 28.00 BSC 2, 3 e 0.50 BSC b 0.17 0.27 4 L1 1.30 REF Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, toler ances, datums, etc. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm.

Rev. 1138F–FPSLI–06/02 Thermal Coefficient Table Package Style Lead Count Theta J-A

0 LFPM

225 LFPM

500 LPFM Theta J-C

LQFP 144 33 27 23 8.5 P Q F P 2 0 8 3 22 82 41 0

i AT94K Series FPSLIC 1138F–FPSLI–06/02 Program and SRAM Access X-register, Y-register and

1138F–FPSLI–06/02 IEEE 1149.1 (JTAG) 2-wire Serial Interface

Printed on recycled paper. © Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard warranty w h i c hi sd e t a i l e di nA t m e l’s Terms and Conditions located on the Company ’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel ’s products are not authorized for use as critical components in life support devices or systems. Atmel Headquarters Atmel Operations Corporate Headquarters San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza

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44306 Nantes Cedex 3, France

13106 Rousset Cedex, France

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Atmel Programmable SLI Hotline (408) 436-4119 Atmel Programmable SLI e-mail fpslic@atmel.com FAQ Available on web site e-mail literature@atmel.com Web Site http://www.atmel.com ATM EL®,A V R® and AVR Studio ® are the registered trademarks of Atmel. Microsoft ®, Windows ® and Windows NT ® are the registered trademarks of Microsoft Corporation. Other terms and product names may be the trademarks of others. Rev. 1138F–FPSLI–06/02