AT945

AT945 ATMEL | Alldatasheet

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Technical content

Features

• Multichip Module Containing Field Programmable System Level Integrated Circuit (FPSLIC™ ) and Secure Configuration EEPROM Memory  512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System Programming (ISP)  Field Programmable System Level Integrated Circuit (FPSLIC) – AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core and Extensive Data and Instruction SRAM  5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™ – 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM – High-performance DSP Optimized FPGA Core Cell – Dynamically Reconfigurable In-System – FPGA Configuration Access Available On-chip from AVR Microcontroller Core to Support Cache Logic ® Designs – Very Low Static and Dynamic Power Consumption – Ideal for Portable and Handheld Applications  Patented AVR Enhanced RISC Architecture – 120+ Powerful Instructions – Most Single Clock Cycle Execution – High-performance Hardware Multiplier for DSP-based Systems – Approaching 1 MIPS per MHz Performance – C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers – Low-power Idle, Power-save, and Power-down Modes – 100 µA Standby and Typical 2-3 mA per MHz Active  Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM – Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM – Up to 16 Kbytes x 8 Internal 15 ns Data SRAM  JTAG (IEEE Std. 1149.1 Compliant) Interface – Extensive On-chip Debugging Support – Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)  AVR Fixed Peripherals – Industry-standard 2-wire Serial Interface – Two Programmable Serial UARTs – Two 8-bit Timer/Counters with Separate Prescaler and PWM – One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM  Support for FPGA Custom Peripherals – AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly Accessible to FPGA – FPGA Macro Library of Custom Peripherals  Up to 16 FPGA Supplied Internal Interrupts to AVR  Up to Four External Interrupts to AVR  8 Global FPGA Clocks – Two FPGA Clocks Driven from AVR Logic – FPGA Global Clock Access Available from FPGA Core  Multiple Oscillator Circuits – Programmable Watchdog Timer with On-chip Oscillator – Oscillator to AVR Internal Clock Circuit – Software-selectable Clock Frequency – Oscillator to Timer/Counter for Real-time Clock  VCC : 3.0V - 3.6V  5V Tolerant I/O  3.3V 33 MHz PCI Compliant FPGA I/O – 20 mA Sink/Source High-performance I/O Structures – All FPGA I/O Individually Programmable  High-performance, Low-power 0.35µ CMOS Five-layer Metal Process  State-of-the-art Integrated PC-based Software Suite including Co-verification Rev. 2314D–FPSLI–2/04 Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM AT94S Secure Series Programmable SLI

2 AT94S Secure Family

logic are included in this multi-chip module (MCM). of data) and 5,000 to 40,000 usable gates. Table 1. The AT94S Series Family

Figure 1. AT94S Architecture configuration memories, which are part of the AT94S Multi-chip Module (MCM). complete system co-verification in one easy-to-use software tool.

4 Interrupt Lines

4 AT94S Secure Family

2314D–FPSLI–2/04 Internal ArchitectureFor details of the AT94S Secure FPSLIC architecture, please refer to the AT94K FPSLIC datasheet and the AT17 Series Configuration Memory datasheet, available on the Atmel web site at http://www.atmel.com. This document only describes the differ- ences between the AT94S Secure FPSLIC and the AT94K FPSLIC. FPSLIC and Configurator Interface  Fully In-System Programmable and Re-programmable  When Security Bit Set: – Data Verification Disabled – Data Transfer to FPSLIC not Externally Visible – Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip Erase  When Security Bit Cleared: – Entire Chip Erase Performed – In-System Programming Enabled – Data Verification Enabled External Data pins allow for In-System Programming of the device and setting of the EEPROM-based security bit. When the security bit is set (active) this programming con- nection will only respond to a device erase command. Data cannot be read out of the external programming/data pins when the security bit is set. The part can be re-pro- grammed, but only after first being erased. Programming and Configuration Timing Characteristics Atmel’s Configurator Programming Software (CPS), available from the Atmel web site (http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3191), creates the pro- gramming algorithm for the embedded configurator; however, if you are planning to write your own software or use other means to program the embedded configurator, the section below includes the algorithm and other details. The FPSLIC ConfiguratorThe FPSLIC Configurator is a serial EEPROM memory which is used to load program- mable devices. This document describes the features needed to program the Configurator from within its programming mode (i.e., when SER_EN is driven Low). Reference schematics are supplied for ISP applications. Serial Bus Overview The serial bus is a two-wire bus; one wire (cSCK) functions as a clock and is provided by the programmer, the second wire (cSDA) is a bi-directional signal and is used to pro- vide data and control information. Information is transmitted on the serial bus in messages. Each MESSAGE is preceded by a Start Condition and ends with a Stop Condition. The message consists of an inte- ger number of bytes, each byte consisting of 8 bits of data, followed by a ninth Acknowledge Bit. This Acknowledge Bit is provided by the recipient of the transmitted byte. This is possible because devices may only drive the cSDA line Low. The system must provide a small pull-up current (1 k Ω equivalent) for the cSDA line. The MESSAGE FORMAT for read and write instructions consists of the bytes shown in “Bit Format” on page 5. While writing, the programmer is responsible for issuing the instruction and data. While reading, the programmer issues the instruction and acknowledges the data from the Configurator as necessary.

2314D–FPSLI–2/04 Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a byte-by-byte basis. The factory blanks devices to all zeros before shipping. The array cannot otherwise be “initialized” except by explicitly writing a known value to each location using the serial protocol described herein. Bit Format Data on the cSDA pin may change only during the cSCK Low time; whereas Start and Stop Conditions are identified as transitions during the cSCK High time. Write Instruction Message Format Current Address Read (Extended to Sequential Read) Instruction Message FormatStart and Stop Conditions The Start Condition is indicated by a high-to-low transition of the cSDA line when the cSCK line is High. Similarly, the Stop Condition is generated by a low-to-high transition of the cSDA line when the cSCK line is High, as shown in Figure 2. The Start Condition will return the device to the state where it is waiting for a Device Address (its normal quiescent mode). The Stop Condition initiates an internally timed write signal whose maximum duration is t WR (refer to AC Characteristics table for actual value). During this time, the Configurator must remain in programming mode (i.e., SER_EN is driven Low). cSDA and cSCK lines are ignored until the cycle is completed. Since the write cycle typically completes in less than t WR seconds, we recommend the use of “polling” as described in later sections. Input levels to all other pins should be held constant until the write cycle has been completed. Acknowledge Bit The Acknowledge (ACK) Bit shown in Figure 2 is provided by the Configurator receiving the byte. The receiving Configurator can accept the byte by asserting a Low value on the cSDA line, or it can refuse the byte by asserting (allowing the signal to be externally pulled up to) a High value on the cSDA line. All bytes from accepted messages must be terminated by either an Acknowledge Bit or a Stop Condition. Following an ACK Bit, when the cSDA line is released during an exchange of control between the Configurator and the programmer, the cSDA line may be pulled High temporarily due to the open-col- lector output nature of the line. Control of the line must resume before the next rising edge of the clock. ACK BIT (CONFIGURATOR) DATA BYTE n STOP CONDITION START CONDITION DEVICE ADDRESS MS EEPROM ADDRESS BYTE (NEXT) EEPROM ADDRESS BYTE LS EEPROM ADDRESS BYTE DATA BYTE 1 ACK BIT (CONFIGURATOR) DATA BYTE n STOP CONDITION START CONDITION DEVICE ADDRESS DATA BYTE 1 ACK BIT (PROGRAMMER)

6 AT94S Secure Family

protocol is shown in the diagrams below. the bits are clocked into the device. Figure 2. Start and Stop Conditions the Configurator is also indicated. Unused bits in an Address Byte must be set to “0”. Exceptions to this are when reading Device and Manufacturer Codes.

1010011 R / W

0000000 A E16 ACK A E15 AE14 AE13 AE12 AE11 AE10 AE9 AE8 ACK A E7 AE6 AE5 AE4 AE3 AE2 AE1 AE0 ACK

2314D–FPSLI–2/04 Notes: 1. The 1-Mbit part requires three EEPROM address bytes; all three bytes must be individually ACK’d by the EEPROM. 2. Data byte received/sent LSB to MSB. EEPROM Address is Defined as: Note: where X n ... X0 is (P AGE_COUNT)\\b T_BYTE T_PAGE AT17LV010 0000 000x 9 x8x7x6x5 x4x3x2x1 x0000 0000 AT17LV010 128 AT17LV010 1024 cSDA cSCK cSDA cSCK DATA BIT STOP CONDITION cSDA cSCK ACK BIT cSDA cSCK ACK START CONDITION Programming Summary: Write to Whole Device SER_EN ≤ Low PAGE_COUNT ≤ 0 START Send Start Condition BYTE_COUNT ≤ 0 Send Device Address ($A6) ACK? Send MSB of EEPROM Address (1) ACK? Send LSB of EEPROM Address (1) Send Data Byte(2) BYTE_COUNT ≤ BYTE_COUNT+1 BYTE_COUNT = T_BYTE? Send Stop Condition PAGE_COUNT ≤ PAGE_COUNT+1 PAGE_COUNT = T_PAGE? Yes No No No Yes No Send Start Condition Send Device Address ($A7) END ACK? Yes No ACK? Yes No ACK? Yes No Yes SER_EN ≤ High Low-power (Standby) Power-Cycle EEPROM (Latches 1st Byte for FPGA Download Operations) 1st Data Byte Value Changed Due to Write? No Verify Final Write Cycle Completion Yes Middle Byte EEPROM Address ACK? No Yes

8 AT94S Secure Family

2314D–FPSLI–2/04 Programming Summary: Read from Whole Device SER_EN ≤ Low START Send Start Condition Send Device Address ($A6) ACK? Send MSB of EEPROM Address (1) ACK? Send LSB of EEPROM Address (1) Send Start condition BYTE_COUNT ≤ 0 Send Device Address ($A7) Yes No No Read Data Byte(2) BYTE_COUNT ≤ BYTE_COUNT+1 Send ACK END BYTE_COUNT= TT_BYTE?No ACK? Yes No Yes Sent Stop Condition SER_EN ≤ High Low-power (Standby) Sequential Read from Current Address ACK? No Yes Yes Random Access SetupMiddle Byte EEPROM Address ACK? No Yes Notes: 1. The 1-Mbit part requires three EEPROM address bytes; all three bytes must be individually ACK’d by the EEPROM. 2. Data byte received/sent LSB to MSB EEPROM Address is Defined as: TT_BYTE AT17LV010 00 00 00 \\h AT17LV010 131072 \\d cSDA cSCK cSDA cSCK SAMPLE DATA BIT STOP CONDITION START CONDITION cSDA cSCK ACK BIT cSDA cSCK ACK

2314D–FPSLI–2/04 The organization of the Data Byte is shown above. Note that in this case, the Data Byte is clocked into the device LSB first and MSB last. Writing Writing to the normal address space takes place in pages. A page is 128-bytes long in the 1-Mbit part. The page boundaries are, respectively, addresses where AE0 down to AEOS are all zero, and AE6 down to AE0 are all zero. Writing can start at any address within a page and the number of bytes written must be 128 for the 1-Mbit part. The first byte is written at the transmitted address. The address is incremented in the Configura- tor following the receipt of each Data Byte. Only the lower 7 bits of the address are incremented. Thus, after writing to the last byte address within the given page, the address will roll over to the first byte address of the same page. A Write Instruction con- sists of: a Start Condition a Device Address Byte with R/W = 0 An Acknowledge Bit from the Configurator MS Byte of the EEPROM Address An Acknowledge Bit from the Configurator Next Byte of the EEPROM Address An Acknowledge Bit from the Configurator LS Byte of EEPROM Address An Acknowledge Bit from the Configurator One or more Data Bytes (sent to the Configurator) Each followed by an Acknowledge Bit from the Configurator a Stop Condition WRITE POLLING: On receipt of the Stop Condition, the Configurator enters an inter- nally-timed write cycle. While the Configurator is busy with this write cycle, it will not acknowledge any transfers. The programmer can start the next page write by sending the Start Condition followed by the Device Address, in effect polling the Configurator. If this is not acknowledged, then the programmer should abandon the transfer without asserting a Stop Condition. The programmer can then repeatedly initiate a write instruc- tion as above, until an acknowledge is received. When the Acknowledge Bit is received, the write instruction should continue by sending the first EEPROM Address Byte to the Configurator. An alternative to write polling would be to wait a period of t WR before sending the next page of data or exiting the programming mode. All signals must be maintained during the entire write cycle. Data Byte LSB MSB D0 D1 D2 D3 D4 D5 D6 D7 1st 2nd 3rd 4th 5th 6th 7th 8th

10 AT94S Secure Family

2314D–FPSLI–2/04 Reading Read instructions are initiated similarly to write instructions. However, with the R/W bit in the Device Address set to one. There are three variants of the read instruction: current address read, random read and sequential read. For all reads, it is important to understand that the internal Data Byte address counter maintains the last address accessed during the previous read or write operation, incre- mented by one. This address remains valid between operations as long as the chip power is maintained and the device remains in 2-wire access mode (i.e., SER_EN is driven Low). If the last operation was a read at address n, then the current address would be n + 1. If the final operation was a write at address n, then the current address would again be n + 1 with one exception. If address n was the last byte address in the page, the incremented address n + 1 would “roll over” to the first byte address on the next page. CURRENT ADDRESS READ: Once the Device Address (with the R/W select bit set to High) is clocked in and acknowledged by the Configurator, the Data Byte at the current address is serially clocked out by the Configurator in response to the clock from the pro- grammer. The programmer generates a Stop Condition to accept the single byte of data and terminate the read instruction. A Current Address Read instruction consists of a Start Condition a Device Address with R/W = 1 An Acknowledge Bit from the Configurator a Data Byte from the Configurator a Stop Condition from the programmer. RANDOM READ: A Random Read is a Current Address Read preceded by an aborted write instruction. The write instruction is only initiated for the purpose of loading the EEPROM Address Bytes. Once the Device Address Byte and the EEPROM Address Bytes are clocked in and acknowledged by the Configurator, the programmer immedi- ately initiates a Current Address Read. A Random Address Read instruction consists of : a Start Condition a Device Address with R/W = 0 An Acknowledge Bit from the Configurator MS Byte of the EEPROM Address An Acknowledge Bit from the Configurator Next Byte of the EEPROM Address An Acknowledge Bit from the Configurator LS Byte of EEPROM Address An Acknowledge bit from the Configurator a Start Condition a Device Address with R/W = 1 An Acknowledge Bit from the Configurator a Data Byte from the Configurator a Stop Condition from the programmer.

2314D–FPSLI–2/04 SEQUENTIAL READ: Sequential Reads follow either a Current Address Read or a Random Address Read. After the programmer receives a Data Byte, it may respond with an Acknowledge Bit. As long as the Configurator receives an Acknowledge Bit, it will continue to increment the Data Byte address and serially clock out sequential Data Bytes until the memory address limit is reached. (1) The Sequential Read instruction is terminated when the programmer does not respond with an Acknowledge Bit but instead generates a Stop Condition following the receipt of a Data Byte. Note: 1. If an ACK is sent by the programmer after the data in the last memory address is sent by the configurator, the internal address counter will “rollover” to the first byte address of the memory array and continue to send data as long as an ACK is sent by the programmer. Programmer Functions The following programmer functions are supported while the Configurator is in program- ming mode (i.e., when SER_EN is driven Low): 1. Read the Manufacturer’s Code and the Device Code (optional for ISP). 2. Program the device. 3. Verify the device. In the order given above, they are performed in the following manner. Reading Manufacturer’s and Device Codes On AT17LV010 Configurator, the sequential reading of these bytes are accomplished by performing a Random Read at EEPROM Address 040000H. The correct codes are: Manufacturers Code -Byte 0 1E Device Code - Byte 1 F7 AT17LV010 Note: The Manufacturer’s Code and Device Code are read using the byte ordering specified for Data Bytes; i.e., LSB first, MSB last. Programming the Device All the bytes in a given page must be written. The page access order is not important but it is suggested that the Configurator be written sequentially from address 0. Writing is accomplished by using the cSDA and cSCK pins. Important Note on AT94S Series Configurators Programming The first byte of data will not be cached for read back during FPGA Configuration (i.e., when SER_EN is driven High) until the Configurator is power-cycled. Verifying the Device All bytes in the Configurator should be read and compared to their intended values. Reading is done using the cSDA and cSCK pins. In-System Programming

Applications

The AT94S Series Configurators are in-system (re)programmable (ISP). The example shown on the following page supports the following programmer functions: 1. Read the Manufacturer’s Code and the Device Code. 2. Program the device. 3. Verify the device data. While Atmel’s Secure FPSLIC Configurators can be programmed from various sources (e.g., on-board microcontrollers or PLDs), the applications shown here are designed to facilitate users of our ATDH2225 Configurator Programming Cable. The typical system setup is shown in Figure 3. The pages within the configuration EEPROM can be selectively rewritten. This document is limited to example implementations for Atmel’s AT94S application.

12 AT94S Secure Family

Figure 3. Typical System Setup Figure 4. ISP of the AT17LV512/010 in an AT94S FPSLIC Application Note: 1. Configurator signal names are shown in parenthesis.

Figure 5. Serial Data Timing Diagram

14 AT94S Secure Family

2314D–FPSLI–2/04 Notes: 1. Specific to programming mode (i.e., when SER_EN is driven Low) 2. Commercial temperature range 0°C - 70°C 3. Industrial temperature range -40°C - 85°C 4. This parameter is characterized and is not 100% tested. Notes: 1. Specific to programming mode (i.e., when SER_EN is driven Low) 2. Commercial temperature range 0°C - 70°C 3. Industrial temperature range -40°C - 85°C 4. This parameter is characterized and is not 100% tested. DC Characteristics(1) Symbol Parameter Test Condition Min Typ Max Units VCC Supply Voltage 3.0 3.3 3.6 V ICC Supply Current V CC = 3.6 2 3 m A ILL Input Leakage Current V IN = VCC or VSS 0.10 10 µA ILO Output Leakage Current V OUT = VCC or VSS 0.05 10 µA VIH High-level Input Voltage V CC x 0.7 V CC + 0.5 V VIL Low-level Input Voltage -0.5 0.2 V VOL Output Low-level Voltage I OL = 2.1 mA 0.4 V AC Characteristics(1) Symbol Parameter Min Max Units fCLOCK Clock Frequency, Clock 100 KHz tLOW Clock Pulse Width Low 4 µs tHIGH Clock Pulse Width High 4 µs tAA Clock Low to Data Out Valid 0.1 1 µs tBUF Time the Bus Must Be Free Before a New T ransmission Can Start 4.5 µs tHD;STA Start Hold Time 2 µs tSU;STA Start Setup Time 2 µs tHD DAT Data In Hold Time 0 µs tSU DA T Data In Setup Time 0.2 µs tR Inputs Rise Time 0.3 µs tF Inputs Fall Time 0.3 µs tSU STO Stop Setup Time 2 µs tDH Data Out Hold Time 0.1 µs tWR Write Cycle Time 20 ms

2314D–FPSLI–2/04 Security Bit Once the security bit is programmed, data will no longer output from the normal data pad. Once the fuse is set, any attempt to erase the fuse will cause the configurator to erase all of it contents. AT17LV512/010 Security Bit Programming Disabling the Security Bit Write 4 bytes “00 00 00 00” to addresses 800000-800003 twice, without a power cycle in between, using the previously defined 2-wire write algorithm. Enabling the Security Bit Write 4 bytes “FF FF FF FF” to addresses 800000-800003 using the previously defined 2-wire write algorithm. Verifying the Security Bit Read 4 bytes of data from addresses 800000-800003 using the previously defined 2- wire Random Read algorithm. If the data is “FF FF FF FF”, the security bit has been enabled. If the data is “00 00 00 00”, the security bit has been disabled. Secure FPSLIC Configurator Pin Configurations 144-pin LQFP 256-pin CABGA Name I/O Description 105 D16 cSDA I/O Three-state DAT A output for configuration. Open-collector bi-directional pin for programming. 107 C16 cSCK O CLOCK output. Used to increment the internal address and bit counter for reading and programming. 53 K9 RESET/O E I RESET/OE input (when SER_EN is High). A Low level on both the CE and RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the address and bit counters. The logic polarity of this input is programmable as either RESET/OE or RESET /OE. This document describes the pin as RESET/OE . 72 N16 CE I Chip Enable input. Used for device selection only when SER_EN is High. A Low level on both CE and OE enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power mode. Note this pin will not enable/disable the device in the 2-wire Serial mode (i.e., when SER_EN is driven Low).

81 M5 SER_EN I Serial enable is normally High during FPGA

loading operations. Bringing SER_EN Low enables the programming mode.

16 AT94S Secure Family

will erase the entire array. See Table 2 for specifics on the write algorithm. Figure 6. Chip Erase Timing Diagram Table 2. Chip Erase Cycle Characteristics

Table 4. AT94K JTAG ICE Pin List

96 FPGA I/O

192 FPGA I/O

384 FPGA I/O

Table 5. AT94S Pin List

144 FPGA I/O

288 FPGA I/O

18 AT94S Secure Family

Table 5. AT94S Pin List (Continued)

20 AT94S Secure Family

22 AT94S Secure Family

24 AT94S Secure Family

26 AT94S Secure Family

Note: 1. LQ144 is only offered in the A T94S10 and AT94S40. http://www.atmel.com/dyn/products/app_notes.asp?family_id=627. Table 6. 256 CABGA and LQ144 VDD , VCC and GND Pins(1)

0 LFPM

225 LFPM

500 LPFM

28 AT94S Secure Family

2314D–FPSLI–2/04

Ordering Information

Usable Gates Speed Grade Ordering Code Package Operation Range 5,000 25 MHz AT94S05AL-25DGC 256ZA Commercial (0°C - 70°C) AT94S05AL-25DGI 256ZA Industrial (-40°C - 85°C) 10,000 25 MHz AT94S10AL-25DGC 256ZA Commercial (0°C - 70°C)AT94S10AL-25BQC 144L1 AT94S10AL-25DGI 256ZA Industrial (-40°C - 85°C)AT94S10AL-25BQI 144L1 40,000 16 MHz AT94S40AL-25DGC 256ZA Commercial (0°C - 70°C)AT94S40AL-25BQC 144L1 AT94S40AL-25DGI 256ZA Industrial (-40°C - 85°C)AT94S40AL-25BQI 144L1 Package Type 256ZA 256-ball, Chip Array Ball Grid Array Package (CABGA) 144L1 144-lead, Low Profile Plastic Gull Wing Quad Flat Package (LQFP)

2314D–FPSLI–2/04 Packaging Information 256ZA – CABGA

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 256ZA, 256-ball (16 x 16 Array), 17 x 17 mm Body, Chip Array Ball Grid Array (CABGA) Package A256ZA 11/07/01 Top View 123 A1 Ball Pad Corner 45678 A B D C E 910111214 131516 G J H K M L N P R T

1.00 REF

(256 SOLDER BALLS) F D A1 Ball Pad Corner E Side View b A e e COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D – 17 BSC – E – 17 BSC – A 1.30 1.40 1.50 A1 0.31 0.36 0.41 A2 0.29 0.34 0.39 A3 0.65 0.70 0.75 e 1.00 BSC b 0.46 REF Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-205 for proper dimensions, tolerances, datums, etc. 2. Array as seen from the bottom of the package.

30 AT94S Secure Family

2314D–FPSLI–2/04 144L1 – LQFP San Jose, CA 95131 TITLE DRAWING NO. R REV. 144L1 A 11/30/01 144L1, 144-lead (20 x 20 x 1.4 mm Body), Low Profile Plastic Quad Flat Pack (LQFP) Bottom View Side View Top View N T YRU CO XX e D E b COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages. 5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. A1 is defined as the distance from the seating place to the lowest point on the package body. A1 0.05 0.15 6 A2 1.35 1.40 1.45 D 22.00 BSC D1 20.00 BSC 2, 3 E 22.00 BSC E1 20.00 BSC 2, 3 e 0.50 BSC b 0.17 0.22 0.27 4, 5 L1 1.00 REF Notes:

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