AT93C46C ATMEL | Alldatasheet

Document overview

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Technical content

Features

  • Low-Voltage and Standard-Voltage Operation – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 2.5 (VCC = 2.5V to 5.5V)
  • 3-Wire Serial Interface
  • Schmitt Trigger, Filtered Inputs for Noise Suppression
  • 2 MHz Clock Rate (5V) Compatibility
  • Self-Timed Write Cycle (10 ms max)
  • High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years – ESD Protection: > 4000V
  • Automotive Grade and Extended Temperature Devices Available
  • 8-Pin PDIP and JEDEC SOIC Packages

Description

The AT93C46C provides 1024 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 64 words of 16 bits each. The device is opti- mized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT93C46C is available in space saving 8-pin PDIP and 8-pin JEDEC packages. The AT93C46C is enabled through the Chip Select pin (CS), and accessed via a 3- wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a READ instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The WRITE cycle is completely self- timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought “high” following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY status of the part. 3-Wire Serial EEPROM 1K (64 x 16) AT93C46C Rev. 1122A–07/98 3-Wire, 1K Serial E 2PROM Pin Configurations Pin Name Function CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND Ground VCC Power Supply NC No Connect DC Don’t Connect 8-Pin PDIP CS SK DI DO VCC DC NC GND 8-Pin SOIC CS SK DI DO VCC DC NC GND

Note: 1. This parameter is characterized and is not 100% tested. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Test Conditions Max Units Conditions C OUT Output Capacitance (DO) 5 pF V OUT = 0V C IN Input Capacitance (CS, SK, DI) 5 pF V IN = 0V

Note: 1. V IL min and VIH max are reference only and are not tested. DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.5V to +5.5V, TAC = 0°C to +70°C, VCC = +2.5V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC1 Supply Voltage 2.5 5.5 V VCC2 Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC Supply Current VCC = 5.0V READ at 1.0 MHz 0.5 2.0 mA WRITE at 1.0 MHz 0.5 2.0 mA ISB1 Standby Current V CC = 2.5V CS = 0V 14.0 20.0 µA ISB2 Standby Current V CC = 2.7V CS = 0V 14.0 20.0 µA ISB3 Standby Current V CC = 5.0V CS = 0V 35.0 50.0 µA IIL Input Leakage V IN = 0V to VCC 0.1 1.0 µA IOL Output Leakage V IN = 0V to VCC 0.1 1.0 µA VIL1 (1) VIH1 (1) Input Low Voltage Input High Voltage 2.5V ≤ VCC ≤ 5.5V -0.6 VCC x 0.7 VCC x 0.3 VCC + 1 V VOL1 VOH1 Output Low Voltage Output High Voltage 4.5V ≤ VCC ≤ 5.5V IOL = 2.1 mA 0.4 V IOH = -0.4 mA 2.4 V VOL2 VOH2 Output Low Voltage Output High Voltage 2.5V ≤ VCC ≤ 2.7V IOL = 0.15 mA 0.2 V IOH = -100 µAV CC - 0.2 V AC Characteristics Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units fSK SK Clock Frequency 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 0.5 MHz tSKH SK High Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 250 250 500 ns tSKL SK Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 250 250 500 ns tCS Minimum CS Low Time 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 250 250 500 ns tCSS CS Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 100 ns

Note: 1. This parameter is characterized and is not 100% tested. tDIS DI Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 100 100 200 ns t CSH CS Hold Time Relative to SK 0 ns tDIH DI Hold Time Relative to SK 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 100 100 200 ns tPD1 Output Delay to ‘1’ AC T est 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 250 250 500 ns tPD0 Output Delay to ‘0’ AC T est 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 250 250 500 ns tSV CS to Status Valid AC T est 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 250 250 500 ns tDF CS to DO in High Impedance AC T est CS = VIL 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 2.5V ≤ VCC ≤ 5.5V 100 100 200 ns tWP Write Cycle Time 0.1 10 ms 4.5V ≤ VCC ≤ 5.5V 1 ms Endurance(1) 5.0V , 25°C, Page Mode 1 M Write Cycle AC Characteristics (Continued) Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units Instruction Set for the AT93C46C Instruction SB Op Code Address Commentsx 16 READ 1 10 A 5 - A0 Reads data stored in memory, at specified address. EWEN 1 00 11XXXX Write enable must precede all programming modes. ERASE 1 11 A 5 - A0 Erase memory location An - A0. WRITE 1 01 A 5 - A0 Writes memory location An - A0. ERAL 1 00 10XXXX Erases all memory locations. Valid only at V CC = 4.5V to 5.5V . WRAL 1 00 01XXXX Writes all memory locations. Valid only at V CC = 4.5V to 5.5V . EWDS 1 00 00XXXX Disables all programming instructions.

The AT93C46C is accessed via a simple and versatile three-wire serial communication interface. Device opera- tion is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic ‘1’) followed by the appropriate Op Code and the desired memory Address location. READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the ris- ing edges of serial clock SK. It should be noted that a dummy bit (logic ‘0’) precedes the 16-bit data output string. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the Erase/Write Enable state, program- ming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or V CC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction pro- grams all bits in the specified memory location to the logical ‘1’ state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS ). A logic ‘1’ at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruc- tion. WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be written into the specified memory location. The self-timed programming cycle t WP starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS ). A logic ‘0’ at DO indicates that programming is still in progress. A logic ‘1’ indicates that the memory loca- tion at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A Ready/Busy Status cannot be obtained if the CS is brought high after the end of the self-timed programming cycle, t WP . ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic ‘1’ state and is primarily used for testing purposes. The DO pin out- puts the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS ). The ERAL instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns spec- ified in the instruction. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS ). The WRAL instruction is valid only at VCC = 5.0V ± 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.

Note: 1. This is the minimum SK period.

EWEN Timing (1) Note: 1. Requires a minimum of nine clock cycles. EWDS Timing (1) Note: 1. Requires a minimum of nine clock cycles. Organization Key for Timing Diagrams I/O AT93C46C x 16 AN A5 D N D 15 CS SK DI DO tCS 11 0 AN ... ... D N D0

WRAL Timing (1)(2) Notes: 1. Valid only at VCC = 4.5V to 5.5V . 2. Requires a minimum of nine clock cycles.

TERAL Timing (1) Note: 1. Valid only at VCC = 4.5V to 5.5V .

Ordering Information

tWP (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package Operation Range 10 2000 50.0 2000 A T93C46C-10PC A T93C46C-10SC 8P3 8S1 Commercial (0°C to 70°C) 10 2000 50.0 2000 A T93C46C-10PI A T93C46C-10SI 8P3 8S1 Industrial (-40°C to 85°C) 10 800 20.0 1000 A T93C46C-10PC-2.7 A T93C46C-10SC-2.7 8P3 8S1 Commercial (0°C to 70°C) 10 800 20.0 1000 A T93C46C-10PI-2.7 A T93C46C-10SI-2.7 8P3 8S1 Industrial (-40°C to 85°C) 10 600 20.0 500 A T93C46C-10PC-2.5 A T93C46C-10SC-2.5 8P3 8S1 Commercial (0°C to 70°C) 10 600 20.0 500 A T93C46C-10PI-2.5 A T93C46C-10SI-2.5 8P3 8S1 Industrial (-40°C to 85°C) Package Type 8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low Voltage (2.7V to 5.5V) -2.5 Low Voltage (2.5V to 5.5V)

.400 (10.16) .355 (9.02) PIN .280 (7.11) .240 (6.10) .037 (.940) .210 (5.33) MAX SEATING PLANE .100 (2.54) BSC .015 (.380) MIN .022 (.559) .014 (.356) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .325 (8.26) .300 (7.62)

15 REF

.430 (10.9) MAX .012 (.305) .008 (.203) .020 (.508) .013 (.330) PIN 1 .157 (3.99) .150 (3.81) .244 (6.20) .228 (5.79) .050 (1.27) BSC .196 (4.98) .189 (4.80) .068 (1.73) .053 (1.35) .010 (.254) .004 (.102) 8 REF .010 (.254) .007 (.203) .050 (1.27) .016 (.406) 8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA 8S1, 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters)