AT93C46A ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Low-voltage and Standard-voltage Operation –2 . 7 ( VCC = 2.7V to 5.5V) –1 . 8 ( VCC = 1.8V to 5.5V)
- Three-wire Serial Interface
- 2 MHz Clock Rate (5V) Compatibility
- Self-timed Write Cycle (10 ms max)
- High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years
- Automotive Grade, Extended Temperature, and Lead-free/Halogen-free Devices Available
- 8-lead PDIP , 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
Description
The AT93C46A provides 1024 bits of serial electrically-erasable programmable read- only memory (EEPROM) organized as 64 word s of 16 bits each. The device is opti- mized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT 93C46A is available in space-saving 8- lead PDIP , 8-lead JEDEC SOIC, and 8-lead TSSOP packages. The AT93C46A is enabled through the Chip Select pin (CS) and accessed via a three- wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output DO pin. The write cycle is completely self-timed and no separate erase cycle is required before write. The write cycle is only enabled when the part is in the erase/write enable state. When CS is brought high following the initiation of a write cycle, the DO pin outputs the ready/busy status of the part. Table 1. Pin Configuration
2 AT93C46A
Figure 1. Block Diagram
64 X 16
Note: This parameter is characterized and is not 100% tested. Note: 1. V IL min and VIH max are reference only and are not tested. Table 2. Pin Capacitance(1) Table 3. DC Characteristics
4 AT93C46A
Note: 1. This parameter is characterized and is not 100% tested. Table 4. AC Characteristics
0539K–SEEPR–2/07 Functional The AT93C46A is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host pro- cessor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the appropriate op code and the desired memory address location. READ (READ): The Read (READ) instruction contains the address code for the mem- ory location to be read. After the instruction and address are decoded, data from the selected memory location is available at th e serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 16-bit data output string. ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or V CC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction pr ograms all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (t CS). A logic “1” at pin DO indicates that the selected memory location has been erased and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contai ns the 16 bits of data to be writ- ten into the specified memory location. The self-timed programming cycle, t WP, starts after the last bit of data is received at se rial data input pin DI. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and th e part is ready for further instructions. A ready/busy status cannot be obtained if the CS is brought high after the end of the self- timed programming cycle, tWP. ERASE ALL (ERAL): The Erase All (ERAL) instructio n programs every bit in the mem- ory array to the logic “1” state and is prim arily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the inst ruction. The DO pin outputs the ready/busy Table 5. Instruction Set for the AT93C46A
6 AT93C46A
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%. Figure 2. Synchronous Data Timing Note: 1. This is the minimum SK period. Table 6. Organization Key for Timing Diagrams
8 AT93C46A
Figure 6. WRITE Timing Figure 7. WRAL Timing(1 ),( 2 ) Notes: 1. Valid only at V CC = 4.5V to 5.5V.
- Requires a minimum of nine clock cycles.
Figure 8. ERASE Timing
Figure 9. ERAL Timing(1) Note: 1. Valid only at V CC = 4.5V to 5.5V.
10 AT93C46A
0539K–SEEPR–2/07 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in Table 3 on page 3 and Table 4 on page 4. Not recommended for new design. Please see AT93C46E datasheet. Ordering Information(1) Ordering Code Package Operation Range AT93C46A-10PU-2.7 AT93C46A-10PU-1.8 AT93C46A-10SU-2.7 AT93C46A-10SU-1.8 AT93C46A-10TU-2.7 AT93C46A-10TU-1.8 8P3 8P3 8S1 8S1 8A2 8A2 Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Small Outline Package (TSSOP) Options −2.7 Low Voltage (2.7V to 5.5V) −1.8 Low Voltage (1.8V to 5.5V)
0539K–SEEPR–2/07 Packaging Information 8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B D E e Lb2 b A2 A N eA c
4 PLCS
(Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. A 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2
12 AT93C46A
0539K–SEEPR–2/07 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L
0539K–SEEPR–2/07 8A2 – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e
14 AT93C46A
0539K–SEEPR–2/07
Revision History
Doc. Rev. Date Comments 0539K 2/2007 Implemented revision history. Added Note to page 1 and ordering information; Not recommended for new design; please refer to AT93C46E datasheet.
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