AT91M43300 ATMEL | Alldatasheet

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Technical content

Features

  • Utilizes the ARM7TDMI™ ARM® Thumb® Processor Core – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-Circuit Emulation)  3K Bytes Internal RAM  Fully-programmable External Bus Interface (EBI) – Maximum External Address Space of 64M Bytes – Up to 8 Chip Selects – Software-programmable 8/16-bit External Data Bus  8-channel Peripheral Data Controller  8-level Priority, Individually-maskable, Vectored Interrupt Controller – 5 External Interrupts, including a High-priority, Low-latency Interrupt Request  58 Programmable I/O Lines  6-channel 16-bit Timer/Counter – 6 External Clock Inputs – 2 Multi-purpose I/O Pins per Channel  3 USARTs – 2 Dedicated Peripheral Data Controller (PDC) Channels per USART – Support for up to 9-bit Data Transfers  Master/Slave SPI Interface – 2 Dedicated Peripheral Data Controller (PDC) Channels – 8- to 16-bit Programmable Data Length – 4 External Slave Chip Selects  Programmable Watchdog Timer  Power Management Controller (PMC) – CPU and Peripherals can be Deactivated Individually  IEEE 1149.1 JTAG Boundary Scan on all Active Pins  Fully Static Operation: 0 Hz to 25 MHz (12 MHz @ 1.8V)  1.8V to 3.6V Core Operating Voltage Range  2.7V to 5.5V I/O Operating Voltage Range  -40° to +85°C Operating Temperature Range  Available in a 144-ball PBGA Package

Description

The AT91M43300 is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and features very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91 ARM-based MCU family also features Atmel ’s high-density, in-system programmable, nonvolatile memory technology. The AT91M43300 has a direct connection to off-chip memory, including Flash, through the fully-programmable External Bus Interface. The AT91M43300 is manufactured using Atmel ’s high-density CMOS technology. By combining the ARM7TDMI microcontroller core with an on-chip SRAM, and a wide range of peripheral functions on a monolithic chip, the AT91M43300 provides a highly- flexible and cost-effective solution to many compute-intensive multi-processor appli- cations. The compact BGA package reduces required board space to an absolute minimum. Rev. 1322A–10/99

Table 1. AT91M43300 Pin Description

Figure 1. AT91M43300 in 144-ball BGA Package (top view)

The AT91M43300 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is opti- mized for low power consumption. The AMBA Bridge pro- vides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPI and the on- and off-chip memories without processor intervention. Most importantly, the PDC removes the processor interrupt handling over- head and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contig- uous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The AT91M43300 peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16K-byte address space allocated in the upper 3M bytes of the 4G byte address space. Except for the interrupt controller, the peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequently- written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writ- ing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modify- write and complex bit manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O controller. The PIO controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO Controller in order to define which peripheral signals are connected with off-chip logic. The ARM7TDMI processor operates in little-endian mode in the AT91M43300 microcontroller. The processor ’s inter- nal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are described in the datasheet entitled “AT91M63200 Datasheet ” (Literature No. 1028). Electrical characteristics for the AT91M43300 are documented in the datasheet “AT91M63200 Electrical and Mechanical Characteristics” (Literature No. 1090). The ARM standard In-Circuit Emulation debug interface is supported via the ICE port of the AT91M43300 via the JTAG/ICE port when JTAGSEL is low. IEEE JTAG bound- ary scan is supported via the JTAG/ICE port when JTAG- SEL is high. PDC: Peripheral Data Controller The AT91M43300 has an 8-channel PDC dedicated to the three on-chip USARTs and to the SPI. One PDC channel is connected to the receiving channel and one to the transmit- ting channel of each peripheral. The user interface of a PDC channel is integrated in the memory space of each USART channel and in the memory space of the SPI. It contains a 32-bit address pointer regis- ter and a 16-bit count register. When the programmed data is transferred, an end-of-transfer interrupt is generated by the corresponding peripheral. See the USART section and the SPI section for more details on PDC operation and pro- gramming. Power Supplies The AT91M43300 has two kinds of power supply pins:  VDDCORE pins, which power the chip core  VDDIO pins, which power the I/O lines This allows core power consumption to be reduced by sup- plying it with a lower voltage than the I/O lines. The VDDCORE pins must never be powered at a voltage greater than the supply voltage applied to the VDDIO pins. Typical supported voltage combinations are shown in the following table: Pins Typical Supply Voltages

Figure 2. AT91M43300

2 PDC

EBI: External Bus Interface The EBI generates the signals that control the access to the external memory or peripheral devices. The EBI is fully programmable and can address up to 64M bytes. It has eight chip selects and a 24-bit address bus, the upper four bits of which are multiplexed with a chip select. The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. The EBI supports different access protocols, allowing sin- gle-clock-cycle memory accesses. The main features are:  External memory mapping  Up to eight chip select lines  8- or 16-bit data bus  Byte-write or byte-select lines  Remap of boot memory  Two different read protocols  Programmable wait state generation  External wait request  Programmable data float time AIC: Advanced Interrupt Controller The AT91M43300 has an 8-level priority, individually- maskable, vectored interrupt controller. This feature sub- stantially reduces the software and real-time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast inter- rupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor ’s NFIQ line can only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to IRQ3. An 8-level priority encoder allows the customer to define the priority between the different NIRQ interrupt sources. Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive- or negative-edge triggered or high- or low-level sensitive. PIO: Parallel I/O Controller The AT91M43300 features 58 programmable I/O lines. 14 pins on the AT91M43300 are dedicated as general-pur- pose I/O pins. Other I/O lines are multiplexed with on-chip peripheral I/O signals in order to optimize the use of avail- able package pins. The I/O lines are controlled by two sep- arate and identical PIO controllers (PIOA and PIOB). Each PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller (AIC). USART: Universal Synchronous/Asynchronous Receiver/Transmitter The AT91M43300 provides three identical, full-duplex, uni- versal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Periph- eral Data Controller. The main features are:  Programmable baud rate generator  Parity, framing and overrun error detection  Line break generation and detection  Automatic echo, local loopback and remote loopback channel modes  Multi-drop mode: address detection and generation  Interrupt generation  Two dedicated Peripheral Data Controller channels  5-, 6-, 7-, 8- and 9-bit character length SPI: Serial Peripheral Interface The AT91M43300 features an SPI that provides communi- cation with external devices in master or slave mode. The SPI has four external chip selects that can be con- nected to up to 15 devices. The data length is programma- ble, from 8- to 16-bit. As for the USART, a two-channel PDC is used to move data directly between memory and the SPI without CPU intervention for maximum real-time processing throughput. TC: Timer/Counter The AT91M43300 features two identical timer/counter blocks, each containing three identical 16-bit timer/counter channels. Each channel can be independently pro- grammed to perform a wide range of functions, including frequency measurement, event counting, interval measure- ment, pulse generation, delay timing and pulse width mod- ulation. Each timer/counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/out- put signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts via the Advanced Interrupt Controller (AIC). Each timer/counter block features two global registers that act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each timer/counter channel, allow- ing them to be chained.

WD: Watchdog Timer The AT91M43300 features an internal Watchdog Timer that can be used to guard against system lock-up if the software becomes trapped in a deadlock. PMC: Power Management Controller The Power Management Controller allows optimization of power consumption. The PMC enables/disables the clock inputs to most of the peripherals as well as to the ARM pro- cessor core. When the ARM core clock is disabled, the current instruc- tion is processed before the clock is stopped. The clock can be re-enabled by any enabled interrupt or by a hard- ware reset. When a peripheral clock is disabled, the clock is immedi- ately stopped. When the clock is re-enabled, the peripheral resumes action where it left off. Due to the static nature of the design, the contents of the on-chip RAM and registers for which the clocks are dis- abled remain unchanged. SF: Special Function The AT91M43300 provides registers that implement the following special functions:  Chip identification  RESET status

Ordering Information

(MHz) Core Operating Voltage I/O Operating Voltage Ordering Code RAM (bytes) Package Operating Temperature Range 25 2.7V to 3.6V 2.7V to 5.5V AT91M43300-25CC 3K BGA 144 Commercial (0°C to 70°C) AT91M43300-25CI Industrial (-40°C to 85°C) 12 1.8V to 3.6V 2.7V to 3.6V AT91M43300-12CC-1.8 Commercial (0°C to 70°C) AT91M43300-12CI-1.8 Industrial (-40°C to 85°C)

Figure 3. 144-ball Ball Grid Array Package

© Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard war- ranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any tim e without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectu al prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel ’s products are not authorized for use as critical components in life support devices or systems. ARM, Thumb, ARM7TDMI, and ARM Powered are trademarks of ARM Limited. All other marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Atmel Headquarters Atmel Operations Corporate Headquarters

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