AT91M40400

AT91M40400_99 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Incorporates the ARM7TDMI™ ARM ® Thumb ® Processor Core – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In Circuit Emulation)  4K Bytes Internal RAM  Fully Programmable External Bus Interface (EBI) – Maximum External Address Space of 64M Bytes – Up to 8 Chip Selects – Software Programmable 8/16-bit External Databus  8-level Priority, Individually Maskable, Vectored Interrupt Controller – 4 External interrupts, including a High-priority Low-latency Interrupt Request  32 Programmable I/O Lines  3-channel 16-bit Timer/Counter – 3 External Clock Inputs – 2 Multi-purpose I/O Pins per Channel  2 USARTs – 2 Dedicated Peripheral Data Controller (PDC) Channels per USART  Programmable Watchdog Timer  Low-power Idle Mode  Fully Static Operation: 0 Hz to 33 MHz  2.7V to 3.6V Operating Range  Available in a 100-lead TQFP Package

Description

The AT91M40400 is a member of the Atmel AT91 16/32-bit Microcontroller family which is based on the ARM7TDMI processor core. This processor has a high-perfor- mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applica- tions. The AT91M40400 features a direct connection to off-chip memory, including Flash, through the fully programmable External Bus Interface (EBI). An eight-level priority vectored interrupt controller, in conjuction with the Peripheral Data Controller signifi- cantly improve the real-time performance of the device. The device is manufactured using Atmel’s high density CMOS technology. By combin- ing the ARM7TDMI microcontroller core with on-chip RAM and a wide range of periph- eral functions on a monolithic chip, the Atmel AT91M40400 is a powerful microcontrol- ler that offers a flexible, cost-effective solution to many compute-intensive embedded control applications. Rev. 0768C–10/99 AT91 ARM ® Thumb ® Microcontrollers AT91M40400

Figure 1. AT91M40400 Pinout (Top View)

Table 1. AT91M40400 Pin Description

Figure 2. AT91M40400

2 PDC

The AT91M40400 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is opti- mized for low power consumption. The AMBA Bridge pro- vides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and the on and off-chip memories without processor intervention. Most importantly, the PDC removes the processor interrupt handling over- head and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64k contig- uous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The AT91M40400 peripherals are designed to be pro- grammed with a minimum number of instructions. Each peripheral has a 16K byte address space allocated in the upper 3M bytes of the 4G byte address space. Except for the interrupt controller, the peripheral base address is the lowest address of its memory space. The peripheral regis- ter set is composed of control, mode, data, status and inter- rupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writ- ing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modify- write and complex bit manipulation instructions and without having to store-disable-restore the interrupt state. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O controller. The PIO con- troller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO Controller in order to define which peripheral signals are connected with off- chip logic. The ARM7TDMI processor operates in little-endian mode in the AT91M40400 microcontroller. The processor’s inter- nal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI Datasheet. The memory map and the on-chip peripherals are described in the sub- sequent sections of this datasheet. Electrical characteris- tics are documented in a separate datasheet entitled “AT91M40400 Electrical and Mechanical Characteristics”. The ARM Standard In-Circuit-Emulation debug interface is supported via the ICE port of the AT91M40400 microcon- troller. (This is not a standard IEEE 1149.1 JTAG Boundary Scan interface) PDC: Peripheral Data Controller The AT91M40400 has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART. The user interface of a PDC channel is integrated in the memory space of each USART channel. It contains a 32-bit address pointer register and a 16-bit byte count register. When the programmed number of bytes are transferred, an end of transfer interrupt is generated by the corresponding USART. See the section describing the USART beginning on page 64 for more details on PDC operation and pro- gramming.

Figure 3. AT91M40400

Figure 4. AT91M40400

cycles just prior to the rising edge of NRST. Boot memory. Boot operation is described on page 13. BMS must be driven to a valid logic value during reset. be programmed after reset like any standard PIO. ing the last 10 clock cycles before the rising edge of NRST. to a valid logic value during reset. serial data transmit line TXD1. out the need for an additional external resistor. computer via an external ICE Interface. JTAG chip ID which identifies the core to the ICE system. This is not IEEE 1149.1 JTAG compliant. Table 2. Boot Mode Select

0 All External 16-bit memory on NCS0

The following table shows how certain EBI signals are multiplexed: Name Description Type A0 - A23 Address bus (output) Output D0 - D15 Data bus (input/output) I/O NCS0 - NCS3 Active low chip selects (output) Output CS4 - CS7 Active high chip selects (output) Output NRD Read Enable (output) Output NWR0 - NWR1 Lower and upper write enable (output) Output NOE Output enable (output) Output NWE Write enable (output) Output NUB, NLB Upper and lower byte select (output) Output NWAIT Wait request (input) Input Multiplexed Signals Functions A23 - A20 CS4 - CS7 Allows from 4 to 8 chip select lines to be used. A0 NLB 8- or 16-bit data bus NRD NOE Byte-write or byte select access NWR0 NWE Byte-write or byte select access NWR1 NUB Byte-write or byte select access

Figure 20. Chip Select Wait

Figures 21 through 24 show examples of the two alternative protocols for external memory read access. Figure 21. Standard Read Protocol with no tDF

Figure 22. Early Read Protocol with no tDF

Figure 23. Standard Read Protocol with tDF

Figure 24. Early Read Protocol with tDF

Table 3. Memory Access Waveforms

Figure 25. 0 Wait States, 16-Bit Bus Width, Word Transfer

Figure 26. 1 Wait, 16-Bit Bus Width, Word Transfer

Figure 27. 1 Wait State, 16-Bit Bus Width, Half Word Transfer

Figure 28. 0 Wait States, 8-Bit Bus Width, Word Transfer

Figure 29. 1 Wait State, 8-Bit Bus Width, Half Word Transfer

Figure 30. 1 Wait State, 8-Bit Bus Width, Byte Transfer

Figure 31. 0 Wait States, 16-Bit Bus Width, Byte Transfer

the number of active chip selects and data read protocol. ferent base address, even for unused chip selects.

1. 16-Bit boot (if BMS is detected low)

Table 4. EBI Memory Map

Register Name: EBI_CSR0 - EBI_CSR7 Access Type: Read/Write Reset Value: See Table 4 Absolute Address: 0xFFE00000 - 0xFFE0001C  DBW: Data Bus Width  NWS: Number of Wait States This field is valid only if WSE is set.  WSE: Wait State Enable 0 = Wait state generation is disabled. No wait states are inserted. 1 = Wait state generation is enabled. 31 30 29 28 27 26 25 24 BA 23 22 21 20 19 18 17 16 BA -- -- -- -- 15 14 13 12 11 10 9 8 -- -- CSEN BAT TDF PAGES 76543210 PAGES -- WSE NWS DBW DBW Data Bus Width 0 0 Reserved 0 1 16-bit data bus width 1 0 8-bit data bus width

11 R e s e r v e d

 PAGES: Page Size  TDF: Data Float Output Time  BAT: Byte Access Type 0 = Byte write access type. 1 = Byte select access type.  CSEN: Chip Select Enable 0 = Chip select is disabled. 1 = Chip select is enabled.  BA: Base Address These bits contain the highest bits of the base address. If the page size is larger than 1Mbyte, the unused bits of the base address are ignored by the EBI decoder. PAGES Page Size Active bits in base address 0 0 1M byte 12 bits (31-20) 0 1 4M bytes 10 bits (31-22) 1 0 16M bytes 8 bits (31-24) 1 1 64M bytes 6 bits (31-26) TDF Number of Cycles added after the transfer 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7

EBI Remap Control Register Register Name: EBI_RCR Access Type: Write only Absolute Address: 0xFFE00020  RCB: Remap Command Bit 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices. EBI Memory Control Register Register Name: EBI_MCR Access Type: Read/Write Reset Value: See Table 4 Absolute Address: 0xFFE00024  ALE: Address Line Enable This field determines the number of valid address lines and the number of valid chip select lines.  DRP: Data Read Protocol 0 = Standard read protocol for all external memory devices enabled. 1 = Early read protocol for all external memory devices enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 --- --- --- DRP --- ALE ALE Valid Address Bits Maximum Addressable Space Valid Chip Select

0 X X A20, A21, A22, A23 16M bytes none

1 0 0 A20, A21, A22 8M bytes CS4 1 0 1 A20, A21 4M bytes CS4, CS5 1 1 0 A20 2M bytes CS4, CS5, CS6 1 1 1 none 1M bytes CS4, CS5, CS6, CS7

handling internal and external interrupts. external interrupt request lines: IRQ0 to IRQ2. the priority between the different NIRQ interrupt sources. grammable registers in Table 6. Figure 32. Interrupt Controller Block Diagram by the peripheral before being used.

Note: 1. Reserved interrupt sources are not available. Corresponding registers must not be used and read 0. Table 5. AIC Interrupt Sources

0 FIQ Fast Interrupt

1 SWIRQ Software Interrupt

2 US0IRQ USART Channel 0 interrupt

3 US1IRQ USART Channel 1 interrupt

4 TC0IRQ Timer Channel 0 interrupt

5 TC1IRQ Timer Channel 1 interrupt

6 TC2IRQ Timer Channel 2 interrupt

7 WDIRQ Watchdog interrupt

8 PIOIRQ Parallel I/O Controller interrupt

16 IRQ0 External interrupt 0

17 IRQ1 External interrupt 1

18 IRQ2 External interrupt 2

Hardware Interrupt Vectoring The hardware interrupt vectoring reduces the number of instructions to reach the interrupt handler to only one. By storing the following instruction at address 0x00000018, the processor loads the program counter with the interrupt handler address stored in the AIC_IVR register. Execution is then vectored to the interrupt handler corresponding to the current interrupt. ldr PC,[PC,# -&F20] The current interrupt is the interrupt with the highest priority when the Interrupt Vector Register (AIC_IVR) is read. The value read in the AIC_IVR corresponds to the address stored in the Source Vector Register (AIC_SVR) of the cur- rent interrupt. Each interrupt source has its corresponding AIC_SVR. In order to take advantage of the hardware inter- rupt vectoring it is necessary to store the address of each interrupt handler in the corresponding AIC_SVR, at system initialization. Priority Controller The NIRQ line is controlled by an 8-level priority encoder. Each source has a programmable priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest. When the AIC receives more than one unmasked interrupt at a time, the interrupt with the highest priority is serviced first. If both interrupts have equal priority, the interrupt with the lowest interrupt source number (see table 5) is serviced first. The current priority level is defined as the priority level of the current interrupt at the time the register AIC_IVR is read (the interrupt which will be serviced). In the case when a higher priority unmasked interrupt occurs while an interrupt already exists, there are two pos- sible outcomes depending on whether the AIC_IVR has been read.  If the NIRQ line has been asserted but the AIC_IVR has not been read, then the processor will read the new higher priority interrupt handler address in the AIC_IVR register and the current interrupt level is updated.  If the processor has already read the AIC_IVR then the NIRQ line is reasserted. When the processor has authorized nested interrupts to occur and reads the AIC_IVR again, it reads the new, higher priority interrupt handler address. At the same time the current priority value is pushed onto a first-in last-out stack and the current priority is updated to the higher priority. When the end of interrupt command register (AIC_EOICR) is written the current interrupt level is updated with the last stored interrupt level from the stack (if any). Hence at the end of a higher priority interrupt, the AIC returns to the pre- vious state corresponding to the preceding lower priority interrupt which had been interrupted. Interrupt Handling The interrupt handler must read the AIC_IVR as soon as possible. This de-asserts the NIRQ request to the proces- sor and clears the interrupt in case it is programmed to be edge triggered. This permits the AIC to assert the NIRQ line again when a higher priority unmasked interrupt occurs. At the end of the interrupt service routine, the end of inter- rupt command register (AIC_EOICR) must be written. This allows pending interrupts to be serviced. Interrupt Masking Each interrupt source, including FIQ, can be enabled or disabled using the command registers AIC_IECR and AIC_IDCR. The interrupt mask can be read in the read only register AIC_IMR. A disabled interrupt does not affect the servicing of other interrupts. Interrupt Clearing and Setting All interrupt sources which are programmed to be edge trig- gered (including FIQ) can be individually set or cleared by respectively writing to the registers AIC_ISCR and AIC_ICCR. This function of the interrupt controller is avail- able for auto-test or software debug purposes. Fast Interrupt Request The external FIQ line is the only source which can raise a fast interrupt request to the processor. Therefore it has no priority controller. The external FIQ line can be programmed to be positive or negative edge triggered or high or low level sensitive in the AIC_SMR0 register. The fast interrupt handler address can be stored in the AIC_SVR0 register. The value written into this register is available by reading the AIC_FVR register when an FIQ interrupt is raised. By storing the following instruction at address 0x0000001C, the processor will load the program counter with the interrupt handler address stored in the AIC_FVR register. ldr PC,[PC,# -&F20] Alternatively the interrupt handler can be stored starting from address 0x0000001C as described in the ARM7TDMI datasheet. Software Interrupt Interrupt source 1 of the advanced interrupt controller is a software interrupt. It must be programmed to be edge trig- gered in order to set or clear it by writing to the AIC_ISCR and AIC_ICCR. This is totally independent of the SWI instruction of the ARM7TDMI processor.

When the AIC asserts the NIRQ line, the ARM7TDMI enters IRQ mode and the interrupt handler reads the IVR. It may happen that the AIC de-asserts the NIRQ line after the core has taken into account the NIRQ assertion and before the read of the IVR. This behavior is called a Spurious Interrupt. The AIC is able to detect these Spurious Interrupts and returns the Spurious Vector when the IVR is read. The Spu- rious Vector can be programmed by the user when the vec- tor table is initialized. A spurious interrupt may occur in the following cases:  With any sources programmed to be level sensitive, if the interrupt signal of the AIC input is de-asserted at the same time as it is taken into account by the ARM7TDMI.  If an interrupt is asserted at the same time as the software is disabling the corresponding source through AIC_IDCR (this can happen due to the pipelining of the ARM core). The same mechanism of spurious interrupt occurs if the ARM7TDMI reads the IVR (application software or ICE) when there is no interrupt pending. This mechanism is also valid for the FIQ interrupts. Once the AIC enters the spurious interrupt management, it asserts neither the NIRQ nor the NFIQ lines to the ARM7TDMI as long as the spurious interrupt is not acknowledged. Therefore, it is mandatory for the Spurious Interrupt Service Routine to acknowledge the “spurious” behavior by writing to the AIC_EOICR (End of Interrupt) before returning to the interrupted software. It also can per- form other operation(s), e.g. trace possible undesirable behavior. Protect Mode The Protect Mode permits reading of the Interrupt Vector Register without performing the associated automatic oper- ations. This is necessary when working with a debug sys- tem. When a Debug Monitor or an ICE reads the AIC User Inter- face, the IVR could be read. This would have the following consequences in normal mode:  If an enabled interrupt with a higher priority than the current one is pending, it would be stacked.  If there is no enabled pending interrupt, the spurious vector would be returned. In either case, an End of Interrupt Command would be nec- essary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system. Hence the debug system would become strongly intrusive, and could cause the application to enter an undesired state. This is avoided by using Protect Mode. The Protect Mode is enabled by setting the AIC bit in the SF Protect Mode Register (see SF: Special Function Reg- isters on page 145). When Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Inter- rupt Status Register (AIC_ISR), is updated with the current interrupt only when IVR is written. An AIC_IVR read on its own (e.g. by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads performed in between the read and the write can cause unpredictable results. Therefore, it is strongly recommended not to set a breakpoint between these 2 actions, nor to stop the software. The debug system must not write to the AIC_IVR as this would cause undesirable effects. The following table shows the main steps of an interrupt and the order in which they are performed according to the mode: Notes: 1. NIRQ de-assertion and automatic interrupt clearing if the source is programmed as level sensitive 2. Note that software which has been written and debugged using Protect Mode will run correctly in Normal Mode without modification. However in Nor- mal Mode the AIC_IVR write has no effect and can be removed to optimize the code. Action Normal Mode Protect Mode Calculate active interrupt (higher than current or spurious) Read AIC_IVR Read AIC_IVR Determine and return the vector of the active interrupt Read AIC_IVR Read AIC_IVR Memorize interrupt Read AIC_IVR Read AIC_IVR Push on internal stack the current priority level Read AIC_IVR Write AIC_IVR Acknowledge the interrupt (1) Read AIC_IVR Write AIC_IVR No effect (2) Write AIC_IVR ---

Note: 1. The reset value of this register depends on the level of the External IRQ lines. All other sources are cleared at reset. Table 6. AIC Memory Map

Register Name: AIC_SMR0 - AIC_SMR31 Access Type: Read/Write Reset Value: 0  PRIOR: Priority Level Program the priority level for all sources except source 0 (FIQ). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ, in the SMR0.  SRCTYPE: Interrupt Source Type Program the input to be positive or negative edge triggered or positive or negative level sensitive. The active level or edge is not programmable for the internal sources. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 --- SRCTYPE --- --- PRIOR SRCTYPE Internal Sources External Sources 0 0 Level Sensitive Low Level Sensitive 0 1 Edge T riggered Negative Edge Triggered 1 0 Level Sensitive High Level Sensitive 1 1 Edge T riggered Positive Edge Triggered

AIC Source Vector Register Register Name: AIC_SVR0 - AIC_SVR31 Access Type: Read/Write Reset Value: 0  VECTOR: Interrupt Handler Address The user may store in these registers the addresses of the corresponding handler for each interrupt source. 31 30 29 28 27 26 25 24 VECTOR 23 22 21 20 19 18 17 16 VECTOR 15 14 13 12 11 10 9 8 VECTOR 76543210 VECTOR

AIC Interrupt Vector Register Register Name: AIC_IVR Access Type: Read only Reset Value: 0  IRQV: Interrupt Vector Register The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register (1 to 31) is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the IRQ Vector Register reads 0. AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Read only Reset Value: 0  FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0 which corre- sponds to FIQ. 31 30 29 28 27 26 25 24 IRQV 23 22 21 20 19 18 17 16 IRQV 15 14 13 12 11 10 9 8 IRQV 76543210 IRQV 31 30 29 28 27 26 25 24 FIQV 23 22 21 20 19 18 17 16 FIQV 15 14 13 12 11 10 9 8 FIQV 76543210 FIQV

AIC Interrupt Status Register Register Name: AIC_ISR Access Type: Read only Reset Value: 0  IRQID: Current IRQ Identifier The Interrupt Status Register returns the current interrupt source number. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 --- --- --- IRQID

AIC Interrupt Pending Register Register Name: AIC_IPR Access Type: Read only Reset Value: 0  Interrupt Pending 0 = Corresponding interrupt is inactive. 1 = Corresponding interrupt is pending. AIC Interrupt Mask Register Register Name: AIC_IMR Access Type: Read only Reset Value: 0  Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 --- --- --- --- --- IRQ2 IRQ1 IRQ0 15 14 13 12 11 10 9 8 76543210 WDIRQ TC2IRQ TC1IRQ TC0IRQ US1IRQ US0IRQ SWIRQ FIQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 --- --- --- --- --- IRQ2 IRQ1 IRQ0 15 14 13 12 11 10 9 8 76543210 WDIRQ TC2IRQ TC1IRQ TC0IRQ US1IRQ US0IRQ SWIRQ FIQ

AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read only Reset Value: 0  NFIQ: NFIQ Status 0 = NFIQ line inactive. 1 = NFIQ line active.  NIRQ: NIRQ Status 0 = NIRQ line inactive. 1 = NIRQ line active. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

AIC Interrupt Enable Command Register Register Name: AIC_IECR Access Type: Write only  Interrupt Enable 0 = No effect. 1 = Enables corresponding interrupt. AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: Write only  IS1 - IS31: Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 --- --- --- --- --- IRQ2 IRQ1 IRQ0 15 14 13 12 11 10 9 8 76543210 WDIRQ TC2IRQ TC1IRQ TC0IRQ US1IRQ US0IRQ SWIRQ FIQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 --- --- --- --- --- IRQ2 IRQ1 IRQ0 15 14 13 12 11 10 9 8 76543210 WDIRQ TC2IRQ TC1IRQ TC0IRQ US1IRQ US0IRQ SWIRQ FIQ

AIC Interrupt Clear Command Register Register Name: AIC_ICCR Access Type: Write only  Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt. AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: Write only  Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 --- --- --- --- --- IRQ2 IRQ1 IRQ0 15 14 13 12 11 10 9 8 76543210 WDIRQ TC2IRQ TC1IRQ TC0IRQ US1IRQ US0IRQ SWIRQ FIQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 --- --- --- --- --- IRQ2 IRQ1 IRQ0 15 14 13 12 11 10 9 8 76543210 WDIRQ TC2IRQ TC1IRQ TC0IRQ US1IRQ US0IRQ SWIRQ FIQ

AIC End of Interrupt Command Register Register Name: AIC_EOICR Access Type: Write only The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. AIC Spurious Vector Register Register Name: AIC_SPU Access Type: Read/Write Reset Value: 0  SPUVEC: Spurious Interrupt Vector Handler Address The user may store the address of the spurious interrupt handler in this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 31 30 29 28 27 26 25 24 SPUVEC 23 22 21 20 19 18 17 16 SPUVEC 15 14 13 12 11 10 9 8 SPUVEC 76543210 SPUVEC

Standard Interrupt Sequence It is assumed that:  The Advanced Interrupt Controller has been programmed, AIC_SVR are loaded with corresponding interrupt service routine addresses and interrupts are enabled.  The Instruction at address 0x18(IRQ exception vector address) is ldr pc, [pc, #-&F20] When NIRQ is asserted, if the bit I of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the IRQ link register (r14_irq) and the Program Counter (r15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts r14_irq, decrementing it by 4. 2. The ARM core enters IRQ mode, if it is not already. 3. When the instruction loaded at address 0x18 is exe- cuted, the Program Counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the fol- lowing effects: set the current interrupt to be the pending one with the highest priority. The current level is the priority level of the current interrupt. de-assert the NIRQ line on the processor. (Even if vec- toring is not used, AIC_IVR must be read in order to de-assert NIRQ) automatically clear the interrupt, if it has been pro- grammed to be edge triggered push the current level on to the stack return the value written in the AIC_SVR corresponding to the current interrupt 4. The previous step has effect to branch to the corre- sponding interrupt service routine. This should start by saving the Link Register(r14_irq) and the SPSR(SPSR_irq). Note that the Link Register must be decremented by 4 when it is saved, if it is to be restored directly into the Program Counter at the end of the interrupt. 5. Further interrupts can then be unmasked by clear- ing the I bit in the CPSR, allowing re-assertion of the NIRQ to be taken into account by the core. This can occur if an interrupt with a higher priority than the current one occurs. 6. The Interrupt Handler can then proceed as required, saving the registers which will be used and restoring them at the end. During this phase, an interrupt of priority higher than the current level will restart the sequence from step 1. Note that if the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. The I bit in the CPSR must be set in order to mask interrupts before exiting, to ensure that the interrupt is completed in an orderly manner. 8. The End Of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than old current level but with higher priority than the new current level, the NIRQ line is re-asserted, but the interrupt sequence does not immediately start because the I bit is set in the core. 9. The SPSR (SPSR_irq) is restored. Finally, the saved value of the Link Register is restored directly into the PC. This has effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in the SPSR (the previous state of the ARM core). Note: The I bit in the SPSR is significant. If it is set, it indi- cates that the ARM core was just about to mask IRQ inter- rupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the mask instruction is com- pleted (IRQ is masked).

It is assumed that:  The Advanced Interrupt Controller has been programmed, AIC_SVR[0] is loaded with fast interrupt service routine address and the fast interrupt is enabled.  The Instruction at address 0x1C(FIQ exception vector address) is:  ldr pc, [pc, #-&F20].  Nested Fast Interrupts are not needed by the user. When NFIQ is asserted, if the bit F of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the Program Counter is loaded in the FIQ link register (r14_fiq) and the Program Counter (r15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts r14_fiq, decrementing it by 4. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the Program Counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt (source 0 connected to the FIQ line), if it has been programmed to be edge triggered. In this case only, it de-asserts the NFIQ line on the processor. 4. The previous step has effect to branch to the corre- sponding interrupt service routine. It is not neces- sary to save the Link Register(r14_fiq) and the SPSR(SPSR_fiq) if nested fast interrupts are not needed. 5. The Interrupt Handler can then proceed as required. It is not necessary to save registers r8 to r13 because FIQ mode has its own dedicated regis- ters and the user r8 to r13 are banked. The other registers, r0 to r7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the NFIQ line. 6. Finally, the Link Register (r14_fiq) is restored into the PC after decrementing it by 4 (with instruction sub pc, lr, #4 for example). This has effect of return- ing from the interrupt to whatever was being exe- cuted before, and of loading the CPSR with the SPSR, masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The F bit in the SPSR is significant. If it is set, it indi- cates that the ARM core was just about to mask FIQ inter- rupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked).

PIO: Parallel I/O Controller The AT91M40400 has 32 programmable I/O lines. Six pins on the AT91M40400 are dedicated as general purpose I/O pins (P16, P17, P18, P19, P23 and P24). Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins (see Table 7). The PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller. Multiplexed I/O Lines Some I/O lines are multiplexed with an I/O signal of a peripheral. After reset, the pin is generally controlled by the PIO Controller and is in input mode. Table 7 indicates which of these pins are not controlled by the PIO Controller after reset. When a peripheral signal is not used in an application, the corresponding pin can be used as a parallel I/O. Each par- allel I/O line is bi-directional, whether the peripheral defines the signal as input or output. Figure 33 shows the multiplex- ing of the peripheral signals with Parallel I/O signals. If a pin is multiplexed between the PIO Controller and a peripheral, the pin is controlled by the registers PIO_PER (PIO Enable) and PIO_PDR (PIO Disable). The register PIO_PSR (PIO Status) indicates whether the pin is con- trolled by the corresponding peripheral or by the PIO Con- troller. If a pin is a general-purpose parallel I/O pin (not multi- plexed with a peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the bits corresponding to these pins. When the PIO is selected, the peripheral input line is con- nected to zero. Output Selection The user can enable each individual I/O signal as an output with the registers PIO_OER (Output Enable) and PIO_ODR (Output Disable). The output status of the I/O signals can be read in the register PIO_OSR (Output Sta- tus). The direction defined has effect only if the pin is con- figured to be controlled by the PIO Controller. I/O Levels Each pin can be configured to be driven high or low. The level is defined in four different ways, according to the fol- lowing conditions. If a pin is controlled by the PIO Controller and is defined as an output (see Output Selection above), the level is pro- grammed using the registers PIO_SODR (Set Output Data) and PIO_CODR (Clear Output Data). In this case, the pro- grammed value can be read in PIO_ODSR (Output Data Status). If a pin is controlled by the PIO Controller and is not defined as an output, the level is determined by the external circuit. If a pin is not controlled by the PIO Controller, the state of the pin is defined by the peripheral (see peripheral datasheets). In all cases, the level on the pin can be read in the register PIO_PDSR (Pin Data Status). Filters Optional input glitch filtering is available on each pin and is controlled by the registers PIO_IFER (Input Filter Enable) and PIO_IFDR (Input Filter Disable). The input glitch filter- ing can be selected whether the pin is used for its periph- eral function or as a parallel I/O line. The register PIO_IFSR (Input Filter Status) indicates whether or not the filter is activated for each pin. Interrupts Each parallel I/O can be programmed to generate an inter- rupt when a level change occurs. This is controlled by the PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Dis- able) registers which enable/disable the I/O interrupt by setting/clearing the corresponding bit in the PIO_IMR. When a change in level occurs, the corresponding bit in the PIO_ISR (Interrupt Status) is set whether the pin is used as a PIO or a peripheral and whether it is defined as input or output. If the corresponding interrupt in PIO_IMR (Interrupt Mask) is enabled, the PIO interrupt is asserted. When PIO_ISR is read, the register is automatically cleared. User Interface Each individual I/O is associated with a bit position in the Parallel I/O user interface registers. Each of these registers are 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero.

Figure 33. Parallel I/O Multiplexed with a Bi-directional Signal

Note: 1. Bit number refers to the data bit which corresponds to this signal in each of the User Interface registers. Table 7. Multiplexed Parallel I/Os

0 P0 TCLK0 Timer 0 Clock signal input PIO Input 49

1 P1 TIOA0 Timer 0 Signal A bi-directional PIO Input 50

2 P2 TIOB0 Timer 0 Signal B bi-directional PIO Input 51

3 P3 TCLK1 Timer 1 Clock signal input PIO Input 54

4 P4 TIOA1 Timer 1 Signal A bi-directional PIO Input 55

5 P5 TIOB1 Timer 1 Signal B bi-directional PIO Input 56

6 P6 TCLK2 Timer 2 Clock signal input PIO Input 57

7 P7 TIOA2 Timer 2 Signal A bi-directional PIO Input 58

8 P8 TIOB2 Timer 2 Signal B bi-directional PIO Input 59

9 P9 IRQ0 External Interrupt 0 input PIO Input 60

10 P10 IRQ1 External Interrupt 1 input PIO Input 63

11 P11 IRQ2 External Interrupt 2 input PIO Input 64

12 P12 FIQ Fast Interrupt input PIO Input 66

13 P13 SCK0 USART 0 clock signal bi-directional PIO Input 67

14 P14 TXD0 USART 0 transmit data signal output PIO Input 68

15 P15 RXD0 USART 0 receive data signal input PIO Input 69

16 P16 –– – PIO Input 70

17 P17 –– – PIO Input 71

18 P18 –– – PIO Input 72

19 P19 –– – PIO Input 73

20 P20 SCK1 USART 1 clock signal bi-directional PIO Input 74

21 P21 TXD1 USART 1 transmit data signal output PIO Input 75

22 P22 RXD1 USART 1 receive data signal input PIO Input 76

23 P23 –– – PIO Input 83

24 P24 –– – PIO Input 84

25 P25 MCKO Master Clock Output output MCKO 85

26 P26 NCS2 Chip Select 2 output NCS2 99

27 P27 NCS3 Chip Select 3 output NCS3 100

28 P28 A20/CS7 Address 20/Chip Select 7 output A20 25

29 P29 A21/CS6 Address 21/Chip Select 6 output A21 26

30 P30 A22/CS5 Address 22/Chip Select 5 output A22 29

31 P31 A23/CS4 Address 23/Chip Select 4 output A23 30

Notes: 1. The reset value of this register depends on the level of the external pins at reset.

1. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes

have occurred on any pins between the reset and the read. Table 8. PIO Controller Memory Map

Register Name: PIO_PER Access Type: Write only This register is used to enable individual pins to be controlled by the PIO Controller instead of the associated peripheral. When the PIO is enabled, the associated peripheral input (if any) is held at logic zero. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 0 = No effect. PIO Disable Register Register Name: PIO_PDR Access Type: Write Only This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral func- tion is enabled on the corresponding pin. 1 = Disables PIO control (enables peripheral control) on the corresponding pin. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

Register Name: PIO_PSR Access Type: Read only Reset Value: 0x01FFFFFF This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or dis- abled. 1 = PIO is active on the corresponding line (peripheral is inactive). 0 = PIO is inactive on the corresponding line (peripheral is active). 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Output Enable Register Register Name: PIO_OER Access Type: Write only This register is used to enable PIO output drivers. If the pin is driven by a peripheral, this has no effect on the pin, but the information is stored. The register is programmed as follows: 1 = Enables the PIO output on the corresponding pin. 0 = No effect. PIO Output Disable Register Register Name: PIO_ODR Access Type: Write only This register is used to disable PIO output drivers. If the pin is driven by the peripheral, this has no effect on the pin, but the information is stored. The register is programmed as follows: 1 = Disables the PIO output on the corresponding pin. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Output Status Register Register Name: PIO_OSR Access Type: Read only Reset Value: 0 This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows: 1 = The corresponding PIO is output on this line. 0 = The corresponding PIO is input on this line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Input Filter Enable Register Register Name: PIO_IFER Access Type: Write only This register is used to enable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is pro- grammed as follows: 1 = Enables the glitch filter on the corresponding pin. 0 = No effect. PIO Input Filter Disable Register Register Name: IO_IFDR Access Type: Write only This register is used to disable input glitch filters. It affects the pin whether or not the PIO is enabled. The register is pro- grammed as follows: 1 = Disables the glitch filter on the corresponding pin. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Input Filter Status Register Register Name: PIO_IFSR Access Type: Read only Reset Value: 0 This register indicates which pins have glitch filters selected. It is updated when PIO outputs are enabled or disabled by writing to PIO_IFER or PIO_IFDR. 1 = Filter is selected on the corresponding input (peripheral and PIO). 0 = Filter is not selected on the corresponding input. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Set Output Data Register Register Name: PIO_SODR Access Type: Write only This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is set. 0 = No effect. PIO Clear Output Data Register Register Name: PIO_CODR Access Type: Write only This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is cleared. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Output Data Status Register Register Name: PIO_ODSR Access Type: Read only Reset Value: 0 This register shows the output data status which is programmed in PIO_SODR or PIO_CODR. The defined value is effec- tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output. 1 = The output data for the corresponding line is programmed to 1. 0 = The output data for the corresponding line is programmed to 0. PIO Pin Data Status Register Register Name: PIO_PDSR Access Type: Read only Reset Value: Undefined This register shows the state of the physical pin of the chip. The pin values are always valid regardless of whether the pins are enabled as PIO, peripheral, input or output. The register reads as follows: 1 = The corresponding pin is at logic 1. 0 = The corresponding pin is at logic 0. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Interrupt Enable Register Register Name: PIO_IER Access Type: Write only This register is used to enable PIO interrupts on the corresponding pin. It has effect whether PIO is enabled or not. 1 = Enables an interrupt when a change of logic level is detected on the corresponding pin. 0 = No effect. PIO Interrupt Disable Register Register Name: PIO_IDR Access Type: Write only This register is used to disable PIO interrupts on the corresponding pin. It has effect whether the PIO is enabled or not. 1 = Disables the interrupt on the corresponding pin. Logic level changes are still detected. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

PIO Interrupt Mask Register Register Name: PIO_IMR Access Type: Read Only Reset Value: 0 This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR. 1 = Interrupt is enabled on the corresponding input pin. 0 = Interrupt is not enabled on the corresponding input pin. PIO Interrupt Status Register Register Name: PIO_ISR Access Type: Read only Reset Value: 0 This register indicates for each pin when a logic value change has been detected (rising or falling edge). This is valid whether the PIO is selected for the pin or not and whether the pin is an input or output. The register is reset to zero following a read, and at reset. 1 = At least one change has been detected on the corresponding pin since the register was last read. 0 = No change has been detected on the corresponding pin since the register was last read. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 76543210 P7 P6 P5 P4 P3 P2 P1 P0

Figure 34. USART Block Diagram before enabling the transmitter or receiver.

Baud Rate clock) to both the Receiver and the Transmitter. internal clock sources. The external clock source is SCK. MCKI or the master clock divided by 8 (MCKI/8). least 2.5 times lower than the system clock. US_BRGR is set to 0, the Baud Rate Clock is disabled. Baud Rate Clock is disabled. Figure 35. Baud Rate Generator

1 Baud Rate

The parity bit is set according to the PAR field in US_MR. it is transferred to the Shift Register as soon as it is empty. is detected with a parity bit set to identify an address byte. fying a data byte, PARE is not set. a Send Address Command (SENDA) is written to US_CR. have the parity bit cleared. Figure 39. Synchronous and Asynchronous Modes: Character Transmission

A break condition is a low signal level which has a duration of at least one character (including start/stop bits and par- ity). Transmit Break The transmitter generates a break condition on the TXD line when STTBRK is set in US_CR (Control Register). In this case, the character present in the Transmit Shift Regis- ter is completed before the line is held low. To cancel a break condition on the TXD line, the STPBRK command in US_CR must be set. The USART completes a minimum break duration of one character length. The TXD line then returns to high level (idle state) for at least 12 bit periods to ensure that the end of break is correctly detected. Then the transmitter resumes normal operation. The BREAK is managed like a character:  The STTBRK and the STPBRK commands are performed only if the transmitter is ready (bit TXRDY = 1 in US_CSR)  The STTBRK command blocks the transmitter holding register (bit TXRDY is cleared in US_CSR) until the break has started  A break is started when the Shift Register is empty (any previous character is fully transmitted). TXEMPTY is cleared in US_CSR. The break blocks the transmitter shift register until it is completed (high level for at least 12 bit periods after the STPBRK command is requested) In order to avoid unpredictable states:  STTBRK and STPBRK commands must not be requested at the same time  Once an STTBRK command is requested, further STTBRK commands are ignored until the BREAK is ended (high level for at least 12 bit periods)  All STPBRK commands requested without a previous STTBRK command are ignored  A byte written into the Transmit Holding Register while a break is pending but not started (US_CSR.TXRDY = 0) is ignored  It is not permitted to write new data in the Transmit Holding Register while a break is in progress (STPBRK has not been requested), even though TXRDY = 1 in US_CSR.  A new STTBRK command must not be issues until an existing break has ended (TXEMPTY= 1 in US_CSR) The standard break transmission sequence is: 1. Wait for the transmitter ready (US_CSR.TXRDY = 1) 2. Send the STTBRK command (write 0x0200 to US_CR) 3. Wait for the transmitter ready (TXRDY = 1 in US_CSR) 4. Send the STPBRK command (write 0x0400 to US_CR) The next byte can then be sent: 5. Wait for the transmitter ready (TXRDY = 1 in US_CSR) 6. Send the next byte (write byte to US_THR) Each of these steps can be scheduled by using the inter- rupt if the bit TXRDY in US_IMR is set. For character transmission, the USART channel must be enabled before sending a break. Receive Break The receiver detects a break condition when all data, parity and stop bits are low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or at least one sample in synchronous operating mode. RXBRK is also asserted when an end of break is detected. Both the beginning and the end of a break can be detected by interrupt if the bit US_IMR.RXBRK is set. Peripheral Data Controller Each USART channel is closely connected to a corre- sponding Peripheral Data Controller channel. One is dedi- cated to the receiver. The other is dedicated to the trans- mitter. The PDC channel is programmed using US_TPR (Transmit Pointer) and US_TCR (Transmit Counter) for the transmit- ter and US_RPR (Receive Pointer) and US_RCR (Receive Counter) for the receiver. The status of the PDC is given in US_CSR by the ENDTX bit for the transmitter and by the ENDRX bit for the receiver. The pointer registers (US_TPR and US_RPR) are used to store the address of the transmit or receive buffers. The counter registers (US_TCR and US_RCR) are used to store the size of these buffers. The receiver data transfer is triggered by the RXRDY bit and the transmitter data transfer is triggered by TXRDY. When a transfer is performed, the counter is decremented and the pointer is incremented. When the counter reaches 0, the status bit is set (ENDRX for the receiver, ENDTX for the transmitter in US_CSR) which can be programmed to generate an interrupt. Transfers are then disabled until a new non-zero counter value is programmed.

status of the corresponding bits. US_IMR, the interrupt line is asserted. ent test modes, using the field CHMODE in US_MR. Automatic echo mode allows bit by bit re-transmission. line. Programming the transmitter has no effect. pin is held high, as in idle state. Figure 40. Channel Modes

Table 9. USART Memory Map

Name: US_CR Access Type: Write only  RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset.  RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset.  RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0.  RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled.  TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0.  TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled.  RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR.  STTBRK: Start Break 0 = No effect. 1 = If break is not being transmitted, start transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted.  STPBRK: Stop Break 0 = No effect. 1 = If a break is being transmitted, stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods.  STTTO: Start Time-out 0 = No effect. 1 = Start waiting for a character before clocking the time-out counter.  SENDA: Send Address 0 = No effect. 1 = In Multi-drop Mode only, the next character written to the US_THR is sent with the address bit set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 --- --- --- SENDA STTTO STPBRK STTBRK RSTSTA 76543210 TXDIS TXEN RXDIS RXEN RSTTX RSTRX --- ---

Name: US_MR Access Type: Read/Write  USCLKS: Clock Selection (Baud Rate Generator Input Clock)  CHRL: Character Length Start, stop and parity bits are added to the character length.  SYNC: Synchronous Mode Select 0 = USART operates in Asynchronous Mode. 1 = USART operates in Synchronous Mode.  PAR: Parity Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHMODE NBSTOP PAR SYNC 76543210 CHRL USCLKS --- --- --- --- USCLKS Selected Clock

00 M C K I

1 X External (SCK)

00 F i v e b i t s

01 S i x b i t s

000 E v e n P a r i t y

001 O d d P a r i t y

0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multi-drop mode

 NBSTOP: Number of Stop Bits The interpretation of the number of stop bits depends on SYNC.  CHMODE: Channel Mode  CKLO: Clock Output Select 0 = The USART does not drive the SCK pin. 1 = The USART drives the SCK pin if USCLKS[1] is 0. NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved CHMODE Mode Description

00 Normal Mode

The USART Channel operates as an Rx/Tx USART .

01 Automatic Echo

Receiver Data Input is connected to the TXD pin.

10 Local Loopback

Transmitter Output Signal is connected to Receiver Input Signal.

11 Remote Loopback

RXD pin is internally connected to TXD pin.

USART Interrupt Enable Register Name: US_IER Access Type: Write only  RXRDY: Enable RXRDY Interrupt 0 = No effect. 1 = Enables RXRDY Interrupt.  TXRDY: Enable TXRDY Interrupt 0 = No effect. 1 = Enables TXRDY Interrupt.  RXBRK: Enable Receiver Break Interrupt 0 = No effect. 1 = Enables Receiver Break Interrupt.  ENDRX: Enable End of Receive Transfer Interrupt 0 = No effect. 1 = Enables End of Receive Transfer Interrupt.  ENDTX: Enable End of Transmit Interrupt 0 = No effect. 1 = Enables End of Transmit Interrupt.  OVRE: Enable Overrun Error Interrupt 0 = No effect. 1 = Enables Overrun Error Interrupt.  FRAME: Enable Framing Error Interrupt 0 = No effect. 1 = Enables Framing Error Interrupt.  PARE: Enable Parity Error Interrupt 0 = No effect. 1 = Enables Parity Error Interrupt.  TIMEOUT: Enable Time-out Interrupt 0 = No effect. 1 = Enables Reception Time-out Interrupt.  TXEMPTY: Enable TXEMPTY Interrupt 0 = No effect. 1 = Enables TXEMPTY Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 --- --- --- --- --- --- TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

USART Interrupt Disable Register Name: US_IDR Access Type: Write only  RXRDY: Disable RXRDY Interrupt 0 = No effect. 1 = Disables RXRDY Interrupt.  TXRDY: Disable TXRDY Interrupt 0 = No effect. 1 = Disables TXRDY Interrupt.  RXBRK: Disable Receiver Break Interrupt 0 = No effect. 1 = Disables Receiver Break Interrupt.  ENDRX: Disable End of Receive Transfer Interrupt 0 = No effect. 1 = Disables End of Receive Transfer Interrupt.  ENDTX: Disable End of Transmit Interrupt 0 = No effect. 1 = Disables End of Transmit Interrupt.  OVRE: Disable Overrun Error Interrupt 0 = No effect. 1 = Disables Overrun Error Interrupt.  FRAME: Disable Framing Error Interrupt 0 = No effect. 1 = Disables Framing Error Interrupt.  PARE: Disable Parity Error Interrupt 0 = No effect. 1 = Disables Parity Error Interrupt.  TIMEOUT: Disable Time-out Interrupt 0 = No effect. 1 = Disables Receiver Time-out Interrupt.  TXEMPTY: Disable TXEMPTY Interrupt 0 = No effect. 1 = Disables TXEMPTY Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 --- --- --- --- --- --- TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

USART Interrupt Mask Register Name: US_IMR Access Type: Read only  RXRDY: Mask RXRDY Interrupt 0 = RXRDY Interrupt is Disabled 1 = RXRDY Interrupt is Enabled  TXRDY: Mask TXRDY Interrupt 0 = TXRDY Interrupt is Disabled 1 = TXRDY Interrupt is Enabled  RXBRK: Mask Receiver Break Interrupt 0 = Receiver Break Interrupt is Disabled 1 = Receiver Break Interrupt is Enabled  ENDRX: Mask End of Receive Transfer Interrupt 0 = End of Receive Transfer Interrupt is Disabled 1 = End of Receive Transfer Interrupt is Enabled  ENDTX: Mask End of Transmit Interrupt 0 = End of Transmit Interrupt is Disabled 1 = End of Transmit Interrupt is Enabled  OVRE: Mask Overrun Error Interrupt 0 = Overrun Error Interrupt is Disabled 1 = Overrun Error Interrupt is Enabled  FRAME: Mask Framing Error Interrupt 0 = Framing Error Interrupt is Disabled 1 = Framing Error Interrupt is Enabled  PARE: Mask Parity Error Interrupt 0 = Parity Error Interrupt is Disabled 1 = Parity Error Interrupt is Enabled  TIMEOUT: Mask Time-out Interrupt 0 = Receive Time-out Interrupt is Disabled 1 = Receive Time-out Interrupt is Enabled  TXEMPTY: Mask TXEMPTY Interrupt 0 = TXEMPTY Interrupt is Disabled. 1 = TXEMPTY Interrupt is Enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 --- --- --- --- --- --- TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

USART Channel Status Register Name: US_CSR Access Type: Read only  RXRDY: Receiver Ready 0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. 1 = At least one complete character has been received and the US_RHR has not yet been read.  TXRDY: Transmitter Ready 0 = US_THR contains a character waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested. 1 = US_THR is empty and there is no Break request pending TSR availability. Equal to zero when the USART is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one.  RXBRK: Break Received/End of Break 0 = No Break Received nor End of Break has been detected since the last “Reset Status Bits” command in the Control Register. 1 = Break Received or End of Break has been detected since the last “Reset Status Bits” command in the Control Reg- ister.  ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.  ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.  OVRE: Overrun Error 0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last “Reset Status Bits” command. 1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last “Reset Status Bits” command.  FRAME: Framing Error 0 = No stop bit has been detected low since the last “Reset Status Bits” command. 1 = At least one stop bit has been detected low since the last “Reset Status Bits” command.  PARE: Parity Error 1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last “Reset Status Bits” command. 0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last “Reset Status Bits” com- mand.  TIMEOUT: Receiver Time-out 0 = There has not been a time-out since the last “Start Time-out” command or the Time-out Register is 0. 1 = There has been a time-out since the last “Start Time-out” command.  TXEMPTY: Transmitter Empty 0 = There are characters in either US_THR or the Transmit Shift Register or a Break is being transmitted. 1 = There are no characters in US_THR and the Transmit Shift Register and Break is not active. Equal to zero when the USART is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 --- --- --- --- --- --- TXEMPTY TIMEOUT 76543210 PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY

USART Receiver Holding Register Name: US_RHR Access Type: Read only  RXCHR: Received Character Last character received if RXRDY is set. When number of data bits is less than 8 bits, the bits are right-aligned. All non-significant bits read zero. USART Transmitter Holding Register Name: US_THR Access Type: Write only  TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RXCHR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TXCHR

USART Baud Rate Generator Register Name: US_BRGR Access Type: Read/Write  CD: Clock Divisor This register has no effect if Synchronous Mode is selected with an external clock. Note: In Synchronous Mode, the value programmed must be even to ensure a 50:50 mark:space ratio. Note: Clock divisor bypass (CD = 1) must not be used when internal clock MCKI is selected (USCLKS = 0). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CD 76543210 CD CD

0 Disables Clock

1 Clock Divisor bypass

2 to 65535 Baud Rate (Asynchronous Mode) = Selected clock / (16 x CD) Baud Rate (Synchronous Mode) = Selected clock / CD

USART Receiver Time-out Register Name: US_RTOR Access Type: Read/Write  TO: Time-out Value When a value is written to this register, a Start Time-out Command is automatically performed. Time-out duration = TO x 4 x Bit period USART Transmitter Time-guard Register Name: US_TTGR Access Type: Read/Write  TG: Time-guard Value Time-guard duration = TG x Bit period 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TO TO 0 Disables the RX Time-out function. 1-255 The Time-out counter is loaded with TO when the Start Time-out Command is given or when each new data character is received (after reception has started). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 TG TG 0 Disables the TX Time-guard function. 1-255 TXD is inactive high after the transmission of each character for the time-guard duration.

USART Receive Pointer Register Name: US_RPR Access Type: Read/Write  RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer. USART Receive Counter Register Name: US_RCR Access Type: Read/Write  RXCTR: Receive Counter RXCTR must be loaded with the size of the receive buffer. 0: Stop Peripheral Data Transfer dedicated to the receiver. 1-65535: Start Peripheral Data transfer if RXRDY is active. 31 30 29 28 27 26 25 24 RXPTR 23 22 21 20 19 18 17 16 RXPTR 15 14 13 12 11 10 9 8 RXPTR 76543210 RXPTR 31 30 29 28 27 26 25 24 23 22 21 4920 19 18 17 16 15 14 13 12 11 10 9 8 RXCTR 76543210 RXCTR

USART Transmit Pointer Register Name: US_TPR Access Type: Read/Write  TXPTR: Transmit Pointer TXPTR must be loaded with the address of the transmit buffer. USART Transmit Counter Register Name: US_TCR Access Type: Read/Write  TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer. 0: Stop Peripheral Data Transfer dedicated to the transmitter. 1-65535: Start Peripheral Data transfer if TXRDY is active. 31 30 29 28 27 26 25 24 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 76543210 TXPTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXCTR 76543210 TXCTR

delay timing and pulse width modulation. (Advanced Interrupt Controller). allowing them to be chained. Figure 41. TC Block Diagram

ured to be controlled by the peripheral before being used. ming are listed in Table 11. by reading TC_CV. The counter can be reset by a trigger. next valid edge of the selected clock. opposite edges of the clock. Register defines this signal (none, XC0, XC1, XC2). least 2.5 times lower than the system clock (MCKI). Figure 42. Clock Selection

ways: it can be enabled/disabled and started/stopped. only if the clock is enabled. Figure 43. Clock Control is an output if it is not selected to be the external trigger. A trigger resets the counter and starts the counter clock. fourth external trigger is available to each mode. available by setting SWTRG in TC_CCR. ger by setting ENETRG in TC_CMR.

This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC Channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are inputs. Figure 44 shows the configuration of the TC Channel when programmed in Capture Mode. Capture Registers A and B (RA and RB) Registers A and B are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The parameter LDRA in TC_CMR defines the TIOA edge for the loading of register A, and the parameter LDRB defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trig- ger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. Bit ABETRG in TC_CMR selects input signal TIOA or TIOB as an external trigger. Parameter ETRGEDG defines the edge (rising, falling or both) detected to generate an exter- nal trigger. If ETRGEDG = 0 (none), the external trigger is disabled. Status Register The following bits in the status register are significant in Capture Operating Mode.  CPCS: RC Compare Status There has been an RC Compare match at least once since the last read of the status  COVFS: Counter Overflow Status The counter has attempted to count past $FFFF since the last read of the status  LOVRS: Load Overrun Status RA or RB has been loaded at least twice without any read of the corresponding register, since the last read of the status  LDRAS: Load RA Status RA has been loaded at least once without any read, since the last read of the status  LDRBS: Load RB Status RB has been loaded at least once without any read, since the last read of the status  ETRGS: External Trigger Status An external trigger on TIOA or TIOB has been detected since the last read of the status

Figure 44. Capture Mode

This mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). Waveform Operating Mode allows the TC Channel to gen- erate 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or to generate different types of one-shot or repetitive pulses. In this mode, TIOA is configured as output and TIOB is defined as output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 45 shows the configuration of the TC Channel when programmed in Waveform Operating Mode. Compare Register A, B and C (RA, RB, and RC) In Waveform Operating Mode, RA, RB and RC are all used as compare registers. RA Compare is used to control the TIOA output. RB Com- pare is used to control the TIOB (if configured as output). RC Compare can be programmed to control TIOA and/or TIOB outputs. RC Compare can also stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). As in Capture Mode, RC Compare can also generate a trig- ger if CPCTRG = 1. A trigger resets the counter so RC can control the period of PWM waveforms. External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The parameter EEVT in TC_CMR selects the external trig- ger. The parameter EEVTEDG defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as output and the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trig- ger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal, the software trigger and the RC compare trigger are also available as triggers. Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trig- ger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the out- put as defined in the corresponding parameter in TC_CMR. The tables below show which parameter in TC_CMR is used to define the effect of each event. If two or more events occur at the same time, the priority level is defined as follows: 1. Software trigger 2. External event 3. RC compare 4. RA or RB compare Status The following bits in the status register are significant in Waveform Mode:  CPAS: RA Compare Status there has been a RA Compare match at least once since the last read of the status  CPBS: RB Compare Status there has been a RB Compare match at least once since the last read of the status  CPCS: RC Compare Status there has been a RC Compare match at least once since the last read of the status  COVFS: Counter Overflow Counter has attempted to count past $FFFF since the last read of the status  ETRGS: External Trigger External trigger has been detected since the last read of the status Parameter TIOA Event ASWTRG Software trigger AEEVT External event ACPC RC compare ACPA RA compare Parameter TIOB Event BSWTRG Software trigger BEEVT External event BCPC RC compare BCPB RB compare

Figure 45. Waveform Mode

corresponding channel as mentioned in Table 10. Table 10. TC Global Memory Map Table 11. TC Channel Memory Map

Register Name: TC_BCR Access Type: Write only  SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

Register Name: TC_BMR Access Type: Read/Write  TC0XC0S: External Clock Signal 0 Selection  TC1XC1S: External Clock Signal 1 Selection  TC2XC2S: External Clock Signal 2 Selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 --- --- TC2XC2S TC1XC1S TC0XC0S TC0XC0S Signal Connected to XC0

00 T C L K 0

10 T I O A 1

11 T I O A 2

TC1XC1S Signal Connected to XC1

00 T C L K 1

10 T I O A 0

TC2XC2S Signal Connected to XC2

00 T C L K 2

11 T I O A 1

TC Channel Control Register Register Name: TC_CCR Access Type: Write only  CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1.  CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock.  SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and clock is started. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 --- --- --- --- --- SWTRG CLKDIS CLKEN

TC Channel Mode Register: Capture Mode Register Name: TC_CMR Access Type: Read/Write  TCCLKS: Clock Selection  CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock.  BURST: Burst Signal Selection  LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs.  LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 --- --- --- --- LDRB LDRA 15 14 13 12 11 10 9 8 WAVE=0 CPCTRG --- --- --- ABETRG ETRGEDG 76543210 LDBDIS LDBSTOP BURST CLKI TCCLKS TCCLKS Clock Selected

000 M C K I / 2

001 M C K I / 8

010 M C K I / 3 2

011 M C K I / 1 2 8

100 M C K I / 1 0 2 4

101 X C 0

110 X C 1

111 X C 2

00 The clock is not gated by an external

signal.

01 XC0 is ANDed with the selected

clock.

10 XC1 is ANDed with the selected

clock.

11 XC2 is ANDed with the selected

clock.

 ETRGEDG: External Trigger Edge Selection  ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger.  CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock.  WAVE = 0 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled).  LDRA: RA Loading Selection  LDRB: RB Loading Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge LDRA Edge 0 0 none 0 1 rising edge of TIOA 1 0 falling edge of TIOA 1 1 each edge of TIOA LDRB Edge 0 0 none 0 1 rising edge of TIOA 1 0 falling edge of TIOA 1 1 each edge of TIOA

TC Channel Mode Register: Waveform Mode Register Name: TC_CMR Access Type: Read/Write  TCCLKS: Clock Selection  CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock.  BURST: Burst Signal Selection  CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC.  CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. 31 30 29 28 27 26 25 24 BSWTRG BEEVT BCPC BCPB 23 22 21 20 19 18 17 16 ASWTRG AEEVT ACPC ACPA 15 14 13 12 11 10 9 8 WAVE=1 CPCTRG --- ENETRG EEVT EEVTEDG 76543210 CPCDIS CPCSTOP BURST CLKI TCCLKS TCCLKS Clock Selected signal. clock. clock. clock.

 EEVTEDG: External Event Edge Selection  EEVT: External Event Selection Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.  ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock.  CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock.  WAVE = 1 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled.  ACPA: RA Compare Effect on TIOA  ACPC: RC Compare Effect on TIOA  AEEVT: External Event Effect on TIOA EEVTEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge EEVT Signal selected as external event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output ACPA Effect 0 0 none 01 s e t 10 c l e a r 1 1 toggle ACPC Effect 0 0 none 01 s e t 10 c l e a r 1 1 toggle AEEVT Effect 0 0 none 01 s e t 10 c l e a r 1 1 toggle

 ASWTRG: Software Trigger Effect on TIOA  BCPB: RB Compare Effect on TIOB  BCPC: RC Compare Effect on TIOB  BEEVT: External Event Effect on TIOB  BSWTRG: Software Trigger Effect on TIOB ASWTRG Effect 0 0 none 01 s e t 1 0 clear 11 t o g g l e BCPB Effect 0 0 none 01 s e t 10 c l e a r 1 1 toggle BCPC Effect 0 0 none 01 s e t 10 c l e a r 1 1 toggle BEEVT Effect 0 0 none 01 s e t 10 c l e a r 1 1 toggle BSWTRG Effect 0 0 none 01 s e t 10 c l e a r 1 1 toggle

Register Name: TC_CVR Access Type: Read only  CV: Counter Value CV contains the counter value in real time. TC Register A Register Name: TC_RA Access Type: Read only if WAVE = 0, Read/Write if WAVE = 1  RA: Register A RA contains the Register A value in real time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CV 76543210 CV 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RA 76543210 RA

Register Name: TC_RB Access Type: Read only if WAVE = 0, Read/Write if WAVE = 1  RB: Register B RB contains the Register B value in real time. TC Register C Register Name: TC_RC Access Type: Read/Write  RC: Register C RC contains the Register C value in real time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RB 76543210 RB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RC 76543210 RC

Register Name: TC_SR Access Type: Read/Write  COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register.  LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0.  CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.  CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.  CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register.  LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.  LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.  ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register.  CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled.  MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.  MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 --- --- --- --- --- MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC Interrupt Enable Register Register Name: TC_IER Access Type: Write only  COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt.  LOVRS: Load Overrun 0 = No effect. 1: Enables the Load Overrun Interrupt.  CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt.  CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt.  CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt.  LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt.  LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt.  ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC Interrupt Disable Register Register Name: TC_IDR Access Type: Write only  COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt.  LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0).  CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1).  CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1).  CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt.  LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0).  LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0).  ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

TC Interrupt Mask Register Register Name: TC_IMR Access Type: Read only  COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled.  LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled.  CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled.  CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled.  CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled.  LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled.  LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled.  ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS

signal for a duration of 8 MCKI cycles. of 1ms to 2s with a 33 MHz system clock. control bits are written (the same write access). Figure 46. Watchdog Timer Block Diagram Table 12. WD Memory Map

Name: WD_OMR Access: Read/Write Reset Value: 0  WDEN: Watch Dog Enable 0 = Watch Dog is disabled and does not generate any signals. 1 = Watch Dog is enabled and generates enabled signals.  RSTEN: Reset Enable 0 = Generation of an internal reset by the Watch Dog is disabled. 1 = When overflow occurs, the Watch Dog generates an internal reset.  IRQEN: Interrupt Enable 0 = Generation of an interrupt by the Watch Dog is disabled. 1 = When overflow occurs, the Watch Dog generates an interrupt.  EXTEN: External Signal Enable 0 = Generation of a pulse on the pin NWDOVF by the Watch Dog is disabled. 1 = When an overflow occurs, a pulse on the pin NWDOVF is generated.  OKEY: Overflow Access Key Used only when writing WD_OMR. OKEY is read as 0. 0x234 = Write access in WD_OMR is allowed. Other value = Write access in WD_OMR is prohibited. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 OKEY 76543210 OKEY EXTEN IRQEN RSTEN WDEN

Name: WD_CMR Access: Read/Write Reset Value: 0  WDCLKS: Clock Selection  HPCV: High Preload Counter Value Counter is preloaded when watchdog counter is restarted with bits 0 to 11 set (FFF) and bits 12 to 15 equaling HPCV.  CKEY: Clock Access Key Used only when writing WD_CMR. CKEY is read as 0. 0x06E: Write access in WD_CMR is allowed. Other value: Write access in WD_CMR is prohibited. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CKEY 76543210 CKEY --- HPCV WDCLKS WDCLKS Clock Selected 0 0 MCKI/8 0 1 MCKI/32 1 0 MCKI/128 1 1 MCKI/1024

Name: WD_CR Access: Write only  RSTKEY: Restart Key 0xC071 = Watch Dog counter is restarted. Other value = No effect. WD Status Register Name: WD_SR Access: Read only  WDOVF: Watchdog Overflow 0 = No watchdog overflow. 1 = A watchdog overflow has occurred since the last restart of the watchdog counter or since internal or external reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RSTKEY 76543210 RSTKEY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

To enable the Watchdog Timer the sequence is as follows: 1. Disable the Watchdog by clearing the bit WDEN: Write 0x2340 to WD_OMR This step is unnecessary if the WD is already disabled (reset state). 2. Initialize the WD Clock Mode Register: Write 0x373C to WD_CMR (HPCV = 15 and WDCLKS = MCK/8) 3. Restart the timer: Write 0xC071 to WD_CR 4. Enable the watchdog: Write 0x2345 to WD_OMR (interrupt enabled)

The CPU clock is re-enabled by any enabled interrupt or by a hardware Reset. Table 13. Power Saving Memory Map

SF: Special Function The AT91M40400 provides registers which implement the following special functions.  Chip identification  RESET status  Protect Mode (see Protect Mode on page 37) SF User Interface Chip ID Base Address = 0xFFF00000 Chip ID Register Register Name: SF_CIDR Access Type: Read only  VERSION: Version of the chip This value is incremented by one with each new version of the chip (from zero to a maximum value of 31).  NVPSIZ: Non Volatile Program Memory Size Table 14. SF Memory Map 0x18 Protect Mode Register SF_PMR Read/Write 0x0 31 30 29 28 27 26 25 24 EXT NVPTYP ARCH 23 22 21 20 19 18 17 16 ARCH VDSIZ 15 14 13 12 11 10 9 8 NVDSIZ NVPSIZ 76543210 0 1 0 VERSION NVPSIZ Size

0000 N o n e

 NVDSIZ: Non Volatile Data Memory Size  VDSIZ: Volatile Data Memory Size  ARCH: Chip Architecture Code of Architecture: Two BCD digits.  NVPTYP: Non Volatile Program Memory Type  EXT: Extension Flag 0 = Chip ID has a single register definition without extensions 1 = An extended Chip ID exists (to be defined in the future). Chip ID Extension Register Register Name: SF_EXID Access Type: Read only This register is reserved for future use. It will be defined when needed. NVDSIZ Size

000 R e s e r v e d

001 ‘M ’ Series (Mask ROM or ROM less) 010 ‘C ’ Series (Programmable Flash through Parallel Port) 011 ‘S’ Series (Programmable Flash through Serial Port) 1 x x Reserved

Register Name: SF_RSR Access Type: Read only  RESET: Reset Status Information This field indicates whether the reset was demanded by the external system (via NRST) or by the Watchdog internal reset request. SF Protect Mode Register Register Name: SF_PMR Access Type: Read/Write Reset Value: 0  PMRKEY: Protect Mode Register Key Used only when writing SF_PMR. PMRKEY is reads 0. 0x27A8: Write access in SF_PMR is allowed. Other value: Write access in SF_PMR is prohibited.  AIC: AIC Protect Mode Enable 0 = The Advanced Interrupt Controller runs in Normal Mode. 1 = The Advanced Interrupt Controller runs in Protect Mode. See Protect Mode on page 37. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 RESET Reset Cause of Reset 0x6C External Pin 0x53 Internal Watchdog 31 30 29 28 27 26 25 24 PMRKEY 23 22 21 20 19 18 17 16 PMRKEY 15 14 13 12 11 10 9 8 76543210

Table 15. Revision History B June 1998 Major changes to Revision A. EBI: Added more detailed description of External Wait (page 16). Mode (page 37) and corresponding registers (pages 47 and 114 respectively).

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