AT91C140

AT91C140 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 ARM7TDMI ® ARM ® Thumb ® Processor Core – In-Circuit Emulator, 36 MHz operation  Ethernet Bridge – Dual Ethernet 10/100 Mbps MAC Interface – 16-Kbyte Frame Buffer  1 K-Byte Boot ROM, Embedding a Boot Program – Enable Application Download from DataFlash®  External Bus Interface – On-chip 32-bit SDRAM Controller – 4-Chip Select Static Memory Controller  Multi-level Priority, Individually Maskable, Vectored Interrupt Controller  Three 16-bit Timer/Counters  Two UARTs with Modem Control Lines  Serial Peripheral Interface (SPI)  Two PIO Controllers, Managing up to 48 General-purpose I/O Pins  Available in a 256-ball BGA Package  Power Supplies – VDDIO 3.3V nominal – VDDCORE and VDDOSC 1.8V nominal  -40°C to + 85°C Operating Temperature Range

Description

The AT91C140 is a member of the Atmel AT91 16- and 32-bit microcontroller family based on the ARM7TDMI processor core. This processor has a high performance 32-bit RISC architecture with a high density 16-bit instruction set and very low power consumption. In addition, the AT91C140 integrates a double Ethernet 10/100 base-T MAC capable of operating as an Ethernet bridge, thus making it ideally suited for networking appli- cations. It supports a wide range of memory devices such as SDRAM, SRAM and Flash and embeds an extensive array of peripherals. The device is manufactured using Atmel’s high-density CMOS technology. By combin- ing the ARM7TDMI processor core with an expansive assortment of peripheral functions and low-power oscillators and PLL on a monolithic chip, the Atmel AT91C140 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many networking applications. AT91® ARM ® Thumb Microcontrollers AT91C140

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Figure 1. AT91C140 Block Diagram

Table 1. Pinout for 256-ball BGA Package

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Note: 1. NC Balls should be left unconnected. Table 1. Pinout for 256-ball BGA Package (Continued)

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6069A–ATARM–05/04 Peripheral Multiplexing on PIO Lines The AT91C140 features two PIO Controllers, PIOA and PIOB, multiplexing I/O lines of the peripheral set. The PIO Controller A manages 32 I/O lines, PA0 to PA31. The PIO Controller B manages only 16 I/O lines, PB0 to PB15. Each I/O line of a PIO Controller can be multiplexed with a peripheral I/O. Multiplexing of the PIO Controller A is given in Table 2 on page 7. Multiplexing of the PIO Controller B is given in Table 3 on page 8.

Table 2. Multiplexing on PIO Controller A

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Table 3. Multiplexing on PIO Controller B

Table 4. Signal Description

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Table 4. Signal Description (Continued)

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6069A–ATARM–05/04 ARM7TDMI Core The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor archi- tecture is Von Neumann load/store architecture, characterized by a single data and address bus for instructions and data. The CPU has two instruction sets: the ARM and the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and pro- vides maximum performance. Thumb instructions are 16-bit wide and give maximum code density. Instructions operate on 8-bit, 16-bit and 32-bit data types. The CPU has seven operating modes. Each operating mode has dedicated banked reg- isters for fast exception handling. The processor has a total of 37 32-bit registers, including six status registers. Power Supplies The AT91C140 has three types of power supply pins:  VDDCORE pins power the core, including the ARM7TDMI processor, the memories and the peripherals; voltage is between 1.65V and 1.95V, 1.8V nominal.  VDDIO pins power the I/O lines, including those of the External Bus Interface and those of the peripherals; voltage is between 3V and 3.6V, 3.3V nominal.  VDDOSC pins power the PLL and oscillator cells; voltage is between 1.65V and 1.95V, 1.8V nominal. Ground pins are common to all power supplies. System Controller The AT91C140 features a System Controller that takes care of and controls:  The Test Mode T h e R e s e t  The System Clocks  The Chip Identifier The System Controller manages the reset of all the system and integrates a clock gen- erator, made up of an oscillator and a PLL. Test The AT91C140 features a test pin (TST). This pin must be tied low for normal opera- tions. Using the AT91C140 with the TST pin at a high level might lead to unpredictable results. Reset Controller NRST Pin The AT91C140 is reset by asserting the NRST pin low. It should be asserted for a time adequate to ensure the startup of the oscillator on a power on, and at least 1 ACLK cycle for a warm reset. As the ACLK switches on the 31,25kHz (assuming the crystal is at 16 MHz) as soon as the reset is asserted, it must remain low for at least 32 µs. The first instruction fetch happens 10 ACLK cycles after the reset releases. System Reset A reset initializes the user interface registers to their default states as defined in the peripheral sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter and the Current Pro- gram Status Register, the ARM processor registers do not have defined reset states. When NRST is active, the inputs of the AT91C140 must be held at valid logic levels to reduce the power consumption to a minimum.

details of the boot operations are described in “Memory Controller (MC)” on page 17. The Boot Program is described in “Boot Program” on page 24. The ACLK signal is also provided on the ACLKO pin, through PIO Controller A. Figure 3 below shows the architecture of the Clock Generator. Figure 3. Clock Generator field to speed the boot sequence.

16 MHz

240 MHz

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Table 5. System Controller Register Mapping

6069A–ATARM–05/04 System Mode Register Register Name: SYS_MD Access: Read/Write R M : R e m a p 0 =The ROM is mapped only at its normal address. 1 =The ROM is mapped at its address and at address 0x0.  LP: Low Power Mode 0 =The PLL is enabled and ACLK is the output of the PLL divided by 6 or 7. 1 =The PLL is disabled and ACLK is defined by LPCS.  SA: Slow ARM 0 =The ARM divider is 6. 1 =The ARM divider is 7.  LPCS: Low Power Clock Select 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 –0–0–– L P C S 76543210 S A L P ––0–0 R M LPCS Divisor ACLK 0 0 2 8 MHz 0 1 16 1 MHz 1 0 64 250 kHz 1 1 512 31,25 kHz

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6069A–ATARM–05/04 System ID Register Register Name: SYS_ID Access: Read-only System Clock Status Register Register Name: SYS_CLKF Access: Read-only  ACLKST: ARM Clock Status 0 = ARM Clock currently using the 240 MHz source (PLL). 1 = ARM Clock currently using the 16 MHz source (oscillator). 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000001 15 14 13 12 11 10 9 8 00000010 76543210 00100001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

and the MAC ASB. Both handle a single memory space. the Frame Buffer, but also connects with the ARM ASB. mum speed while the Ethernet traffic goes through the Frame Buffer. The AT91C140 architecture is shown in Figure 4. Figure 4. AT91C140 Memory Controller Architecture

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memory and the embedded peripherals. static memory controller and SDRAM memory controller. regions results in undefined behavior. Figure 5. AT91C140 Memory Map

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described in “Boot Program” on page 24. Figure 7 below shows the mapping of the ROM depending on the Boot Mode. Figure 7. ROM Mapping Depending on the Boot Mode PDC are compliant with this mode of byte arrangement.

6069A–ATARM–05/04 Peripherals The Peripheral Bridge allows access to the embedded peripheral user interfaces. It is optimized for low power consumption, as it is built without usage of any clock. However, any access on the peripheral is performed in two cycles. The AT91C140 peripherals are designed to be programmed with a minimum number of instructions. Each peripheral has 16K bytes of address space allocated in the upper part of the address space. Peripheral Registers All of the peripheral registers are 32-bits wide and support only aligned accesses. When a misaligned access is performed within the peripheral address space, the access is automatically performed at the lower aligned address. All undefined or unused register bits (marked “-”) read 0. It is recommended to write them at 0 for software upward compatibility.

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Peripheral Memory Map Figure 8 below gives the mapping of the peripherals integrated in the AT91C140. Figure 8. Peripheral Memory Map

6069A–ATARM–05/04 Peripheral Data Controller (PDC) PDC Overview The AT91C140 features a six-channel Peripheral Data Controller (PDC) dedicated to the two on-chip UARTs and the SPI. One PDC channel is connected to the receiving channel and one to the transmitting channel of each UART and of the SPI. Each PDC channel operates as DMA (Direct Memory Access). The User Interface of a PDC channel is integrated in the memory space of each periph- eral. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed number of bytes is transferred, an end-of-transfer signal is sent to the peripheral and is visible in the peripheral status register. This status bit might trigger an interrupt. PDC Channel Priority The transfer requests from the peripherals are treated in the order they happen. When several transfer requests happen in the same cycle, the following priority order is applied:  the UART A receiver  the UART A transmitter  the UART B receiver  the UART B transmitter  the SPI receiver  the SPI transmitter

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processor is released from reset it basically attempts a fetch from address 0x00000000. modify how the system boots. When PA0 is latched at 0, the AT91C140 is said to be configured in internal boot mode. tions out of the internal boot ROM. ing RM allows to select the mapping of the boot ROM under software control. external serial DataFlash connected on the on-chip SPI interface as described above. be connected to the AT91C140 as shown below in Figure 9. Figure 9. DataFlash Connection  The processor enters the supervisor mode and all the interrupts are masked.  A branch is executed into the ROM alias based from 0xf9000000.  The ROM alias based at 0x00000000 is removed by writing the RM bit at 1. chip PLL (i.e. the frequency of the crystal divided by 2).  The on-chip SPI interface is setup to prepare for communications with DataFlash. a formatted header describing the contents of the DataFlash. contains valid executable code.

this address and contain the expected code. illustrated below in Table 6. branches to 0x0000 0000 where the real application code is expected. depending on the specific DataFlash device. address should point into some internal RAM. of the header. It must be even. this is not required, the ENTRY field equals the DDST field in most cases. Table 6. Header Structure

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6069A–ATARM–05/04 The internal boot code also uses some internal RAM locations to store temporary data. These reside in the first 64 bytes of RAM, i.e. from 0xFD00 FFC0 to 0xFD00 FFFF. The DDST, DSIZE fields of the DataFlash header must not define a memory area overlap- ping the locations used by the internal boot routine. The ENTRY field must not point into this area.

between both of these controllers. Table 7. Signal Description and Multiplexing

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6069A–ATARM–05/04 SDRAM Controller (SDRAMC) Description The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by provid- ing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The maximum addressable SDRAM size is 256M bytes. The SDRAM Controller supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank. Block Diagram Figure 10. SDRAM Controller Block Diagram Memory Controller APB SDCK SDCS A[12:11, 9:0] SDRAMC BA[1:0] RAS CAS WE DQM[3:0] User Interface System Controller ACLK D[31:0] SDRAMC Chip Select SDA10

device connection by using a 16-bit data bus width. Figure 11. SDRAM Controller Connections to SDRAM Devices: 32-bit Data Bus Width Table 8. I/O Line Description

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Figure 12. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width Table 9. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns Table 10. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns Table 11. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns

1. A minimum pause of 200 µs is provided to precede any signal toggle.
2. An All Banks Precharge command is issued to the SDRAM devices.
3. Eight auto-refresh (CBR) cycles are provided.
4. A mode register set (MRS) cycle is issued to program the parameters of the

SDRAM devices, in particular CAS latency and burst length.

1. A Normal Mode command is provided, 3 clocks after t
2. Perform a dummy access in the SDRAM Memory Space to initialize the state
3. Write refresh rate into the count field in the SDRAMC Refresh Timer register.

(Refresh rate = delay between refresh cycles). After these six steps, the SDRAM devices are fully functional. command field in the SDRAMC Mode register. Table 12. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns Table 13. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns

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Figure 13. SDRAM Device Initialization Sequence

generates a precharge command, activates the new row and initiates a write command. these timing parameters, refer to the “SDRAMC Configuration Register” on page 39. This is described in Figure 14 below. Figure 14. Write Burst, 32-bit SDRAM Access

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described in Figure 15 below. Figure 15. Read Burst, 32-bit SDRAM access

command and the active/read (tRCD ) command. This is described in Figure 16 below. Figure 16. Read Burst with Boundary Row Access

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number of clock cycles between refresh cycles. until the refresh cycle has completed. See Figure 17 below. Figure 17. Refresh Cycle Followed by a Read Access

This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed. Table 14. SDRAM Controller Register Mapping 0 0 0 Normal mode. Any access to the SDRAM is decoded normally. 0 0 1 The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. generates a “Load Mode Register” command with the value “offset” written to the SDRAM device Mode Register. cycle. Prior to this, an “All Banks Precharge” command must be issued.

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6069A–ATARM–05/04 SDRAMC Refresh Timer Register Register Name: SDRAMC_TR Access Type: Read/Write Reset Value: 0x00000800  COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate of the SDRAM device and the refresh burst length where 15.6 µs per row is a typical value for a burst of one length. To refresh the SDRAM device even if the reset value is not equal to 0, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – – – COUNT 76543210 COUNT

6069A–ATARM–05/04 SDRAMC Configuration Register Register Name: SDRAMC_CR Access Type: Read/Write Reset Value: 0x0299C140  NC: Number of Column Bits Reset value is 8 column bits.  NR: Number of Row Bits Reset value is 11 row bits.  NB: Number of Banks Reset value is two banks.  TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 2 and 15. If TWR is less than or equal to 2, two clock periods are inserted by default. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TRAS TRCD TRP 15 14 13 12 11 10 9 8 TRP TRC TWR 76543210 TWR 1 0 NB NR NC NC Column Bits 008 019 10 1 0 11 1 1 NR Row Bits 00 1 1 01 1 2 10 1 3

11 R e s e r v e d

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6069A–ATARM–05/04  TRC: Row Cycle Delay Reset value is eight cycles. This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 2 and 15. If TRC is less than or equal to 2, two clock periods are inserted by default.  TRP: Row Precharge Delay Reset value is three cycles. This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles is between 2 and 15. If TRP is less than or equal to 2, two clock periods are inserted by default.  TRCD: Row to Column Delay Reset value is three cycles. This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is between 2 and 15. If TRCD is less than or equal to 2, two clock periods are inserted by default.  TRAS: Active to Precharge Delay Reset value is five cycles. This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 2 and 15. If TRAS is less than or equal to 2, two clock periods are inserted by default. SDRAMC Address Register Register Name: SDRAMC_ADDR Access Type: Read/Write  SDCS_ADDR This field defines the eight most significant bits of the base address of the SDRAMC. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SDCS_ADDR

static RAM, and parallel peripherals. has up to 24 bits of address bus, a 32- or 16-bit data bus and up to four chip select lines. with the SDRAMC and any external bus master. memories whereas address bits A1 to A23 are significant for 16-bit memories. any valid access to the memory device within the page. tion handling routine used in case of an abort. Pin Description Table 15 below lists the pins used by the SMC to control external memories. The DBW bit in SMC_CSR resets accordingly to the level of DBW32. Table 15. SMC Pin Description

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6069A–ATARM–05/04 Byte Write or Byte Select Mode Each chip select can be individually programmed to operate in Byte Write or Byte Select Mode.  The Byte Write Mode supports four (32-bit bus) or two (16-bit bus) byte writes and a single read signal.  The Byte Select Mode selects the appropriate byte(s) using four (32-bit bus) or two (16-bit bus) byte-select lines and separate read and write signals. This option is controlled by the BAT bit in the Chip Select Register (SMC_CSR0 to SMC_CSR3). The Byte Write Mode is used to connect four 8-bit devices on a 32-bit bus or two 8-bit devices on a 16-bit bus. For a 32-bit bus:  The NWE0 signal is used as the write enable signal for byte 0.  The NWE1 signal is used as the write enable signal for byte 1.  The NWE2 signal is used as the write enable signal for byte 2.  The NWE3 signal is used as the write enable signal for byte 3.  The NSOE signal enables memory reads to all memory blocks. For a 16-bit bus:  The NWE0 signal is used as the write enable signal for byte 0.  The NWE1 signal is used as the write enable signal for byte 1.  The NSOE signal enables memory reads to all memory blocks. The Byte Select Mode is used to connect one 32-bit device or two 16-bit devices on a 32-bit data bus or one 16-bit device on a 16-bit data bus. For a 32-bit bus:  The NWE0 signal is used to select byte 0 for read and write operations.  The NWE1 signal is used to select byte 1 for read and write operations.  The NWE2 signal is used to select byte 2 for read and write operations.  The NWE3 signal is used to select byte 3 for read and write operations.  The NWR signal is used as the write enable signal for the memory block.  The NSOE signal enables memory reads to the memory block. For a 16-bit bus:  The NWE0 signal is used to select byte 0 for read and write operations.  The NWE1 signal is used to select byte 1 for read and write operations.  The NWR signal is used as the write enable signal for the memory block.  The NSOE signal enables memory reads to the memory block. Read Protocols The SMC provides two alternative protocols for external memory read access; standard and early read. The difference between the two protocols lies in the timing of the NSOE (read cycle) waveform. The protocol is selected by the DRP field in the Memory Control Register (SMC_MCR) and is valid for all memory devices. Standard read protocol is the default protocol after reset. Standard Read Protocol Standard read protocol implements a read cycle in which NSOE and the write strobes are similar. Both are active during the second half of the clock cycle. The first half of the clock cycle allows time to ensure completion of the previous access, as well as the out- put of address and NCE before the read cycle begins.

6069A–ATARM–05/04 During a standard read protocol external memory access, the chip enable signal sNCE0 to NCE3 are set low and the address lines are valid at the beginning of the access, whereas NSOE goes low only in the second half of the master clock cycle to avoid bus conflict. The write strobes are the same in both protocols. The write strobes always go low in the second half of the master clock cycle. Early Read Protocol Early read protocol provides more time for a read access from the memory by asserting NSOE at the beginning of the clock cycle. In the case of successive read cycles in the same memory, NSOE remains active continuously. Since a read cycle normally limits the speed of operation of the external memory system, early read protocol allows a faster clock frequency to be used. However, an extra wait state is required in some cases to avoid contention on the external bus. In early read protocol, an early read wait state is automatically inserted when an exter- nal write cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is generated in addition to any other programmed wait states (i.e., data float wait). No wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type or between external and internal memory accesses. Write Protocol During a write cycle, the data becomes valid after the falling edge of the write strobe sig- nal and remains valid after the rising edge of the write strobe. The external write strobe waveform on the appropriate write strobe pin is used to control the output data timing to guarantee this operation. Thus, it is necessary to avoid excessive loading of the write strobe pins, which could delay the write signal too long and cause a contention with a subsequent read cycle in standard protocol. In early read protocol, the data can remain valid longer than in stan- dard read protocol due to the additional wait cycle that follows a write access. Wait States The SMC can automatically insert wait states. The different types of wait states are:  Standard wait states  Data float wait states  Chip select change wait states  Early read wait states, as described in “Early Read Protocol” above. Standard Wait States Each chip select can be programmed to insert one or more wait states during an access on the corresponding device. This is done by setting the WSE field in the corresponding SMC_CSR. The number of cycles to insert is programmed in the NWS field in the same register. When no wait state is programmed (WSE = 0), the NWE signal lasts only one-half cycle. If at least one wait state is programmed, the NWE signal lasts an integer number of cycles, accordingly to the number of wait states programmed. Data Float Wait States Some memory devices are slow to release the external bus. For such devices it is nec- essary to add wait states (data float waits) after a read access before starting a write access or a read access to a different external memory. The Data Float Output Time (TDF) for each external memory device is programmed in the TDF field of the SMC_CSR register for the corresponding chip select. The value (0 - 7 clock cycles) indicates the number of data float waits to be inserted and represents the time allowed for the data output to go to high impedance after the memory is disabled. The SMC keeps track of the programmed external data float time even when it makes internal accesses to ensure that the external memory system is not accessed while it is still busy.

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6069A–ATARM–05/04 Internal memory accesses and consecutive accesses to the same external memory do not insert added data float wait states. When data float wait states are being used, the SMC prevents the SDRAM Controller from accessing the external data bus. Chip Select Change Wait States A chip select wait state is automatically inserted when consecutive accesses are made to two different external memories (if no wait states have already been inserted). If any wait states have already been inserted (e.g., data float wait), then none are added. Signal Waveforms Figure 18 on page 45 shows a write to memory 0 followed by a write and a read to mem- ory 1. SMC_CSR0 is programmed for one wait state with BAT = 0 and TDF = 0. SMC_CSR1 is programmed for zero wait states with BAT = 1 and TDF = 0. Early Read Protocol is enabled. The write to memory 0 is a word access and therefore all four NWE strobes are active. As BAT = 0, they are configured as write strobes and have the same timing as NWR. As the access employs a single wait state, the write strobe pulse is one clock cycle long. There is a chip select change wait state between the memory 0 write and the memory 1 write. The new address is output at the end of the memory 0 access, but the strobes are delayed for one clock cycle. The write to memory 1 is a half-word access to an odd half-word address and, therefore, NWE2 and NWE3 are active. As BAT = 1, they are configured as byte select signals and have the same timing as NCE. As the access has no internal wait states, the write strobe pulse is one- half clock cycle long. Data and address are driven until the write strobe rising edge is sensed at the AT91C140 pin to guarantee positive hold times. There is an early read wait state between memory 1 write and memory 1 read to provide time for the AT91C140 to disable the output data before the memory is read. If the read was normal mode, i.e., not early, the NSOE strobe would not fall until the rising edge of ACLK and no wait state would be inserted. If the write and early read were to different memories, then the early read wait state is not required as a chip select wait state will be implemented. The read from memory 1 is a byte access to an address with a byte offset of 2 and therefore only NWE2 is active.

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therefore, only NWE2 is active. Figure 19. Write and Read to Memory 0, Read and Write to Memory 1

The SMC_CSR register resets according to the DBW32 pin. when they are programmed to optimize boot program execution. Table 16. SMC Register Mapping

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6069A–ATARM–05/04 SMC Chip Select Register Register Name: SMC_CSR0..SMC_CSR3 Access: Read/Write  DBW: Data Bus Width  NWS: Number of Wait States  WSE: Wait State Enable  MWS: Multiply Wait States P A G E S : P a g e S i z e 31 30 29 28 27 26 25 24 BA 23 22 21 20 19 18 17 16 B A –––– 15 14 13 12 11 10 9 8 – – CSEN BAT TDF PAGES 76543210 PAGES MWS WSE NWS DBW DBW Data Bus Width 0 0 Reserved 0 1 16-bit external bus 1 0 32-bit external bus 1 1 Reserved NWS WSE Wait States Number MWS = 0 MWS = 1 X X X 0 0 0 0 0 0 1 1 8 0 0 1 1 2 16 0 1 0 1 3 24 0 1 1 1 4 32 1 0 0 1 5 40 1 0 1 1 6 48 1 1 0 1 7 56 1 1 1 1 8 64 PAGES Page Size Base Address 0 0 1M byte BA20-BA31 0 1 4M bytes BA22-BA31 1 0 16M bytes BA24-BA31 1 1 Reserved –

6069A–ATARM–05/04  TDF: Data Float Output Time  BAT: Byte Access Mode 0 = Byte Write Mode 1= Byte Select Mode  CSEN: Chip Select Enable 0 = Chip Select is disabled 1 = Chip Select is enabled  BA: Base Address This field contains the high-order bits of the base address. If the page size is larger than 1M byte, then the unused bits of the base address are ignored by the SMC decoder. SMC Memory Control Register Register Name: SMC_MCR Access Type: Read/Write  DRP: Data Read Protocol 0 =Standard Read Mode 1 =Early Read Mode TDF Cycles after Transfer 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

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6069A–ATARM–05/04 Ethernet MAC (EMAC) The AT91C140 features two identical Ethernet MACs, both of which feature the following:  Compatible with IEEE Standard 802.3  10 and 100 Mbits per Second Data Throughput Capability  Full- and Half-duplex Operation  Media Independent Interface to the Physical Layer  Register Interface to Address, Status and Control Registers  DMA Interface  Interrupt Generation to Signal Receive and Transmit Completion  28-byte Transmit and 28-byte Receive FIFOs  Automatic Pad and CRC Generation on Transmitted Frames  Address Checking Logic to Recognize Four 48-bit Addresses  Supports Promiscuous Mode Where All Valid Frames are Copied to Memory  Supports Physical Layer Management through MDIO Interface The Ethernet MAC is the hardware implementation of the MAC sub-layer OSI reference model between the physical layer (PHY) and the logical link layer (LLC). It controls the data exchange between a host and a PHY layer according to Ethernet IEEE 802.3 data frame format. The Ethernet MAC contains the required logic and transmit and receive FIFOs for DMA management. In addition, it is interfaced through MDIO/MDC pins for PHY layer management. The Ethernet MAC transfers data in media-independent interface (MII). Block Diagram Figure 20. Block Diagram Ethernet MAC Interrupt Control APB Bridge ACLK EMAC IRQ Mx_TXCLK, Mx_RXCLK Mx_TXEN, Mx_TXER Mx_CRS, Mx_COL Mx_RXER, Mx_RXDV Mx_RXD[3:0] Mx_TXD[3:0] DMA APB MAC ASB Mx_MDC Mx_MDIO

Link Control Data) and frame check sequence CRC32 (FCS). Note: 1. Frame Length between 64 bytes and 1518 bytes. ates and appends the preamble, SFD and CRC fields during transmission. The preamble and SFD fields are stripped during reception. with the Start of Frame Delimiter (SFD) pattern that consists of two consecutive 1's. only to a single node. All physical addresses have an MSB of 0. it is a broadcast address, indicating that the packet is intended for all nodes. Source Address (SA) The source address (SA) is the physical address of the node that sent the packet. Table 17. Pin Configuration Table 18. Packet Format

52 AT91C140

6069A–ATARM–05/04 Length/Type If the value of this field is less than or equal to 1500, then the Length/Type field indicates the number of bytes in the subsequent LLC Data field. If the value of this field is greater than or equal to 1536, then the Length/Type field indicates the nature of the MAC client protocol (protocol type). LLC Data The data field consists of anywhere from 46 to 1500 bytes. Messages longer than 1500 bytes need to be broken into multiple packets. Messages shorter than 46 bytes require appending a pad to bring the data field to the minimum length of 46 bytes. If the data field is padded, the number of valid data bytes is indicated in the length field. Frame Check Sequence Field (FCS) The Frame Check Sequence (FCS) is a 32-bit CRC field, calculated and appended to a packet during transmission to allow detection of errors when a packet is received. Dur- ing reception, error free packets result in a specific pattern in the CRC generator. Packets with improper CRC will be rejected. Frame Format Extensions The original Ethernet standards define the minimum frame size as 64 bytes and the maximum as 1518 bytes. These numbers include all bytes from the Destination MAC Address field through the Frame Check Sequence field. The Preamble and Start Frame Delimiter fields are not included when quoting the size of a frame. The IEEE 802.3ac standard extended the maximum allowable frame size to 1522 bytes to allow a VLAN tag to be inserted into the Ethernet frame format. The BIG bit defined in the ETH_CFG register processes packets with a VLAN tag. The VLAN protocol permits insertion of an identifier, or tag, into the Ethernet frame for- mat to identify the VLAN to which the frame belongs. It allows frames from stations to be assigned to logical groups. This provides various benefits, such as easing network administration, allowing formation of work groups, enhancing network security, and pro- viding a means of limiting broadcast domains (refer to IEEE standard 802.1Q for definition of the VLAN protocol). The 802.3ac standard defines only the implementation details of the VLAN protocol that are specific to Ethernet. If present, the 4-byte VLAN tag is inserted into the Ethernet frame between the Source MAC Address field and the Length field. The first 2 bytes of the VLAN tag consist of the “802.1Q Tag Type” and are always set to a value of 0x8100. The 0x8100 value is a reserved Length/Type field assignment that indicates the presence of the VLAN tag, and signals that the traditional Length/Type field can be found at an offset of four bytes fur- ther into the frame. The last two bytes of the VLAN tag contain the following information.  The first three bits are a User Priority Field that may be used to assign a priority level to the Ethernet frame.  The following one bit is a Canonical Format Indicator (CFI) used in Ethernet frames to indicate the presence of a Routing Information Field (RIF).  The last twelve bits are the VLAN Identifier (VID) that uniquely identifies the VLAN to which the Ethernet frame belongs. With the addition of VLAN tagging, the 802.3ac standard permits the maximum length of an Ethernet frame to be extended from 1518 bytes to 1522 bytes. Table 19 on page 53 illustrates the format of an Ethernet frame that has been “tagged” with a VLAN identifier according to the IEEE 802.3ac standard.

fers are 32-bit words and may be single accesses or bursts of two, three or four words. Burst accesses do not cross 16-byte boundaries. transmit data DMA read and receive data DMA write. Reading the transmit control register returns the total number of bytes to be transmitted. safely queued. An interrupt is generated whenever this bit is set. CRC is not appended if the NCRC bit is set in the transmit control register. mitted at least 96 bit times apart to guarantee the inter-frame gap. Table 19. Ethernet Frame with VLAN Tagging

54 AT91C140

6069A–ATARM–05/04 In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de- assert and then starts transmission after the inter-frame gap of 96 bit-times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retries transmission after the backoff time has elapsed. An error is indicated and any further attempts aborted if 16 attempts cause collisions. If transmit DMA underruns, bad CRC is automatically appended using the same mecha- nism as jam insertion. Underrun also causes TXER to be asserted. Receiver Mode When a packet is received, it is checked for valid preamble, CRC, alignment, length and address. If all these criteria are met, the packet is stored successfully in a receive buffer. If at the end of reception the CRC is bad, then the received buffer is recovered. Each received frame including CRC is written to a single receive buffer. Receive buffers are word-aligned and are capable of containing 1518 or 1522 bytes (BIG = 1 in ETH_CFG) of data (the maximum length of an Ethernet frame). The start location for each received frame is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. Each entry in the list consists of two words. The first word is the address of the received buffer; the second is the receive status. Table 20 defines an entry in the received buffer descriptor list. To receive frames, the buffer queue must be initialized by writing an appropriate address to bits [31:2] in the first word of each list entry. Bit zero of word zero must be written with zero. After a frame is received, bit zero becomes set and the second word indicates what caused the frame to be copied to memory. The start location of the received buffer descriptor list should be written to the received buffer queue pointer register before receive is enabled (by setting the receive enable bit in the network control register). As soon as the received block starts writing received frame data to the receive FIFO, the received buffer manager reads the first receive buffer location pointed to by the received buffer queue pointer register. If the filter block is active, the frame should be copied to memory; the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered. If the frame is received without error, the queue entry is updated. The buffer pointer is rewritten to memory with its low-order bit set to indicate successful frame reception and a used buffer. The next word is written with the length of the frame and how the destination address was recognized. The next receive buffer location is then read from the following word or, if the current buffer pointer had its wrap bit set, the beginning of the table. The maximum number of buffer pointers before a wrap bit is seen is 1024. If a wrap bit is not seen by then, a wrap bit is assumed in that entry. The received buffer queue pointer register must be written with zero in its lower- order bit positions to enable the wrap function to work correctly. If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer unavailable bit in the received status register and triggers an interrupt. The frame is discarded and the queue entry is reread on reception of the next frame to see if the buffer is now available. Each discarded frame increments a statistics register that is cleared on being read. When there is network congestion, it is possible for the MAC to be programmed to apply back pressure. This is when half-duplex mode collisions are forced on all received frames by transmit- ting 64 bits of data (a default pattern).

time a destination address is received. The hash register is 64 bits long and takes up two locations in the memory map. There are four 48-bit specific address registers, each taking up two memory locations. addresses stored can be specific, group, local or universal. Table 20. Received Buffer Descriptor List

31 Global all ones broadcast address detected

30 Multicast hash match

29 Unicast hash match

28 External address

27 Unknown source address (reserved for future use)

26 Local address match (Specific address 1 match)

25 Local address match (Specific address 2 match)

24 Local address match (Specific address 3 match)

23 Local address match (Specific address 4 match)

56 AT91C140

6069A–ATARM–05/04 the specific address register. The MSB of the first byte of the destination address corre- sponds to bit 31 of the specific address register. The specific address registers are compared to the destination address of received frames once they have been activated. Addresses are deactivated at reset or when the first byte [47:40] is written and activated or when the last byte [7:0] is written. If a receive frame address matches an active address, the local match signal is set and the store frame pulse signal is sent to the DMA block via the ACLK synchronization block. A frame can also be copied if a unicast or multicast hash match occurs, it has the broad- cast address of all ones, or the copy all frames bit in the network configuration register is set. The broadcast address of 0xFFFFFFFF is recognized if the no broadcast bit in the net- work configuration register is zero. This sets the broadcast match signal and triggers the store frame signal. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. So all multicast frames can be received by setting all bits in the hash register. The CRC algorithm reduces the destination address to a 6-bit index into a 64-bit hash register.If the equivalent bit in the register is set, the frame is matched depending on whether the frame is multicast or unicast and the appropriate match signals are sent to the DMA block. If the copy all frames bit is set in the network configuration register, the store frame pulse is always sent to the DMA block as soon as any destination address is received.

Note: 1. For further details on the statistics registers, see Table 22, “Statistics Register Block,” on page 71. Table 21. Ethernet MAC Register Mapping

58 AT91C140

6069A–ATARM–05/04 EMAC Control Register Register Name: ETH_CTL Access Type: Read/Write  LB: Loopback . When set, loopback signal is at high level.  LBL: Loopback Local When set, connects ETX[3:0] to ERX[3:0], ETXEN to ERXDV, forces full duplex and drives ERXCK and ETXCK_REFCK with ACK divided by 4.  RE: Receive Enable When set, enables the Ethernet MAC to receive data.  TE: Transmit Enable When set, enables the Ethernet transmitter to send data.  MPE: Management Port Enable Set to one to enable the management port. When zero, forces MDIO to high impedance state.  CSR: Clear Statistics Registers This bit is write-only. Writing a one clears the statistics registers.  ISR: Increment Statistics Registers This bit is write-only. Writing a one increments all the statistics registers by one for test purposes.  WES: Write Enable for Statistics Registers Setting this bit to one makes the statistics registers writable for functional test purposes.  BP: Back Pressure If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (default pattern). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 WES ISR CSR MPE TE RE LBL LB

6069A–ATARM–05/04 EMAC Mode Register Name: ETH_CFG Access Type: Read/Write  SPD: Speed Set to 1 to indicate 100 Mbit/sec, 0 for 10 Mbit/sec. Has no other functional effect.  FD: Full Duplex If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting.  BR: Bit Rate  CAF: Copy All Frames When set to 1, all valid frames are received.  NBC: No Broadcast When set to 1, frames addressed to the broadcast address of all ones are not received.  MTI: Multicast Hash Enable When set multicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register.  UNI: Unicast Hash Enable When set, unicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register.  BIG: Receive 1522 Bytes When set, the MAC receives up to 1522 bytes. Normally the MAC receives frames up to 1518 bytes in length. This bit allows to receive extended Ethernet frame with “VLAN tag” (IEEE 802.3ac)  EAE: External Address Match Enable C L K The ARM clock is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that ACK is divided by 32.  RTY: Retry Test When set, the time between frames is always one time slot. For test purposes only. Must be cleared for normal operation. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – – RTY CLK EAE BIG 76543210 UNI MTI NBC CAF – BR FD SPD CLK MDC

00 ACK divided by 8

01 ACK divided by 16

10 ACK divided by 32

11 ACK divided by 64

60 AT91C140

6069A–ATARM–05/04 EMAC Status Register Name: ETH_SR Access Type: Read-only L I N K 0 = LINK is at 0. 1 = LINK is at 1. M D I O 0 = MDIO pin not set. 1 = MDIO pin set. I D L E 0 = PHY logic is idle. 1 = PHY logic is running. EMAC Transmit Address Register Name: ETH_TAR Access Type: Read/Write  ADDRESS: Transmit Address Register Written with the address of the frame to be transmitted, read as the base address of the buffer being accessed by the trans- mit FIFO. Note that if the two least significant bits are not zero, transmit starts at the byte indicated. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––––– I D L E M D I O L I N K 31 30 29 28 27 26 25 24 ADDRESS 23 22 21 20 19 18 17 16 ADDRESS 15 14 13 12 11 10 9 8 ADDRESS 76543210 ADDRESS

6069A–ATARM–05/04 EMAC Transmit Control Register Name: ETH_TCR Access Type: Read/Write  LEN: Transmit Frame Length This register is written to the number of bytes to be transmitted excluding the four CRC bytes unless the no CRC bit is asserted. Writing these bits to any non-zero value initiates a transmission. If the value is greater than 1514 (1518 if no CRC is being generated), an oversize frame is transmitted. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Must always be written in address-then-length order. Reads as the total number of bytes to be transmitted (i.e., this value does not change as the frame is transmitted.) Frame transmission does not start until two 32-bit words have been loaded into the transmit FIFO. The length must be great enough to ensure two words are loaded.  NCRC: No CRC If this bit is set, it is assumed that the CRC is included in the length being written in the low-order bits and the MAC does not append CRC to the transmitted frame. If the buffer is not at least 64 bytes long, a short frame is sent. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Reads as the value of the frame cur- rently being transmitted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 NCRC – – – – LEN 76543210 LEN

62 AT91C140

6069A–ATARM–05/04 EMAC Transmit Status Register Name: ETH_TSR Access Type: Read/Write  OVR: Ethernet Transmit Buffer Overrun Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when bit BNQ was not set. Cleared by writing a one to this bit.  COL: Collision Occurred Set by the assertion of a collision. Cleared by writing a one to this bit.  RLE: Retry Limit Exceeded Cleared by writing a one to this bit.  IDLE: Transmitter Idle Asserted when the transmitter has no frame to transmit. Cleared when a length is written to transmit frame length portion of the Transmit Control register. This bit is read-only.  BNQ: Ethernet Transmit Buffer not Queued Software may write a new buffer address and length to the transmit DMA controller when set. Cleared by having one frame ready to transmit and another in the process of being transmitted. This bit is read-only.  COMP: Transmit Complete Set when a frame has been transmitted. Cleared by writing a one to this bit.  UND: Transmit Underrun Set when transmit DMA was not able to read data from memory in time. If this happens, the transmitter forces bad CRC. Cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – UND COMP BNQ IDLE RLE COL OVR

6069A–ATARM–05/04 EMAC Receive Buffer Queue Pointer Register Name: ETH_RBQP Access Type: Read/Write  ADDRESS: Receive Buffer Queue Pointer Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. The receive buffer is forced to word alignment. EMAC Receive Status Register Name: ETH_RSR Access Type: Read/Write  BNA: Buffer Not Available An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit.  REC: Frame Received One or more frames have been received and placed in memory. Cleared by writing a one to this bit.  OVR: RX Overrun The DMA block was unable to store the receive frame to memory, either because the MAC ASB bus was not granted in time or because an abort occurred. The buffer is recovered if this happens. Cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ADDRESS 23 22 21 20 19 18 17 16 ADDRESS 15 14 13 12 11 10 9 8 ADDRESS 76543210 ADDRESS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

64 AT91C140

6069A–ATARM–05/04 EMAC Interrupt Status Register Name: ETH_ISR Access Type: Read/Write  DONE: Management Done The PHY maintenance register has completed its operation. Cleared on read.  RCOM: Receive Complete A frame has been stored in memory. Cleared on read.  RBNA: Receive Buffer Not Available Cleared on read.  TOVR: Transmit Buffer Overrun Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read.  TUND: Transmit Buffer Underrun Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.  RTRY: Retry Limit Retry limit exceeded. Cleared on read.  TBRE: Transmit Buffer Register Empty Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read.  TCOM: Transmit Complete Set when a frame has been transmitted. Cleared on read.  TIDLE: Transmit Idle Set when all frames have been transmitted. Cleared on read. L I N K Set when LINK pin changes value. R O V R : R X O v e r r u n Set when the RX overrun status bit is set. Cleared on read.  ABT: Abort Set when the DMA generates an Abort. Cleared on read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – – – ABT ROVR LINK TIDLE 76543210 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE

6069A–ATARM–05/04 EMAC Interrupt Enable Register Name: ETH_IER Access Type: Write-only  DONE: Management Done Interrupt Enable  RCOM: Receive Complete Interrupt Enable  RBNA: Receive Buffer Not Available Interrupt Enable  TOVR: Transmit Buffer Overrun Interrupt Enable  TUND: Transmit Buffer Underrun Interrupt Enable  RTRY: Retry Limit Interrupt Enable  TBRE: Transmit Buffer Register Empty Interrupt Enable  TCOM: Transmit Complete Interrupt Enable  TIDLE: Transmit Idle Interrupt Enable  LINK: LINK Interrupt Enable  ROVR: RX Overrun Interrupt Enable  ABT: Abort Interrupt Enable 0 =No effect. 1 =Enables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – – – ABT ROVR LINK TIDLE 76543210 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE

66 AT91C140

6069A–ATARM–05/04 EMAC Interrupt Disable Register Name: ETH_IDR Access Type: Write-only  DONE: Management Done Interrupt Disable  RCOM: Receive Complete Interrupt Disable  RBNA: Receive Buffer Not Available Interrupt Disable  TOVR: Transmit Buffer Overrun Interrupt Disable  TUND: Transmit Buffer Underrun Interrupt Disable  RTRY: Retry Limit Interrupt Disable  TBRE: Transmit Buffer Register Empty Interrupt Disable  TCOM: Transmit Complete Interrupt Disable  TIDLE: Transmit Idle Interrupt Disable  LINK: LINK Interrupt Disable  ROVR: RX Overrun Interrupt Disable  ABT: Abort Interrupt Disable 0 =No effect. 1 =Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – – – ABT ROVR LINK TIDLE 76543210 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE

6069A–ATARM–05/04 EMAC Interrupt Mask Register Name: ETH_IMR Access Type: Read-only  DONE: Management Done Interrupt Mask  RCOM: Receive Complete Interrupt Mask  RBNA: Receive Buffer Not Available Interrupt Mask  TOVR: Transmit Buffer Overrun Interrupt Mask  TUND: Transmit Buffer Underrun Interrupt Mask  RTRY: Retry Limit Interrupt Mask  TBRE: Transmit Buffer Register Empty Interrupt Mask  TCOM: Transmit Complete Interrupt Mask  TIDLE: Transmit Idle Interrupt Mask  LINK: LINK Interrupt Mask  ROVR: RX Overrun Interrupt Mask  ABT: Abort Interrupt Mask 0 =The corresponding interrupt is enabled. 1 =The corresponding interrupt is not enabled. Important Note: The interrupt is disabled when the corresponding bit is set. This is non-standard with other peripherals of the product, as generally a mask bit set enables the interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 – – – – ABT ROVR LINK TIDLE 76543210 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE

68 AT91C140

6069A–ATARM–05/04 EMAC PHY Maintenance Register Name: ETH_MAN Access Type: Read/Write Writing to this register starts the shift register that controls the serial connection to the PHY . On each shift cycle the MDIO pin becomes equal to the MSB of the shift register and LSB of the shift register becomes equal to the value of the MDIO pin. When the shifting is complete an interrupt is generated and the IDLE field is set in the Network Status register. When read, gives current shifted value. D A T A For a write operation this is written with the data to be written to the PHY . After a read operation this contains the data read from the PHY . C O D E Must be written to 10 in accordance with IEEE standard 802.3. Reads as written. R E G A Register address. Specifies the register in the PHY to access. P H Y A PHY address. Normally is 0. R W Read/Write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame. H I G H Must be written with 1 to make a valid PHY management frame. Conforms with IEEE standard 802.3. L O W Must be written with 0 to make a valid PHY management frame. Conforms with IEEE standard 802.3. 31 30 29 28 27 26 25 24 LOW HIGH RW PHYA 23 22 21 20 19 18 17 16 PHYA REGA CODE 15 14 13 12 11 10 9 8 DATA 76543210 DATA

6069A–ATARM–05/04 EMAC Hash Address High Register Register Name: ETH_HSH Access Type: Read/Write  ADDR Hash address bits 63 to 32. EMAC Hash Address Low Register Register Name: ETH_HSL Access Type: Read/Write  ADDR Hash address bits 31 to 0. 31 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 76543210 ADDR 31 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 76543210 ADDR

70 AT91C140

6069A–ATARM–05/04 EMAC Specific Address (1, 2, 3 and 4) High Register Register Name: ETH_SA1H,...ETH_SA4H Access Type: Read/Write  ADDR Unicast addresses (1, 2, 3 and 4), Bits 47:32. EMAC Specific Address (1, 2, 3 and 4) Low Register Register Name: ETH_SA1L,...ETH_SA4L Access Type: Read/Write  ADDR Unicast addresses (1, 2, 3 and 4), Bits 31:0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ADDR 76543210 ADDR 31 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 76543210 ADDR

maximum value. They should be read frequently enough to prevent loss of data. Register Mapping,” on page 57. Table 22. Statistics Register Block Frames Transmitted OK Register ETH_FRA A 24-bit register counting the number of frames successfully transmitted. before being transmitted and experiencing no carrier loss nor underrun. of bytes long, that have bad CRC and that are 64 to 1518 bytes long.

• are between 64 and 1518 bytes long.

sense active on their first attempt at transmission (no underrun or collision). counted twice, i.e., both as a collision and a late collision. after the start of transmission (no excessive collision). length but that do not have either a CRC error, an alignment error or a code error. length and having either a CRC error, an alignment error or a code error. within a slot time of pin ETXEN being deasserted. received but cannot be copied to memory because the receive buffer is available.

72 AT91C140

The AT91C140 integrates the Atmel advanced interrupt controller (AIC). the two external interrupt request lines, IRQ0 to IRQ1. or high- or low-level sensitive. Figure 21. Advanced Interrupt Controller Block Diagram Table 23. Interrupt Sources

0 FIQ Fast Interrupt (LOWP)

2 SWI Software Interrupt

3 UARTA UART A Interrupt

4 TC0 Timer Channel 0 Interrupt

5 TC1 Timer Channel 1 Interrupt

6 TC2 Timer Channel 2 Interrupt

7 PIOA PIO A Interrupt

8 MACA MAC A Interrupt

9 SPI Serial Peripheral Interface

10 IRQ0 External Interrupt

mable priority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest. with the lowest interrupt source number is serviced first. possible outcomes depending on whether the AIC_IVR has been read.

1. If the nIRQ line has been asserted but the AIC_IVR has not been read, then the

AIC_IVR register and the current interrupt level is updated.

1. If the processor has already read the AIC_IVR, then the nIRQ line is reasserted.

the current priority is updated to the higher priority. the preceding lower priority interrupt which had been interrupted. (AIC_EOICR) must be written. This allows pending interrupts to be serviced. register AIC_IMR. A disabled interrupt does not affect the servicing of other interrupts.

11 IRQ1 External Interrupt

12 Reserved

13 MACB MAC B Interrupt

14 UARTB UART B Interrupt

15 PIOB PIO B Interrupt

Table 23. Interrupt Sources (Continued)

74 AT91C140

6069A–ATARM–05/04 Standard Interrupt Sequence It is assumed that:  The advanced interrupt controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. When nIRQ is asserted and if the I bit of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the IRQ link register (R14_IRQ) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_IRQ, decrementing it by 4. 2. The ARM core enters IRQ mode if it is not already. 3. When the instruction at 0x18 is executed, the Program Counter is loaded with the value read in the AIC_IVR. Reading the AIC_IVR has the following effects: Sets the current interrupt to be the pending one with the highest priority. The current level is the priority level of the current interrupt. De-asserts the nIRQ line on the processor (even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ). Automatically clears the interrupt if it has been programmed to be edge-triggered. Pushes the current level on to the stack. Returns the AIC_SVR corresponding to the current interrupt. 4. The previous step establishes a connection to the corresponding ISR. This begins by saving the link register (R14_IRQ) and the SPSR (SPSR_IRQ). Note that the link register must be decremented by 4 when it is saved if it is to be restored directly into the Program Counter at the end of the interrupt. 5. Further interrupts can then be unmasked by clearing the I bit in the CPSR, allow- ing re-assertion of the nIRQ to be taken into account by the core. This can occur if an interrupt with a higher priority than the current one occurs. 6. The interrupt handler then proceeds as required, saving the registers which are used and restoring them at the end. During this phase, an interrupt of priority higher than the current level will restart the sequence from step 1. Note that if the interrupt is programmed to be level-sensitive, the source of the interrupt must be cleared during this phase. 7. The I bit in the CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The service routine should then connect to the common exit routine. 9. The End Of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the cur- rent level to be popped from the stack, restoring the previous current level if one exists. If another interrupt with lower or equal priority than the old current level is pending, the nIRQ line is re-asserted but the interrupt sequence does not imme- diately start because the I bit is set in the core. 10. The SPSR (SPSR_IRQ) is restored. Finally, the saved value of the Link Register is restored directly into the PC. This has the effect of returning from the interrupt to the step previously executed, of loading the CPSR with the stored SPSR and of masking or unmasking the interrupts depending on the state saved in the SPSR (the previous state of the ARM core). Note: The I bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask IRQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the mask instruction is completed (IRQ is masked).

6069A–ATARM–05/04 Fast Interrupt The external FIQ line is the only source which can raise a fast interrupt request to the processor. Therefore it has no priority controller. It can be programmed to be positive- or negative-edge triggered or high- or low-level sensitive in the AIC_SMR0 register. The fast interrupt handler address can be stored in the AIC_SVR0 register. The value written into this register is available by reading the AIC_FVR register when an FIQ inter- rupt is raised. By storing the following instruction at address 0x0000001C, the processor will load the program counter with the interrupt handler address stored in the AIC_FVR register. LDR PC, [PC, #-&F20] Alternatively, the interrupt handler can be stored starting from address 0x0000001C as described in the ARM7TDMI datasheet. Fast Interrupt Sequence It is assumed that:  The advanced interrupt controller has been programmed, AIC_SVR[0] is loaded with the fast interrupt service routine address and the fast interrupt is enabled.  Nested fast interrupts are not needed by the user. When nFIQ is asserted, if the F bit of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the Program Counter is loaded in the FIQ link register (R14_FIQ) and the Program Counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_FIQ, decrementing it by 4. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the Program Counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has the effect of clearing the fast interrupt (source 0 connected to the FIQ line) if it has been programmed to be edge-triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step establishes a connection to the corresponding interrupt ser- vice routine. It is not necessary to save the Link Register (R14_FIQ) and the SPSR (SPSR_FIQ) if nested fast interrupts are not needed. 5. The interrupt handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level- sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the nFIQ line. 6. Finally, the Link Register (R14_FIQ) is restored into the PC after decrementing it by 4 (e.g., with instruction SUB PC, LR, #4). This has the effect of returning from the interrupt to the step previously executed, of loading the CPSR with the SPSR and of masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence, when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). Software Interrupt Any interrupt source of the AIC can be a software interrupt. It must be programmed to be edge-triggered in order to set or clear it by writing to the AIC_ISCR and AIC_ICCR. This is totally independent of the SWI instruction of the ARM7TDMI processor.

76 AT91C140

6069A–ATARM–05/04 Spurious Interrupt A spurious interrupt is a signal of very short duration on one of the interrupt input lines. A spurious interrupt also arises when an interrupt is triggered and masked in the same cycle. Spurious Interrupt Sequence A spurious interrupt is handled by the following sequence of actions. 1. When an interrupt is active, the AIC asserts the nIRQ (or nFIQ) line and the ARM7TDMI enters IRQ (or FIQ) mode. At this moment, if the interrupt source disappears, the nIRQ (or nFIQ) line is de-asserted but the ARM7TDMI continues with the interrupt handler. 2. If the IRQ Vector Register (AIC_IVR) is read when the nIRQ is not asserted, the AIC_IVR is read with the contents of the Spurious Interrupt Vector Register. 3. If the FIQ Vector Register (AIC_FVR) is read when the nFIQ is not asserted, the AIC_FVR is read with the contents of the Spurious Interrupt Vector Register. 4. The Spurious ISR must write an End of Interrupt command as a minimum, how- ever, it is sufficient to write to the End of Interrupt Command Register (AIC_EOICR). Until the AIC_EOICR write is received by the interrupt controller, the nIRQ (or nFIQ) line is not re-asserted. 5. This causes the ARM7TDMI to jump into the Spurious Interrupt Routine. 6. During a spurious ISR, the AIC_ISR reads 0.

Note: 1. The reset value of this register depends on the level of the external IRQ lines. All other sources are cleared at reset. Table 1. AIC Register Mapping

78 AT91C140

6069A–ATARM–05/04 AIC Source Mode Register Register Name: AIC_SMR0...AIC_SMR31 Access Type: Read/Write P R I O R : P r i o r i t y L e v e l Programs the priority level for all sources except source 0 (FIQ). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ in the SMR0.  SRCTYPE: Interrupt Source Type Programs the input to be positive- or negative-edge triggered or positive- or negative-level sensitive. The active level or edge is not programmable for the internal sources. AIC Source Vector Registers Register Name: AIC_SVR0...AIC_SVR31 Access Type: Read/Write V e c t o r In these registers, the user may store the addresses of the corresponding handler for each interrupt source. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – SRCTYPE – – PRIOR SRCTYPE Internal Sources External Sources

00 Level-sensitive Low-level sensitive

01 Edge-triggered Negative-edge triggered

10 Level-sensitive High-level sensitive

11 Edge-triggered Positive-edge triggered

6069A–ATARM–05/04 AIC Interrupt Vector Registers Register Name: AIC_IVR Access Type: Read-only Reset Value: 0 I R Q V The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The SVR Register (1 to 31) is indexed by the current interrupt number when the IVR register is read. When there is no interrupt, the IRQ register reads 0. AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Read-only Reset Value: 0 F I Q The vector register contains the vector programmed by the user in SVR Register 0 which corresponds to FIQ. 31 30 29 28 27 26 25 24 IRQV 23 22 21 20 19 18 17 16 IRQV 15 14 13 12 11 10 9 8 IRQV 76543210 IRQV 31 30 29 28 27 26 25 24 FIQV 23 22 21 20 19 18 17 16 FIQV 15 14 13 12 11 10 9 8 FIQV 76543210 FIQV

80 AT91C140

6069A–ATARM–05/04 AIC Interrupt Status Register Register Name: AIC_ISR Access Type: Read-only I R Q I D The interrupt status register returns the current interrupt source register. AIC Interrupt Pending Register Register Name: AIC_IPR Access Type: Read-only  Interrupt Pending 0 = Corresponding interrupt is not pending. 1 = Corresponding interrupt is pending. AIC Interrupt Mask Register Register Name: AIC_IMR Access Type: Read-only  Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ––– I R Q I D 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 PIOB UARTB MACB 0 IRQ1 IRQ0 SPI MACA 76543210 PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 PIOB UARTB MACB 0 IRQ1 (1) IRQ0 SPI MACA 76543210 PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ

6069A–ATARM–05/04 AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read-only  nFIQ: nFIQ Status 0 = nFIQ line inactive. 1 = nFIQ line active.  NIRQ: nIRQ Status 0 = nIRQ line inactive. 1 = nIRQ line active. AIC Interrupt Enable Command Register Register Name: AIC_IECR Access Type: Write-only  Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 PIOB UARTB MACB 0 IRQ1 IRQ0 SPI MACA 76543210 PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ

82 AT91C140

6069A–ATARM–05/04 AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: Write-only  Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. AIC Interrupt Clear Command Register Register Name: AIC_ICCR Access Type: Write-only  Interrupt Clear 0 = No effect. 1 = Clears the corresponding interrupt. 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 PIOB UARTB MACB 0 IRQ1 IRQ0 SPI MACA 76543210 PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 PIOB UARTB MACB 0 IRQ1 IRQ0 SPI MACA 76543210 PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ

6069A–ATARM–05/04 AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: Write-only  Interrupt Set 0 = No effect. 1 = Sets the corresponding interrupt. A IC End of Interrupt Command Register Register Name: AIC_EOICR Access Type: Write-only The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written as it is only necessary to make a write to this register location to signal the end of interrupt treatment. 31 30 29 28 27 26 25 24 00000000 23 22 21 20 19 18 17 16 00000000 15 14 13 12 11 10 9 8 PIOB UARTB MACB 0 IRQ1 IRQ0 SPI MACA 76543210 PIOA TC2 TC1 TC0 UARTA SWI 0 FIQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210

84 AT91C140

6069A–ATARM–05/04 AIC Spurious Interrupt Vector Register Register Name: AIC_SPU Access Type: Read/Write S I Q V This register contains the 32-bit address of an interrupt routine which is used to treat cases of spurious interrupts. The programmed address is read in the AIC_IVR if it is read when the nIRQ line is not asserted. The programmed address is read in the AIC_FVR if it is read when the nFIQ line is not asserted. 31 30 29 28 27 26 25 24 SIQV 23 22 21 20 19 18 17 16 SIQV 15 14 13 12 11 10 9 8 SIQV 76543210 SIQV

6069A–ATARM–05/04 Parallel I/O Controller (PIO) The AT91C140 integrates two PIO controllers, PIOA and PIOB. PIOA controls 32 I/O lines and PIOB controls 16 FI/O lines. Each I/O line can be programmed as an input or an output and can generate an interrupt on level change. These pins are used for several functions:  External I/O for Internal Peripherals  Keypad Controller Function  General Purpose I/O Output Selection The user can enable each individual I/O signal as an output with the PIO_OER and PIO_ODR registers. The output status of the I/O signals can be read in the PIO_OSR register. The direction defined has an effect only if the pin is configured to be controlled by the PIO controller. I/O Levels Each pin can be configured to be driven high or low. The level is defined in four different ways, according to the following conditions:  If a pin is controlled by the PIO controller and is defined as an output, the level is programmed using the PIO_SODR and PIO_CODR registers. In this case, the programmed value can be read in the PIO_ODSR register.  If a pin is controlled by the PIO controller and is not defined as an output, the level is determined by the external circuit.  If a pin is not controlled by the PIO controller, the state of the pin is defined by the peripheral. In all cases, the level on the pin can be read in the register PIO_PDSR. Interrupts Each parallel I/O can be programmed to generate an interrupt when a level change occurs. This is controlled by the PIO_IER and PIO_IDR registers which enable/disable the I/O interrupt by setting/clearing the corresponding bit in PIO_IMR. When a change in level occurs, the corresponding bit in PIO_ISR is set depending on whether the pin is used as a PIO or a peripheral, and whether it is defined as input or output. If the corre- sponding interrupt in PIO_IMR is enabled, the PIO interrupt is asserted. When PIO_ISR is read, the register is automatically cleared.

86 AT91C140

Figure 22. I/O Line Block Diagram

bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read as zero. Notes: 1. The reset value of this register depends on the level of the external pins at reset.

1. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have

occurred on any pins between the reset and the read. Table 24. PIO Controller Memory Map

88 AT91C140

6069A–ATARM–05/04 PIO Enable Register Register Name: PIO_PER Access Type: Write-only This register is used to enable individual pins to be controlled by the PIO controller instead of the associated peripheral. When the PIO is enabled, the associated peripheral (if any) is held at logic zero. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 0 = No effect. PIO Disable Register Register Name: PIO_PDR Access Type: Write-only This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral func- tion is enabled on the corresponding pin. 1 = Disables PIO control (enables peripheral control) on the corresponding pin. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

6069A–ATARM–05/04 PIO Status Register Register Name: PIO_PSR Access Type: Read-only This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or disabled. 1 = PIO is active on the corresponding line (peripheral is inactive). 0 = PIO is inactive on the corresponding line (peripheral is active). PIO Output Enable Register Register Name: PIO_OER Access Type: Write-only This register is used to enable PIO output drivers. If the pin is driven by a peripheral, there is no effect on the pin but the information is stored. The register is programmed as follows: 1 = Enables the PIO output on the corresponding pin. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

90 AT91C140

6069A–ATARM–05/04 PIO Output Disable Register Register Name: PIO_ODR Access Type: Write-only This register is used to disable PIO output drivers. If the pin is driven by the peripheral, there is no effect on the pin, but the information is stored. The register is programmed as follows: 1 = Disables the PIO output on the corresponding pin. 0 = No effect. PIO Output Status Register Register Name: PIO_OSR Access Type: Read-only This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows: 1 = The corresponding PIO is output on this line. 0 = The corresponding PIO is input on this line. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

6069A–ATARM–05/04 PIO Set Output Data Register Register Name: PIO_SODR Access Type: Write-only This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is set. 0 = No effect. PIO Clear Output Data Register Register Name: PIO_CODR Access Type: Write-only This register is used to clear PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored. 1 = PIO output data on the corresponding pin is cleared. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

92 AT91C140

6069A–ATARM–05/04 PIO Output Data Status Register Register Name: PIO_ODSR Access Type: Read-only This register shows the output data status which is programmed in PIO_SODR or PIO_CODR. The defined value is effec- tive only if the pin is controlled by the PIO Controller and only if the pin is defined as an output. 1 = The output data for the corresponding line is programmed to 1. 0 = The output data for the corresponding line is programmed to 0. PIO Pin Data Status Register Register Name: PIO_PDSR Access Type: Read-only This register shows the state of the physical pin of the chip. The pin values are always valid, regardless of whether the pins are enabled as PIO, peripheral, input or output. The register reads as follows: 1 = The corresponding pin is at logic 1. 0 = The corresponding pin is at logic 0. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

6069A–ATARM–05/04 PIO Interrupt Enable Register Register Name: PIO_IER Access Type: Write-only This register is used to enable PIO interrupts on the corresponding pin. It has an effect whether PIO is enabled or not. 1 = Enables an interrupt when a change of logic level is detected on the corresponding pin. 0 = No effect. PIO Interrupt Disable Register Register Name: PIO_IDR Access Type: Write-only This register is used to disable PIO interrupts on the corresponding pin. It has an effect whether the PIO is enabled or not. 1 = Disables the interrupt on the corresponding pin. Logic level changes are still detected. 0 = No effect. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

94 AT91C140

6069A–ATARM–05/04 PIO Interrupt Mask Register Register Name: PIO_IMR Access Type: Read-only This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing to PIO_IER or PIO_IDR. 1 = Interrupt is enabled on the corresponding pin. 0 = Interrupt is not enabled on the corresponding pin. PIO Interrupt Status Register Register Name: PIO_ISR Access Type: Read-only This register indicates for each pin when a logic value change has been detected (rising or falling edge). This is valid whether the PIO is selected for the pin or not and whether the pin is an input or an output. The register is reset to zero following a read and at reset. 1 = At least one input change has been detected on the corresponding pin since the register was last read. 0 = No input change has been detected on the corresponding pin since the register was last read. 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0

connected to the ASB bus (and hence external memory) via a dedicated PDC. Figure 23. UART Block Diagram

96 AT91C140

Each UART channel has external signals as defined in Table 25. receiver and the transmitter. (ACLK) or the ARM Clock divided by 8 (ACLK/8). times lower than the system clock. Rate Generator Register). If US_BRGR is set to 0, the baud rate clock is disabled. Table 25. UART Pins Table 26. Clock Generator Table with Crystal Frequency of 16 MHz

98 AT91C140

received parity bit. If different, the parity error bit PARE in US_CSR is set. level, a framing error is generated. This sets FRAME in US_CSR. counter which is decremented at each bit period and reloaded at each byte reception. the wait for a first character with the STTTO (Start Time-out) bit in US_CR. on the falling edge of the serial clock. The number of data bits is selected in the CHRL field in US_MR. The parity bit is set according to the PAR field in US_MR. The number of stop bits is selected in the NBSTOP field in US_MR. the TXEMPTY bit in US_CSR is set. Figure 27. Character Transmission between two characters. The duration of the idle state is programmed in US_TTGR.

RXD line, it is sent to the TXD line. Programming the transmitter has no effect. Figure 28. Channel Modes channel. One is dedicated to the receiver, the other is dedicated to the transmitter. the ENDTX bit for the transmitter and by the ENDRX bit for the receiver.

100 AT91C140

6069A–ATARM–05/04 (ENDRX for the receiver, ENDTX for the transmitter in US_CSR) and can be pro- grammed to generate an interrupt. Transfers are then disabled until a new non-zero counter value is programmed. Modem Control and Status Signals NCTS: Clear to Send When low, this indicates that the modem or data set is ready to exchange data. The NCTS signal is a modem status input; its conditions can be tested by the CPU reading bit 4 (CTS) of the Modem Status Register. Bit 4 is the complement of the NCTS signal. Bit 0 (DCTS) of the Modem Status Register indicates whether the NCTS input has changed state since the previous read of the Modem Status Register. NCTS has no effect on the transmitter. NDCD: Data Carrier Detect When low, this indicates that the data carrier has been detected by the modem or data set. The NDCD signal is a modem status input; its condition can be tested by the CPU reading bit 7 (DCD) of the Modem Status Register. Bit 7 is the complement of the NDCD signal. Bit 3 (DDCD) of the Modem Status Register indicates whether the NDCD input pin has changed since the previous reading of the Modem Status Register. NDCD has no effect on the receiver. NDSR: Data Set Ready When low, this informs the modem or data set that the UART is ready to communicate. The NDSR signal is a modem status input; its condition can be tested by the CPU read- ing bit 5 (DSR) of the Modem Status Register. Bit 5 is the complement of the NDSR signal. Bit 1 (DDSR of the Modem Status Register) indicates whether the NDSR input has changed state since the previous read of the Modem Status Register. NDTR: Data Terminal Ready When low, this informs the modem or data set that the UART is ready to communicate. The NDTR output signal can be set to active low by programming bit 0 (DTR) of the Modem Control Register to a high level. A master reset operation sets this signal to its inactive (high) state. Loop mode operation holds this signal in its inactive state. NRI: Ring Indicator When low, this indicates that a telephone ringing signal has been received by the modem or data set. The NRI signal is a modem status input; its condition can be tested by the CPU reading bit 6 (RI) of the Modem Status Register. Bit 6 is the complement of the NRI signal. Bit 2 (TERI) of the Modem Status Register indicates whether the NRI input signal has changed from a low to a high state since the previous read of the Modem Status Register. NRTS: Request to Send When low, this informs the modem or data set that the UART is ready to exchange data. The NRTS output signal can be set to an active low by programming bit 1 (RTS) of the Modem Control Register. A master reset operation sets this signal to its inactive (high) state.

Table 27. UART Memory Map

102 AT91C140

6069A–ATARM–05/04 UART Control Register Name: US_CR Access Type: Write-only  RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset.  RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset.  RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0.  RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled.  TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0.  TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled.  RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –

6069A–ATARM–05/04 UART Mode Register Name: US_MR Access Type: Read/Write  USCLKS: Clock Selection  CHRL: Character Length  PAR: Parity Type  NBSTOP: Number of Stop Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CHMODE NBSTOP PA R – 7 6 5 4 3 2 1 0 CHRL USCLKS – – – – USCLKS Selected Clock

00 A C L K

01 A C L K / 8

1 X External (SCK)

00 F i v e b i t s

01 S i x b i t s

000 E v e n p a r i t y

0 1 0 Parity forced to 0 (space) 0 1 1 Parity forced to 1 (mark) 10x N o p a r i t y NBSTOP 00 1 stop bit 01 1.5 stop bits 10 2 stop bits

11 Reserved

104 AT91C140

6069A–ATARM–05/04  CHMODE: Channel Mode CHMODE Mode Description 0 0 Normal Mode The UART channel operates as an Rx/Tx UART. 0 1 Automatic Echo Receiver data input is connected to TXD pin. 1 0 Local Loopback Transmitter output signal is connected to receiver input signal. 1 1 Remote Loopback RXD pin is internally connected to TXD pin.

6069A–ATARM–05/04 UART Interrupt Enable Register Name: US_IER Access Type: Write-only  RXRDY: Enable RXRDY Interrupt  TXRDY: Enable TXRDY Interrupt  ENDRX: Enable End of Receive Transfer Interrupt  ENDTX: Enable End of Transmit Transfer Interrupt  OVRE: Enable Overrun Error Interrupt  FRAME: Enable Framing Error Interrupt  PARE: Enable Parity Error Interrupt  TXEMPTY: Enable TXEMPTY Interrupt  DMSI: Delta Modem Interrupt 0 = No effect. 1 = Enables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA RE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY

106 AT91C140

6069A–ATARM–05/04 UART Interrupt Disable Register Name: US_IDR Access Type: Write-only  RXRDY: Disable RXRDY Interrupt  TXRDY: Disable TXRDY Interrupt  ENDRX: Disable End of Receive Transfer Interrupt  ENDTX: Disable End of Transmit Transfer Interrupt  OVRE: Disable Overrun Error Interrupt  FRAME: Disable Framing Error Interrupt  PARE: Disable Parity Error Interrupt  TXEMPTY: Disable TXEMPTY Interrupt  DMSI: Disable Delta Modem Interrupt 0 = No effect. 1 = Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA RE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY

6069A–ATARM–05/04 UART Interrupt Mask Register Name: US_IMR Access Type: Read-only  RXRDY: RXRDY Interrupt Mask  TXRDY: TXRDY Interrupt Mask  ENDRX: End of Receive Transfer Interrupt Mask  ENDTX: End of Transmit Transfer Interrupt Mask  OVRE: Overrun Error Interrupt Mask  FRAME: Framing Error Interrupt Mask  PARE: Parity Error Interrupt Mask  TXEMPTY: TXEMPTY Interrupt Mask  DMSI: Delta Modem Status Indication Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA RE FRAME OVRE ENDTX ENDRX RXBRK – RXRDY

108 AT91C140

6069A–ATARM–05/04 UART Channel Status Register Name: US_CSR Access Type: Read-only  RXRDY: Receiver Ready 0 = No complete character has been received since the last read of the US_RHR or the receiver is disabled. 1 = At least one complete character has been received and the US_RHR has not yet been read.  TXRDY: Transmitter Ready 0 = US_THR contains a character waiting to be transferred to the Transmit Shift Register. 1 = US_THR is empty and there is no break request pending TSR availability. Equal to zero when the UART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one.  ENDRX: End-of-receive Transfer 0 = The end-of-transfer signal from the PDC channel dedicated to the receiver is inactive. 1 = The end-of-transfer signal from the PDC channel dedicated to the receiver is active.  ENDTX: End-of-transmit Transfer 0 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is inactive. 1 = The end-of-transfer signal from the PDC channel dedicated to the transmitter is active.  OVRE: Overrun Error 0 = No byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last reset status bits command. 1 = At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last reset status bits command.  FRAME: Framing Error 0 = No stop bit has been detected low since the last reset status bits command. 1 = At least one stop bit has been detected low since the last reset status bits command.  PARE: Parity Error 1 = At least one parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bit” command. 0 = No parity bit has been detected false (or a parity bit high in multi-drop mode) since the last reset status bits command.  TXEMPTY: Transmitter Empty 0 = There are characters in either US_THR or the Transmit Shift Register or a break is being transmitted. 1 = There are no characters in US_THR and the Transmit Shift Register and break is not active. Equal to zero when the UART is disabled or at reset. Transmitter enable command (in US_CR) sets this bit to one.  DMSI: Delta Modem Status Indication Interrupt 0 = No effect. 1 = There has been a change in the modem status delta bits since the last reset status bits command. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA RE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY

6069A–ATARM–05/04 UART Receiver Holding Register Name: US_RHR Access Type: Read-only  RXCHR: Received Character Last character received if RXRDY is set. When number of data bits is less than eight, the bits are right-aligned. UART Transmitter Holding Register Name: US_THR Access Type: Write-only  TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than eight, the bits are right-aligned. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXCHR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCHR

110 AT91C140

6069A–ATARM–05/04 UART Baud Rate Generator Register Name: US_BRGR Access Type: Read/Write  CD: Clock Divisor This register has no effect if synchronous mode is selected with an external clock. UART Receive Pointer Register Name: US_RPR Access Type: Read/Write  RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 CD 7 6 5 4 3 2 1 0 CD CD Effect

0 Disables clock

1 Clock divisor bypass

2 to 65535 Baud rate = Selected clock/(16 x CD) 31 30 29 28 27 26 25 24 RXPTR 23 22 21 20 19 18 17 16 RXPTR 15 14 13 12 11 10 9 8 RXPTR 7 6 5 4 3 2 1 0 RXPTR

6069A–ATARM–05/04 UART Receive Counter Register Name: US_RCR Access Type: Read/Write Reset Value: 0x0  RXCTR: Receive Counter RXCTR must be loaded with the size of the receive buffer. 0 =Stop peripheral data transfer dedicated to the receiver. 1 - 65535: Start peripheral data transfer if RXRDY is active. UART Transmit Pointer Register Name: US_TPR Access Type: Read/Write Reset Value: 0x0  TXPTR: Transmit Pointer TXPTR must be loaded with the address of the transmit buffer. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXCTR 7 6 5 4 3 2 1 0 RXCTR 31 30 29 28 27 26 25 24 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 7 6 5 4 3 2 1 0 TXPTR

112 AT91C140

6069A–ATARM–05/04 UART Transmit Counter Register Name: US_TCR Access Type: Read/Write Reset Value: 0x0  TXCTR: Transmit Counter TXCTR must be loaded with the size of the transmit buffer. 0 =Stop peripheral data transfer dedicated to the transmitter. 1 - 65535: Start peripheral data transfer if TXRDY is active. Modem Control Register Register Name: US_MC Access Type: Write-only Reset Value: Undefined This register controls the interface with the modem or data set (or a peripheral device emulating a modem). The contents of the Control Register are indicated below.  DTR: Data Terminal Ready This bit controls the NDTR output. When bit 0 is set to a logic 1, the NDTR output is forced to a logic 0. When bit 0 is reset to a logic 0, the NDTR output is forced to a logic 1. The NDTR output of the UART can be applied to an EIA inverting line driver to obtain proper polarity input at the succeed- ing modem or data set.  RTS: Request to Send This bit controls the NRTS output. Bit 1 affects the NRTS output in a manner identical to that described above for bit 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXCTR 7 6 5 4 3 2 1 0 TXCTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

6069A–ATARM–05/04 Modem Status Register Register Name: US_MS Access Type: Read-only This register provides the current state of the control lines from the modem (or peripheral device) to the CPU. In addition to this current-state information, four bits of the Modem Status Register provide change information. These bits are set to a logic 1 whenever a control input from the modem changes state. They are reset to logic 0 whenever the CPU reads the Modem Status Register.  DCTS: Delta Clear to Send Bit 0 indicates that the NCTS input to the chip has changed state since the last time it was read by the CPU.  DDSR: Delta Data Set Ready Bit 1 indicates that the NDSR input to the chip has changed state since the last time it was read by the CPU.  TERI: Trailing Edge Ring Indicator Bit 2 indicates that the NRI input to the chip has changed from a low to a high state.  DDCD: Delta Data Carrier Detect Bit 3 indicates that the NDCD input has changed state. Note that whenever bit 0, 1, 2, or 3 is set to logic 1, a modem status interrupt is generated. This is reflected in the modem status register.  CTS: Clear to Send This bit is the complement of the Clear to Send (NCTS) input.  DSR: Data Set Ready This bit is the complement of the Data Set Ready (NDSR) input.  RI: Ring Indicator This bit is the complement of the Ring Indicator (NRI) input.  DCD: Data Carrier Detect This bit is the complement of the Data Carrier Detect (NDCD) input. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DCD RI DSR CTS DDCD TERI DDSR DCTS

114 AT91C140

6069A–ATARM–05/04 Timer/Counter (TC) The AT91C140 features a timer/counter block that includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval mea- surement, pulse generation, delay timing and pulse-width modulation. Each timer/counter channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals that can be configured by the user. Each channel drives an internal interrupt signal that can be programmed to generate proces- sor interrupts via the AIC. The timer/counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each timer/counter channel, allowing them to be chained.

Figure 29. Timer/Counter Block Diagram Table 28. Timer Counter Signal Description

116 AT91C140

trolled by the peripheral before being used. Description The three timer/counter channels are independent and identical in operation. COVFS bit in TC_SR (Status Register) is set. the next valid edge of the selected clock. TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). allows counting on the opposite edges of the clock. BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). times lower than the system clock (ACLK).

Figure 30. Clock Selection

1. The clock can be enabled or disabled by the user with the CLKEN and the CLK-

CLKSTA bit is set in the Status Register.

1. The clock can also be started or stopped: a trigger (software, synchro, external

have an effect only if the clock is enabled.

1. Capture mode allows measurement on signals
2. Waveform mode allows wave generation

118 AT91C140

Figure 31. Clock Control common to both modes, and a fourth external trigger is available to each mode.

1. Software trigger: Each channel has a software trigger, available by setting
2. SYNC: Each channel has a synchronization signal, SYNC. When asserted, this
3. Compare RC trigger: RC is implemented in each channel and can provide a trig-

ger when the counter value matches the RC value if CPCTRG is set in TC_CMR. clock (ACLK) period in order to be detected. especially when a low-frequency signal is selected as the clock.

6069A–ATARM–05/04 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture mode allows the TC Channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are inputs. Figure 32 shows the configuration of the TC Channel when programmed in capture mode. Capture Registers A and B (RA and RB) Registers A and B are used as capture registers; thus, they can be loaded with the counter value when a programmable event occurs on the TIOA signal. The parameter LDRA in TC_CMR defines the TIOA edge for the loading of Register A, and the parameter LDRB defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. Bit ABETRG in TC_CMR selects input signal TIOA or TIOB as an external trigger. Parameter ETRGEDG defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. Status Register The following bits in the status register are significant in capture operating mode.  CPCS: RC Compare Status There has been an RC Compare match at least once since the last read of the status.  COVFS: Counter Overflow Status The counter has attempted to count past $FFFF since the last read of the status.  LOVRS: Load Overrun Status RA or RB has been loaded at least twice without any read of the corresponding reg- ister since the last read of the status.  LDRAS: Load RA Status RA has been loaded at least once without any read since the last read of the status.  LDRBS: Load RB Status RB has been loaded at least once without any read since the last read of the status.  ETRGS: External Trigger Status An external trigger on TIOA or TIOB has been detected since the last read of the status.

120 AT91C140

Figure 32. Capture Mode ent types of one-shot or repetitive pulses. as an external event (EEVT parameter in TC_CMR). In waveform operating mode, RA, RB and RC are all used as compare registers. able the counter clock (CPCDIS = 1 in TC_CMR).

resets the counter so RC can control the period of PWM waveforms. XC1, XC2) or TIOB. The external event selected can then be used as a trigger. both). If EEVTEDG is cleared (none), no external event is defined. output and the TC channel can only generate a waveform on TIOA. are also available as triggers. event. TIOB control is used only if TIOB is defined as output (not as an external event). sponding parameter in TC_CMR. Table 29. TIOA Events Table 30. TIOB Events

122 AT91C140

6069A–ATARM–05/04 Status The following bits in the status register are significant in waveform mode:  CPAS: RA Compare Status There has been a RA Compare match at least once since the last read of the status  CPBS: RB Compare Status There has been a RB Compare match at least once since the last read of the status  CPCS: RC Compare Status There has been a RC Compare match at least once since the last read of the status  COVFS: Counter Overflow Counter has attempted to count past $FFFF since the last read of the status  ETRGS: External Trigger External trigger has been detected since the last read of the status

Figure 33. Waveform Mode

124 AT91C140

the corresponding channel as specified in Table 31. Note: 1. Read only if WAVE = 0. Table 31. TC Global Memory Map Table 32. TC Channel Memory Map

6069A–ATARM–05/04 TC Block Control Register Register Name: TC_BCR Access Type: Write-only  SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

126 AT91C140

6069A–ATARM–05/04 TC Block Mode Register Register Name: TC_BMR Access Type: Read/Write  TC0XC0S: External Clock Signal 0 Selection  TC1XC1S: External Clock Signal 1 Selection  TC2XC2S: External Clock Signal 2 Selection 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 – – TC2XC2S TC1XC1S TC0XC0S TC0XC0S Signal Connected to XC0

00 T C L K 0

01 N o n e

10 T I O A 1

11 T I O A 2

00 T C L K 1

10 T I O A 0

TC2XC2S Signal Connected to XC2

00 T C L K 2

11 T I O A 1

6069A–ATARM–05/04 TC Channel Control Register Register Name: TC_CCR Access Type: Write-only  CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1.  CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock.  SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and clock is started. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN

128 AT91C140

6069A–ATARM–05/04 TC Channel Mode Register: Capture Mode Register Name: TC_CMR Access Type: Read/Write  TCCLKS: Clock Selection  CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock.  BURST: Burst Signal Selection  LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs.  LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – – LDRB LDRA 15 14 13 12 11 10 9 8 WAVE CPCTRG – – – ABETRG ETRGEDG 7 6 5 4 3 2 1 0 LDBDIS LDBSTOP BURST CLKI TCCLKS TCCLKS Clock Selected

000 A C L K / 2

001 A C L K / 8

010 A C L K / 3 2

101 X C 0

110 X C 1

111 X C 2

0 0 The clock is not gated by an external signal. 0 1 XC0 is ANDed with the selected clock. 1 0 XC1 is ANDed with the selected clock. 1 1 XC2 is ANDed with the selected clock.

6069A–ATARM–05/04  ETRGEDG: External Trigger Edge Selection  ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger.  CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. W A V E 0 = Capture mode is enabled. 1 = Capture mode is disabled (waveform mode is enabled).  LDRA: RA Loading Selection  LDRB: RB Loading Selection ETRGEDG Edge 0 0 None 0 1 Rising edge 1 0 Falling edge 1 1 Each edge LDRA Edge 0 0 None 0 1 Rising edge of TIOA 1 0 Falling edge of TIOA 1 1 Each edge of TIOA LDRB Edge

00 N o n e

130 AT91C140

6069A–ATARM–05/04 TC Channel Mode Register: Waveform Mode Register Name: TC_CMR Access Type: Read/Write  TCCLKS: Clock Selection  CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock.  BURST: Burst Signal Selection  CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC.  CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. 31 30 29 28 27 26 25 24 BSWTRG BEEVT BCPC BCPB 23 22 21 20 19 18 17 16 ASWTRG AEEVT ACPC ACPA 15 14 13 12 11 10 9 8 WAVE CPCTRG – ENETRG EEVT EEVTEDG 7 6 5 4 3 2 1 0 CPCDIS CPCSTOP BURST CLKI TCCLKS TCCLKS Clock Selected 0 0 The clock is not gated by an external signal. 0 1 XC0 is ANDed with the selected clock. 1 0 XC1 is ANDed with the selected clock. 1 1 XC2 is ANDed with the selected clock.

6069A–ATARM–05/04  EEVTEDG: External Event Edge Selection  EEVT: External Event Selection Note: If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.  ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock.  CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. W A V E 0 = Waveform mode is disabled (Capture mode is enabled). 1 = Waveform mode is enabled.  ACPA: RA Compare Effect on TIOA  ACPC: RC Compare Effect on TIOA EEVTEDG Edge 0 0 TIOB Input (1) 0 1 XC0 Output 1 0 XC1 Output 1 1 XC2 Output ACPA Effect 0 0 None

01 S e t

10 C l e a r

11 T o g g l e

132 AT91C140

6069A–ATARM–05/04  AEEVT: External Event Effect on TIOA  ASWTRG: Software Trigger Effect on TIOA  BCPB: RB Compare Effect on TIOB  BCPC: RC Compare Effect on TIOB  BEEVT: External Event Effect on TIOB AEEVT Effect

6069A–ATARM–05/04  BSWTRG: Software Trigger Effect on TIOB TC Counter Value Register Register Name: TC_CVR Access Type: Read-only  CV: Counter Value CV contains the counter value in real-time. BSWTRG Effect

134 AT91C140

6069A–ATARM–05/04 TC Register A Register Name: TC_RA Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1  RA: Register A RA contains the Register A value in real-time. TC Register B Register Name: TC_RB Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1  RB: Register B RB contains the Register B value in real-time. TC Register C Register Name: TC_RC Access Type: Read/Write  RC: Register C RC contains the Register C value in real-time. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RA 7 6 5 4 3 2 1 0 RA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RB 7 6 5 4 3 2 1 0 RB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RC 7 6 5 4 3 2 1 0 RC

6069A–ATARM–05/04 TC Status Register Register Name: TC_SR Access Type: Read-only  COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register.  LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta- tus Register if WAVE = 0.  CPAS: RA Compare Status 0 = RA compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA compare has occurred since the last read of the Status Register if WAVE = 1.  CPBS: RB Compare Status 0 = RB compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB compare has occurred since the last read of the Status Register if WAVE = 1.  CPCS: RC Compare Status 0 = RC compare has not occurred since the last read of the Status Register. 1 = RC compare has occurred since the last read of the Status Register.  LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.  LDRBS: RB Loading Status 0 = RB load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB load has occurred since the last read of the Status Register if WAVE = 0.  ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register.  CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled.  MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, then TIOA pin is low. If WAVE = 1, then TIOA is driven low. 1 = TIOA is high. If WAVE = 0, then TIOA pin is high. If WAVE = 1, then TIOA is driven high. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CP AS LOVRS COVFS

136 AT91C140

6069A–ATARM–05/04  MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, then TIOB pin is low. If WAVE = 1, then TIOB is driven low. 1 = TIOB is high. If WAVE = 0, then TIOB pin is high. If WAVE = 1, then TIOB is driven high. TC Interrupt Enable Register Register Name: TC_IER Access Type: Write-only  COVFS: Counter Overflow  LOVRS: Load Overrun  CPAS: RA Compare  CPBS: RB Compare  CPCS: RC Compare  LDRAS: RA Loading  LDRBS: RB Loading  ETRGS: External Trigger 0 = No effect. 1 = Enables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CP AS LOVRS COVFS

6069A–ATARM–05/04 TC Interrupt Disable Register Register Name: TC_IDR Access Type: Write-only  COVFS: Counter Overflow  LOVRS: Load Overrun  CPAS: RA Compare  CPBS: RB Compare  CPCS: RC Compare  LDRAS: RA Loading  LDRBS: RB Loading  ETRGS: External Trigger 0 = No effect. 1 = Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CP AS LOVRS COVFS

138 AT91C140

6069A–ATARM–05/04 TC Interrupt Mask Register Register Name: TC_IMR Access Type: Read-only  COVFS: Counter Overflow  LOVRS: Load Overrun  CPAS: RA Compare  CPBS: RB Compare  CPCS: RC Compare  LDRAS: RA Loading  LDRBS: RB Loading  ETRGS: External Trigger 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CP AS LOVRS COVFS

6069A–ATARM–05/04 Serial Peripheral Interface (SPI) The AT91C140 embeds a Serial Peripheral Interface featuring:  Four Chip Selects with External Decoder Support Allowing Communication with Up to 15 Peripherals  Serial Memories, such as DataFlash and 3-wire EEPROMS  Serial Peripherals, such as ADCS, DACS, LCD Controllers, CAN Controllers And Sensors  External Co-processors  Master or Slave Serial Peripheral Bus Interface  8- to 16-bit Programmable Data Length Per Chip Select  Programmable Phase and Polarity Per Chip Select  Programmable Transfer Delays Between Consecutive Transfers and Between Clock and Data Per Chip Select  Programmable Delay Between Consecutive Transfers  Selectable Mode Fault Detection  Connection to PDC Channel Capabilities Optimizes Data Transfers  One Channel for the Receiver, One Channel for the Transmitter Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that pro- vides communication with external devices in Master or Slave Mode. It also allows communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' that controls the data flow, while the other system acts as the “slave'' that has data shifted into and out of it by the master. Different CPUs can take turn being masters (Multiple Master Protocol ver- sus Single Master Protocol, where one CPU is always the master while all of the others are always slaves), and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.

140 AT91C140

Figure 34. Block Diagram

Figure 35. Application Block Diagram: Single Master/Multiple Slave Implementation when the core writes to the SPI_TDR (Transmit Data Register). Table 33. I/O Lines Description

142 AT91C140

6069A–ATARM–05/04 SPI_TDR, the SPI continues to transfer data. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error (OVRES) flag is set. Note: As long as this flag is set, no data is loaded in the SPI_RDR. The user has to read the status register to clear it. The delay between the activation of the chip select and the start of the data transfer (DLYBS), as well as the delay between each data transfer (DLYBCT), can be pro- grammed for each of the four external chip selects. All data transfer characteristics, including the two timing values, are programmed in registers SPI_CSR0 to SPI_CSR3 (Chip Select Registers). In Master Mode, the peripheral selection can be defined in two different ways:  Fixed Peripheral Select: SPI exchanges data with only one peripheral  Variable Peripheral Select: Data can be exchanged with more than one peripheral Figure 39 and Figure 40 show the operation of the SPI in Master Mode. For details con- cerning the flag and control bits in these diagrams, see “SPI Chip Select Register” on page 157. Fixed Peripheral Select This mode is used for transferring memory blocks without the extra overhead in the transmit data register to determine the peripheral. Fixed Peripheral Select is activated by setting bit PS to zero in SPI_MR (Mode Regis- ter). The peripheral is defined by the PCS field in SPI_MR. This option is only available when the SPI is programmed in Master Mode. Variable Peripheral Select Variable Peripheral Select is activated by setting the PS bit to one. The PCS field in SPI_TDR is used to select the destination peripheral. The data transfer characteristics are changed when the selected peripheral changes, depending on the associated chip select register. The PCS field in the SPI_MR has no effect. This option is available only when the SPI is programmed in Master Mode. Chip Selects The Chip Select lines are driven by the SPI only if it is programmed in Master Mode. These lines are used to select the destination peripheral. The PCSDEC field in SPI_MR (Mode Register) selects one to four peripherals (PCSDEC = 0) or up to 15 peripherals (PCSDEC = 1). If Variable Peripheral Select is active, the chip select signals are defined for each trans- fer in the PCS field in SPI_TDR. Chip select signals can thus be defined independently for each transfer. If Fixed Peripheral Select is active, Chip Select signals are defined for all transfers by the field PCS in SPI_MR. If a transfer with a new peripheral is necessary, the software must wait until the current transfer is completed, then change the value of PCS in SPI_MR before writing new data in SPI_TDR. The value on the NPCS pins at the end of each transfer can be read in the SPI_RDR (Receive Data Register). By default, all NPCS signals are high (equal to one) before and after each transfer. Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS[0]/NSS signal.

6069A–ATARM–05/04 When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is disabled until re-enabled by bit SPIEN in the SPI_CR (Control Register). By default, Mode Fault Detection is enabled. It is disabled by setting the MODFDIS bit in the SPI Mode Register.

144 AT91C140

Figure 36. Master Mode Flow Diagram

Figure 37. Master Mode Block Diagram

146 AT91C140

transfer characteristics. The other Chip Select Registers are not used in Slave Mode. Figure 38. Slave Mode Block Diagram

148 AT91C140

Figure 40. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) between master and slave devices. CPOL defines the inactive value of the SPCK.

• Not defined but normally LSB of previous character transmitted.

Table 35. SPI Memory Map

150 AT91C140

6069A–ATARM–05/04 SPI Control Register Name : SPI_CR Access Type: Write-only  SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data.  SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled  SWRST: SPI Software Reset 0 = No effect. 1 = Resets the SPI. A software-triggered hardware reset of the SPI interface is performed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 SWRST – – – – – SPIDIS SPIEN

6069A–ATARM–05/04 SPI Mode Register Name: SPI_MR Access Type: Read/Write  MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode.  PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select.  PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 15*. *Note: The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration to be defined by each chip select register.  DIV32: Clock Selection 0 = SPI Master Clock equals ACK. 1 = SPI Master Clock equals ACK/32.  MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled.  LLB: Local Loopback Enable 0 = Local loopback path disabled 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only. 31 30 29 28 27 26 25 24 DLYBCS 23 22 21 20 19 18 17 16 – – – – PCS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LLB – – MODFDIS DIV32 PCSDEC PS MSTR

152 AT91C140

6069A–ATARM–05/04  PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS  DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DL YBCS time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six SPI Master Clock periods will be inserted by default. Otherwise, the following equation determines the delay: NPCS_to_SCK_Delay = DL YBCS * SPI_Master_Clock_period

6069A–ATARM–05/04 SPI Receive Data Register Name: SPI_RDR Access Type: Read-only  RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.  PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. SPI Transmit Data Register Name: SPI_TDR Access Type: Write-only  TD: Transmit Data Data to be transmitted by the SPI is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 PCS = xx01 NPCS[3:0] = 1101 PCS = x011 NPCS[3:0] = 1011 PCS = 0111 NPCS[3:0] = 0111 PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – – PCS 15 14 13 12 11 10 9 8 RD 7 6 5 4 3 2 1 0 RD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 – – – – PCS 15 14 13 12 11 10 9 8 TD 7 6 5 4 3 2 1 0 TD

154 AT91C140

6069A–ATARM–05/04 SPI Status Register Name: SPI_SR Access Type: Read-only  RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR.  TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.  MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR.  OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.  ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR. 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR.  ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR. 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR.  SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 – – ENDTX ENDRX OVRES MODF TDRE RDRF

6069A–ATARM–05/04 SPI Interrupt Enable Register Name: SPI_IER Access Type: Write-only  RDRF: Receive Data Register Full Interrupt Enable  TDRE: SPI Transmit Data Register Empty Interrupt Enable  MODF: Mode Fault Error Interrupt Enable  OVRES: Overrun Error Interrupt Enable  ENDRX: End of Receive Buffer Interrupt Enable  ENDTX: End of Transmit Buffer Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. SPI Interrupt Disable Register Name: SPI_IDR Access Type: Write-only  RDRF: Receive Data Register Full Interrupt Disable  TDRE: SPI Transmit Data Register Empty Interrupt Disable  MODF: Mode Fault Error Interrupt Disable  OVRES: Overrun Error Interrupt Disable  ENDRX: End of Receive Buffer Interrupt Disable  ENDTX: End of Transmit Buffer Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 – – ENDTX ENDRX OVRES MODF TDRE RDRF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 – – ENDTX ENDRX OVRES MODF TDRE RDRF

156 AT91C140

6069A–ATARM–05/04 SPI Interrupt Mask Register Name: SPI_IMR Access Type: Read-only  RDRF: Receive Data Register Full Interrupt Mask  TDRE: SPI Transmit Data Register Empty Interrupt Mask  MODF: Mode Fault Error Interrupt Mask  OVRES: Overrun Error Interrupt Mask  ENDRX: End of Receive Buffer Interrupt Mask  ENDTX: End of Transmit Buffer Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 – – ENDTX ENDRX OVRES MODF TDRE RDRF

6069A–ATARM–05/04 SPI Chip Select Register Name: SPI_CSR0... SPI_CSR3 Access Type: Read/Write  CPOL: Clock Polarity 0 = The inactive state value of SCK is logic level zero. 1 = The inactive state value of SCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.  NCPHA: Clock Phase 0 = Data is changed on the leading edge of SCK and captured on the following edge of SCK. 1 = Data is captured on the leading edge of SCK and changed on the following edge of SCK. NCPHA determines which edge of SCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.  BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. 31 30 29 28 27 26 25 24 DL YBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 7 6 5 4 3 2 1 0 BITS – – NCPHA CPOL BITS[3:0] Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

158 AT91C140

6069A–ATARM–05/04  SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the SPI Master Clock (selected between CLOCK and FDIV). The Baud rate is selected by writing a value from 2 to 255 in the field SCBR. The fol- lowing equation determines the SPCK baud rate: SPCK Baudrate = SPI_Master_Clock / (2 * SCBR) Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state value. No serial transfers may occur. At reset, baud rate is disabled.  DLYBS: Delay Before SCK This field defines the delay from NPCS valid to the first valid SCK transition. When DL YBS equals zero, the NPCS valid to SCK transition is 1/2 the SCK clock period. Otherwise, the following equation determines the delay: NPCS_to_SCK_Delay = DL YBS * SPI_Master_Clock_period  DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DL YBCT equals zero, a delay of four SPI Master Clock periods are inserted. Otherwise, the following equation determines the delay: Delay_After_Transfer = 32 * DL YBCT * SPI_Master_Clock_period.

6069A–ATARM–05/04 SPI Receive Pointer Register Register Name: SPI_RPR Access Type: Read/Write  RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer. SPI Receive Counter Register Register Name: SPI_RCR Access Type: Read/Write  RXCTR: Receive Counter Register RXCTR must be loaded with the size of the receive buffer. 0 = Stops peripheral data transfer 1 - 65535 = Start peripheral data transfer if RDRF is active. 31 30 29 28 27 26 25 24 RXPTR 23 22 21 20 19 18 17 16 RXPTR 15 14 13 12 11 10 9 8 RXPTR 7 6 5 4 3 2 1 0 RXPTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RXCTR 7 6 5 4 3 2 1 0 RXCTR

160 AT91C140

6069A–ATARM–05/04 SPI Transmit Pointer Register Register Name: SP_TPR Access Type: Read/Write  TXPTR: Transmit Pointer Register TXPTR must be loaded with the address of the transmit buffer. SPI Transmit Counter Register Register Name: SP_TCR Access Type: Read/Write  TXCTR: Transmit Counter Register TXCTR must be loaded with the size of the receive buffer. 0 = Stops peripheral data transfer 1 - 65535 = Start peripheral data transfer if TDRE is active. 31 30 29 28 27 26 25 24 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 7 6 5 4 3 2 1 0 TXPTR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 TXCTR 7 6 5 4 3 2 1 0 TXCTR

6069A–ATARM–05/04

Ordering Information

Table 36. Ordering Information

162 AT91C140

Figure 41. AT91C140 BGA Package

Table 37. Dimensions (mm)

164 AT91C140

6069A–ATARM–05/04

i AT91C140 6069A–ATARM–05/04

6069A–ATARM–05/04

6069A–ATARM–05/04

6069A–ATARM–05/04 Universal Asynchronous Receiver/Transmitter (UART) User Interface .... 101

v AT91C140 6069A–ATARM–05/04

6069A–ATARM–05/04 Table of Contents i

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