AT89C2051X2-16PI

AT89C2051X2 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Compatible with MCS® -51 Products  2K Bytes of Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles  2.7V to 6V Operating Range  Fully Static Operation: 0 Hz to 16 MHz  Two-level Program Memory Lock  128 x 8-bit Internal RAM  15 Programmable I/O Lines  Two 16-bit Timer/Counters  Six Interrupt Sources  Programmable Serial UART Channel  Direct LED Drive Outputs  On-chip Analog Comparator  Low-power Idle and Power-down Modes  6 Clocks per Machine Cycle Operation

Description

The AT89C2051x2 is a low-voltage, high-performance CMOS 8-bit microcontroller with 2K bytes of Flash programmable memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus- try-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051x2 is a powerful microcomputer which pro- vides a highly-flexible and cost-effective solution to many embedded control applications. The AT89C2051x2 provides the following standard features: 2K bytes of Flash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five-vector, two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C2051x2 is designed with static logic for oper- ation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Furthermore, the AT89C2051x2 executes one machine cycle in 6 clock cycles, provid- ing twice the speed of the AT89C2051 device. The user gains the flexibility to divide input frequency crystals by 2 (using less expensive components), while keeping the same CPU power. Alternatively, the user can save on power consumption while keep- ing the same CPU power (oscillator power saving). Pin Configuration PDIP/SOIC RST/VPP (RXD) P3.0 (TXD) P3.1 XTAL2 XTAL1 (INT0) P3.2 (INT1) P3.3 (TO) P3.4 (T1) P3.5 GND VCC P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 (AIN1) P1.0 (AIN0) P3.7 Rev. 3285B–MICRO–10/03 8-bit Microcontroller with 2K Bytes Flash AT89C2051x2

2 AT89C2051x2

3285B–MICRO–10/03 Block Diagram

3285B–MICRO–10/03 Pin Description VCC Supply voltage. GND Ground. Port 1 Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pull-ups. (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog com- parator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (I IL) because of the internal pull-ups. Port 1 also receives code data during Flash programming and verification. Port 3 Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-ups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not acces- sible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C2051x2 as listed below: Port 3 also receives some control signals for Flash programming and verification. RST Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device. Each machine cycle takes 6 oscillator or clock cycles. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input)

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source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. maximum voltage high and low time specifications must be observed. Figure 1. Oscillator Connections Figure 2. External Clock Drive Configuration clock generation block diagram. Figure 3. Clock Generation Block Diagram

and write accesses will have an indeterminate effect. Table 1. AT89C2051x2 SFR Map and Reset Values

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3285B–MICRO–10/03 Restrictions on Certain Instructions The AT89C2051x2 is an economical and cost-effective member of Atmel’s growing fam- ily of microcontrollers. It contains 2K bytes of Flash program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2K for the AT89C2051x2. This should be the responsibility of the software program- mer. For example, LJMP 7E0H would be a valid instruction for the AT89C2051x2 (with 2K of memory), whereas LJMP 900H would not. Branching Instructions LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR These unconditional branching instructions will execute correctly as long as the pro- grammer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to 7FFH for the AT89C2051x2). Violating the physical space limits may cause unknown program behavior. With these conditional branching instructions, the same rule above applies. Again, vio- lating the memory boundaries may cause erratic execution. For applications involving interrupts, the normal interrupt service routine address loca- tions of the 80C51 family architecture have been preserved. MOVX-related Instructions, Data Memory The AT89C2051x2 contains 128 bytes of internal data memory. Thus, in the AT89C2051x2, the stack depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is external PRO- GRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program. A typical 80C51 assembler will still assemble instructions, even if they are written in vio- lation of the restrictions mentioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly. Program Memory Lock Bits On the chip are two lock bits which can be left unprogrammed (U) or can be pro- grammed (P) to obtain the additional features listed in the table below: Lock Bit Protection Modes(1) Note: 1. The Lock Bits can only be erased with the Chip Erase operation. Program Lock Bits LB1 LB2 Protection Type 1 U U No program lock features. 2 P U Further programming of the Flash is disabled. 3 P P Same as mode 2, also verify is disabled.

3285B–MICRO–10/03 Idle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be termi- nated by any enabled interrupt or by a hardware reset. P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if external pull-ups are used. It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power-down Mode In the power-down mode the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if external pull-ups are used. Programming the Flash The AT89C2051x2 is shipped with the 2K bytes of on-chip Flash code memory array in the erased state (i.e., contents = FFH) and ready to be programmed. The code memory array is programmed one byte at a time. Once the array is programmed, to re-program any non-blank byte, the entire memory array needs to be erased electrically. Internal Address Counter: The AT89C2051x2 contains an internal memory address counter which is always reset to 000H on the rising edge of RST and is advanced by applying a positive going pulse to pin XTAL1. Programming Algorithm: To program the AT89C2051x2, the following sequence is recommended. 1. Power-up sequence: Apply power between V CC and GND pins Set RST and XTAL1 to GND 2. Set pin RST to “H” Set pin P3.2 to “H” 3. Apply the appropriate combination of “H” or “L” logic levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations shown in the Flash Programming Modes table. To Program and Verify the Array: 1. Apply data for Code byte at location 000H to P1.0 to P1.7. 2. Raise RST to 12V to enable programming. 3. Pulse P3.2 once to program a byte in the program memory array or the lock bits. The byte-write cycle is self-timed and typically takes 1.2 ms.

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3285B–MICRO–10/03 4. To verify the programmed data, lower RST from 12V to logic “H” level and set pins P3.3 to P3.7 to the appropriate levels. Output data can be read at the port P1 pins. 5. To program a byte at the next address location, pulse XTAL1 pin once to advance the internal address counter. Apply new data to the port P1 pins. 6. Repeat steps 6 through 8, changing data and advancing the address counter for the entire 2-Kbyte array or until the end of the object file is reached. 7. Power-off sequence: set XTAL1 to “L” set RST to “L” Tur n V CC power off Data Polling: The AT89C2051x2 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy : The Progress of byte programming can also be monitored by the RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes High during programming to indicate BUSY. P3.1 is pulled High again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed code data can be read back via the data lines for verification: 1. Reset the internal address counter to 000H by bringing RST from “L” to “H”. 2. Apply the appropriate control signals for Read Code data and read the output data at the port P1 pins. 3. Pulse pin XTAL1 once to advance the internal address counter. 4. Read the next code data byte at the port P1 pins. 5. Repeat steps 3 and 4 until the entire array is read. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire program memory array (2K bytes) and the two Lock Bits are erased electrically by using the proper combination of control signals and by holding P3.2 low for 10 ms. The code array is written with all “1”s in the Chip Erase operation and must be executed before any non-blank memory byte can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 001H, and 002H, except that P3.5 and P3.7 must be pulled to a logic low. The values returned are as follows. (000H) = 1EH indicates manufactured by Atmel (001H) = 22H indicates AT89C2051x2 Programming Interface Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self- timed and once initiated, will automatically time itself to completion. Most worldwide major programming vendors offer support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.

3285B–MICRO–10/03 Notes: 1. The internal memory address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at XTAL1 pin. 2. Chip Erase requires a 10 ms PROG pulse. 3. P3.1 is pulled Low during programming to indicate RDY/BSY. Flash Programming Modes Write Code Data(1)(3) 12V L H H H Read Code Data(1) HH L L H H Write Lock Bit - 1 12V H H H H Bit - 2 12V H H L L Chip Erase 12V H L L L Read Signature Byte H H L L L L (2)

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Figure 4. Programming the Flash Memory Figure 5. Verifying the Flash Memory

3285B–MICRO–10/03 Note: 1. Only used in 12-volt programming mode. Flash Programming and Verification Waveforms Flash Programming and Verification Characteristics TA = 0°C to 70°C, VCC = 5.0 ± 10% Symbol Parameter Min Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 250 µA tDVGL Data Setup to PROG Low 1.0 µs tGHDX Data Hold after PROG 1.0 µs tEHSH P3.4 (ENABLE) High to VPP 1.0 µs tSHGL VPP Setup to PROG Low 10 µs tGHSL VPP Hold after PROG 10 µs tGLGH PROG Width 1 110 µs tELQV ENABLE Low to Data Valid 1.0 µs tEHQZ Data Float after ENABLE 01 . 0 µ s tGHBL PROG High to BUSY Low 50 ns tWC Byte Write Cycle Time 2.0 ms tBHIH RDY/BSY \\ to Increment Clock Delay 1.0 µs tIHIL Increment Clock High 200 ns

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3285B–MICRO–10/03 Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 20 mA Maximum total IOL for all output pins: 80 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power-down is 2V. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol Parameter Condition Min Max Units VIL Input Low-voltage -0.5 0.2 V CC - 0.1 V VIH Input High-voltage (Except XT AL1, RST) 0.2 V CC + 0.9 V CC + 0.5 V VIH1 Input High-voltage (XTAL1, RST) 0.7 V CC VCC + 0.5 V VOL Output Low-voltage(1) (Ports 1, 3) IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 2.7V 0.5 V VOH Output High-voltage (Ports 1, 3) IOH = -80 µA, VCC = 5V ± 10% 2.4 V IOH = -30 µA 0.75 V CC V IOH = -12 µA 0.9 V CC V IIL Logical 0 Input Current (Ports 1, 3) VIN = 0.45V -50 µA ITL Logical 1 to 0 Transition Current (Ports 1, 3) VIN = 2V, VCC = 5V ± 10% -750 µA ILI Input Leakage Current (Port P1.0, P1.1) 0 < VIN < VCC ±10 µA VOS Comparator Input Offset Voltage VCC = 5V 20 mV VCM Comparator Input Common Mode Voltage 0V CC V RRST Reset Pull-down Resistor 50 300 K Ω C IO Pin Capacitance Test Freq. = 1 MHz, T A = 25°C 10 pF ICC Power Supply Current Active Mode, 12 MHz, V CC = 6V/3V 15/5.5 mA Idle Mode, 12 MHz, VCC = 6V/3V P1.0 & P1.1 = 0V or VCC 5/1 mA Power-down Mode(2) VCC = 6V, P1.0 & P1.1 = 0V or VCC 100 µA VCC = 3V, P1.0 & P1.1 = 0V or VCC 20 µA

External Clock Drive Waveforms External Clock Drive Symbol Parameter VCC = 2.7V to 6.0V V CC = 4.0V to 6.0V UnitsMin Max Min Max 1/tCLCL Oscillator Frequency 0 8 0 16 MHz tCLCL Clock Period 12.5 62.5 ns tCHCX High Time 45 22.5 ns tCLCX Low Time 45 22.5 ns tCLCH Rise Time 10 10 ns tCHCL Fall Time 10 10 ns tCHCX /tCLCX Cyclic Ratio (duty cycle) 40 60 40 60 %

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3285B–MICRO–10/03 Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0. Float Waveforms(1) Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH /VOL level occurs. Serial Port Timing: Shift Register Mode Test Conditions VCC = 5.0V ± 20%; Load Capacitance = 80 pF Symbol Parameter

12 MHz Osc Variable Oscillator

tXLXL Serial Port Clock Cycle Time 1.0 12t CLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10t CLCL -133 ns tXHQX Output Data Hold after Clock Rising Edge 50 2t CLCL -117 ns tXHDX Input Data Hold after Clock Rising Edge 0 0 ns tXHDV Clock Rising Edge to Input Data Valid 700 10t CLCL -133 ns

3285B–MICRO–10/03 Notes: 1. XTAL1 tied to GND for ICC (power-down). 3. Lock bits programmed. AT89C2051x2 TYPICAL ICC - ACTIVE (85˚C) 03 691 2 FREQUENCY (MHz) I C C m A Vcc=6.0V Vcc=5.0V Vcc=3.0V AT89C2051x2 TYPICAL ICC - IDLE (85˚C) 0 1.5 3 4.5 6 FREQUENCY (MHz) I C C m A Vcc=6.0V Vcc=5.0V Vcc=3.0V AT89C2051x2 TYPICAL ICC vs. VOLTAGE - POWER DOWN (85˚C) 3.0V 4.0V 5.0V 6.0V Vcc VOLTAGE I C C µ A

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3285B–MICRO–10/03

Ordering Information

(MHz) Power Supply Ordering Code Package Operation Range 8 2.7V to 6.0V AT89C2051x2-8PC AT89C2051x2-8SC 20P3 20S2 Commercial (0° C to 70° C) AT89C2051x2-8PI AT89C2051x2-8SI 20P3 20S2 Industrial (-40° C to 85° C) 16 4.0V to 6.0V AT89C2051x2-16PC AT89C2051x2-16SC 20P3 20S2 Commercial (0° C to 70° C) AT89C2051x2-16PI AT89C2051x2-16SI 20P3 20S2 Industrial (-40° C to 85° C) Package Type 20P3 20-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP) 20S2 20-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)

3285B–MICRO–10/03

Package Information

20P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131 TITLE DRAWING NO. R REV. 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) B20P3 09/28/01 PIN B E C L SEATING PLANE A D e eB eC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 5.334 A1 0.381 – – D 25.984 – 25.493 Note 2 E 7.620 – 8.255 E1 6.096 – 7.112 Note 2 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

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3285B–MICRO–10/03 20S2 – SOIC San Jose, CA 95131 TITLE DRAWING NO. R REV. 20S2, 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 1/9/02 20S2 A L End View Side View Top View HE b N e A D C COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "L" is the length of the terminal for soldering to a substrate. 5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. A 0.0926 0.1043 A1 0.0040 0.0118 b 0.0130 0.0200 4 C 0.0091 0.0125 D 0.4961 0.5118 1 E 0.2914 0.2992 2 H 0.3940 0.4190 L 0.0160 0.050 3 e 0.050 BSC

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