AT89C2051

AT89C2051_00 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Compatible with MCS-51™ Products  2K Bytes of Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles  2.7V to 6V Operating Range  Fully Static Operation: 0 Hz to 24 MHz  Two-level Program Memory Lock  128 x 8-bit Internal RAM  15 Programmable I/O Lines  Two 16-bit Timer/Counters  Six Interrupt Sources  Programmable Serial UART Channel  Direct LED Drive Outputs  On-chip Analog Comparator  Low-power Idle and Power-down Modes

Description

The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 2K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel ’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a power- ful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89C2051 provides the following standard features: 2K bytes of Flash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C2051 is designed with static logic for opera- tion down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Rev. 0368E–02/00 8-bit Microcontroller with 2K Bytes Flash AT89C2051

tion Register (SFR) space is shown in the table below. cupied addresses may not be implemented on the chip. the new bits will always be 0. Table 1. AT89C2051 SFR Map and Reset Values

Restrictions on Certain Instructions The AT89C2051 and is an economical and cost-effective member of Atmel ’s growing family of microcontrollers. It contains 2K bytes of flash program memory. It is fully com- patible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device. All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2K for the AT89C2051. This should be the responsibility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89C2051 (with 2K of memory), whereas LJMP 900H would not. 1. Branching instructions: LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to 7FFH for the 89C2051). Violating the physical space limits may cause unknown program behavior. these conditional branching instructions the same rule above applies. Again, violating the memory boundaries may cause erratic execution. For applications involving interrupts the normal interrupt service routine address locations of the 80C51 family archi- tecture have been preserved. 2. MOVX-related instructions, Data Memory: The AT89C2051 contains 128 bytes of internal data mem- ory. Thus, in the AT89C2051 the stack depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is exter- nal PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program. A typical 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions men- tioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used correspondingly. Program Memory Lock Bits On the chip are two lock bits which can be left unpro- grammed (U) or can be programmed (P) to obtain the additional features listed in the table below: Lock Bit Protection Modes(1) Note: 1. The Lock Bits can only be erased with the Chip Erase operation. Idle Mode In idle mode, the CPU puts itself to sleep while all the on- chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the spe- cial functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external pullups are used. It should be noted that when idle is terminated by a hard- ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power-down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Regis- ters retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external pullups are used. Program Lock Bits LB1 LB2 Protection Type 1 U U No program lock features.

2 P U Further programming of the Flash

is disabled.

3 P P Same as mode 2, also verify is

disabled.

The AT89C2051 is shipped with the 2K bytes of on-chip PEROM code memory array in the erased state (i.e., con- tents = FFH) and ready to be programmed. The code memory array is programmed one byte at a time. Once the array is programmed, to re-program any non-blank byte, the entire memory array needs to be erased electrically. Internal Address Counter: The AT89C2051 contains an internal PEROM address counter which is always reset to 000H on the rising edge of RST and is advanced by apply- ing a positive going pulse to pin XTAL1. Programming Algorithm: To program the AT89C2051, the following sequence is recommended. 1. Power-up sequence: Apply power between V CC and GND pins Set RST and XTAL1 to GND 2. Set pin RST to “H” Set pin P3.2 to “H” 3. Apply the appropriate combination of “H” or “L” logic levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations shown in the PEROM Pro- gramming Modes table. To Program and Verify the Array: 4. Apply data for Code byte at location 000H to P1.0 to P1.7. 5. Raise RST to 12V to enable programming. 6. Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-write cycle is self-timed and typically takes 1.2 ms. 7. To verify the programmed data, lower RST from 12V to logic “H” level and set pins P3.3 to P3.7 to the appropiate levels. Output data can be read at the port P1 pins. 8. To program a byte at the next address location, pulse XTAL1 pin once to advance the internal address counter. Apply new data to the port P1 pins. 9. Repeat steps 5 through 8, changing data and advancing the address counter for the entire 2K bytes array or until the end of the object file is reached. 10.Power-off sequence: set XTAL1 to “L” set RST to “L” Turn V CC power off Data Polling: The AT89C2051 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the com- plement of the written data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The Progress of byte programming can also be monitored by the RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes High during programming to indi- cate BUSY. P3.1 is pulled High again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed code data can be read back via the data lines for verification: 1. Reset the internal address counter to 000H by bringing RST from “L” to “H”. 2. Apply the appropriate control signals for Read Code data and read the output data at the port P1 pins. 3. Pulse pin XTAL1 once to advance the internal address counter. 4. Read the next code data byte at the port P1 pins. 5. Repeat steps 3 and 4 until the entire array is read. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire PEROM array (2K bytes) and the two Lock Bits are erased electrically by using the proper combination of control signals and by holding P3.2 low for 10 ms. The code array is written with all “1”s in the Chip Erase operation and must be executed before any non- blank memory byte can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 001H, and 002H, except that P3.5 and P3.7 must be pulled to a logic low. The values returned are as follows. (000H) = 1EH indicates manufactured by Atmel (001H) = 21H indicates 89C2051 Programming Interface Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combi- nation of control signals. The write operation cycle is self- timed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.

1. Chip Erase requires a 10 ms PROG pulse.
2. P3.1 is pulled Low during programming to indicate RDY/BSY .

Figure 3. Programming the Flash Memory Figure 4. Verifying the Flash Memory

Note: 1. Only used in 12-volt programming mode. Flash Programming and Verification Waveforms Flash Programming and Verification Characteristics TA = 0°C to 70°C, VCC = 5.0 ± 10% Symbol Parameter Min Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 250 µA tDVGL Data Setup to PROG Low 1.0 µs tGHDX Data Hold after PROG 1.0 µs tEHSH P3.4 (ENABLE) High to VPP 1.0 µs tSHGL VPP Setup to PROG Low 10 µs tGHSL VPP Hold after PROG 10 µs tGLGH PROG Width 1 110 µs tELQV ENABLE Low to Data Valid 1.0 µs tEHQZ Data Float after ENABLE 01 . 0 µs tGHBL PROG High to BUSY Low 50 ns tWC Byte Write Cycle Time 2.0 ms tBHIH RDY/BSY\\ to Increment Clock Delay 1.0 µs tIHIL Increment Clock High 200 ns

Notes: 1. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum IOL per port pin: 20 mA Maximum total IOL for all output pins: 80 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum V CC for Power-down is 2V. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin DC Characteristics TA = -40°C to 85°C, VCC = 2.0V to 6.0V (unless otherwise noted) Symbol Parameter Condition Min Max Units VIL Input Low-voltage -0.5 0.2 V CC - 0.1 V VIH Input High-voltage (Except XT AL1, RST) 0.2 V CC + 0.9 V CC + 0.5 V VIH1 Input High-voltage (XTAL1, RST) 0.7 V CC VCC + 0.5 V VOL Output Low-voltage(1) (Ports 1, 3) IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 2.7V 0.5 V VOH Output High-voltage (Ports 1, 3) IOH = -80 µA, VCC = 5V ± 10% 2.4 V IOH = -30 µA 0.75 V CC V IOH = -12 µA 0.9 V CC V IIL Logical 0 Input Current (Ports 1, 3) VIN = 0.45V -50 µA ITL Logical 1 to 0 Transition Current (Ports 1, 3) VIN = 2V, VCC = 5V ± 10% -750 µA ILI Input Leakage Current (Port P1.0, P1.1) 0 < VIN < VCC ±10 µA VOS Comparator Input Offset Voltage V CC = 5V 20 mV VCM Comparator Input Common Mode Voltage 0V CC V RRST Reset Pull-down Resistor 50 300 K Ω CIO Pin Capacitance Test Freq. = 1 MHz, T A = 25°C1 0 p F ICC Power Supply Current Active Mode, 12 MHz, V CC = 6V/3V 15/5.5 mA Idle Mode, 12 MHz, VCC = 6V/3V P1.0 & P1.1 = 0V or VCC 5/1 mA Power-down Mode(2) VCC = 6V P1.0 & P1.1 = 0V or VCC 100 µA VCC = 3V P1.0 & P1.1 = 0V or VCC 20 µA

External Clock Drive Waveforms External Clock Drive Symbol Parameter VCC = 2.7V to 6.0V V CC = 4.0V to 6.0V UnitsMin Max Min Max 1/tCLCL Oscillator Frequency 0 12 0 24 MHz tCLCL Clock Period 83.3 41.6 ns tCHCX High Time 30 15 ns tCLCX Low Time 30 15 ns tCLCH Rise Time 20 20 ns tCHCL Fall Time 20 20 ns

Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Note: 1. AC Inputs during testing are driven at V CC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0. Float Waveforms(1) Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change frothe loaded V OH/VOL level occurs. Serial Port Timing: Shift Register Mode Test Conditions VCC = 5.0V ± 20%; Load Capacitance = 80 pF Symbol Parameter

12 MHz Osc Variable Oscillator

tXLXL Serial Port Clock Cycle Time 1.0 12t CLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10t CLCL-133 ns tXHQX Output Data Hold after Clock Rising Edge 50 2t CLCL-117 ns tXHDX Input Data Hold after Clock Rising Edge 0 0 ns tXHDV Clock Rising Edge to Input Data Valid 700 10t CLCL-133 ns

TYPICAL ICC - ACTIVE (85°C) 0 6 12 18 24 FREQUENCY (MHz) I C C m A Vcc=6.0V Vcc=5.0V Vcc=3.0V AT89C2051 TYPICAL ICC - IDLE (85°C) 0369 1 2 FREQUENCY (MHz) I C C m A Vcc=6.0V Vcc=5.0V Vcc=3.0V AT89C2051 TYPICAL ICC vs. VOLTAGE- POWER DOWN (85°C) 3.0V 4.0V 5.0V 6.0V Vcc VOLTAGE I C C µ A Notes: 1. XT AL1 tied to GND for I CC (power-down) 2. P .1.0 and P1.1 = VCC or GND 3. Lock bits programmed

Ordering Information

(MHz) Power Supply Ordering Code Package Operation Range 12 2.7V to 6.0V AT89C2051-12PC AT89C2051-12SC 20P3 20S Commercial (0°C to 70°C) AT89C2051-12PI AT89C2051-12SI 20P3 20S Industrial (-40°C to 85°C) 24 4.0V to 6.0V AT89C2051-24PC AT89C2051-24SC 20P3 20S Commercial (0°C to 70°C) AT89C2051-24PI AT89C2051-24SI 20P3 20S Industrial (-40°C to 85°C) Package Type 20P3 20-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP) 20S 20-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)

1.060(26.9) .980(24.9) PIN .280(7.11) .240(6.10) .090(2.29) MAX .005(.127) MIN .015(.381) MIN .022(.559) .014(.356) .070(1.78) .045(1.13) .325(8.26) .300(7.62)

15 REF

.430(10.92) MAX .014(.356) .008(.203) .110(2.79) .090(2.29) .150(3.81) .115(2.92) SEATING PLANE .210(5.33) MAX .900(22.86) REF 0.299 (7.60) 0.291 (7.39) 0.020 (0.508) 0.393 (9.98) PIN 1 .050 (1.27) BSC 0.513 (13.0) 0.497 (12.6) 0.012 (0.305) 0.003 (0.076) 0.105 (2.67) 0.092 (2.34) 8 REF 0.035 (0.889) 0.015 (0.381) 0.013 (0.330) 0.009 (0.229) 20P3, 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 AD 20S, 20-lead, 0.300" Wide, Plastic Gull WIng Small Outline (SOIC) Dimensions in Inches and (Millimeters)

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