AT88SC0104CA ATMEL | Alldatasheet
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Technical content
- Features
- One of a Family of Devices with User Memories from 1-Kbit to 8-Kbits 1-Kbit (128-byte) EEPROM User Memory – Four 256-bit (32-byte) Zones – Self-timed Write Cycle – Single Byte or 16-byte Page Write Mode – Programmable Access Rights for Each Zone 2-Kbit Configuration Zone – 37-byte OTP Area for User-defined Codes – 160-byte Area for User-defined Keys and Passwords High Security Features – 64-bit Mutual Authentication Pr otocol (Under License of ELVA) – Cryptographic Message Authentication Codes (MAC) – Stream Encryption – Four Key Sets for Authen tication and Encryption – Eight Sets of Two 24-bit Passwords – Anti-Tearing Function – Voltage and Frequency Monitors Smart Card Features – ISO 7816 Class B (3V) Operation – ISO 7816-3 Asynchronous T=0 Protocol (Gemplus® Patent) – Multiple Zones, Key Sets and Passwords for Multi-application Use – Synchronous 2-wire Seri al Interface for Faster Device Initialization – Programmable 8-byte Answer-To-Reset Register – ISO 7816-2 Compliant Modules Embedded Application Features – Low Voltage Operation: 2.7V – 3.6V – Secure Nonvolatile Storage for Sensitive System or User Information – 2-wire Serial Interface – 1.0 MHz Compatibilit y for Fast Operation – Standard 8-lead Plastic Packages – Same Pin Configuration as AT24CXXX Serial EEPROM in SOIC and PDIP Packages High Reliability – Endurance: 100,000 Cycles – Data Retention: 10 years – ESD Protection: 2,000V min Table 1-1. Pads Pad Description ISO Module “SOIC, PDIP” TSSOP VCC Supply Voltage C1 8 8 GND Ground C5 4 1 SCL/CLK Serial Clock Input C3 6 6 SDA/IO Serial Data Input/Output C7 5 3 RST Reset Input C2 NC NC CryptoMemory AT88SC0104CA Summary 5200AS–CRYPT–7/08
5200AS–CRYPT–7/08 AT88SC0104CA 2. Description The AT88SC0104CA member of the CryptoMemory® family is a high-performance secure mem- ory providing 1 Kbit of user memory with adv anced security and cryptographic features built in. The user memory is divided into four 32-byte z ones, each of which may be individually set with different security access rights or effectively combined together to provide space for 1 to 4 data files. The AT88SC0104CA features an enhanced command set that allows direct communica- tion with microcontroller hardware 2-Wire in terface thereby allowing for faster firmware development with reduced code space requirements. 3. Smart Card Applications The AT88SC0104CA provides high security, low cost, and ease of implementation without the need for a microprocessor operating system. T he embedded cryptographic engine provides for dynamic, symmetric-mutual authentication between the device and host, as well as performing stream encryption for all data and passwords exchanged between the device and host. Up to four unique key sets may be used for these operations. The AT88SC0104CA offers the ability to communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gem- plus Patent) defined in ISO 7816-3. 4. Embedded Applications Through dynamic, symmetric-mutual authentication, data encryption, and the use of crypto- graphic Message Authentication Codes (MAC), the AT88SC0104CA provides a secure place for storage of sensitive information wi thin a system. With its tamper detection circuits, this informa- tion remains safe even under attack. A 2-wire serial interface running at speeds up to 1.0 MHz provides fast and efficient communications with up to 15 individually addressable devices. The AT88SC0104CA is available in i ndustry standard 8-lead packages with the same familiar pin configuration as AT24CXXX serial EEPROM devices. Note: Does not apply to TSSOP pinout. Smart Card Module VCC=C1 RST=C2 SCL/CLK=C3 NC=C4 C5=GND C6=NC C7=SDA/IO C8=NC 8-lead SOIC, PDIP NC NC NC GND VCC NC SCL SDA 8-lead TSSOP NC 1 8 VCC NC 27 N C 8-Lead TSSOP NC 3 6 SCL GND 45 SDA
5200AS–CRYPT–7/08 AT88SC0104CA Figure 4-1. Block Diagram 5. Pin Descriptions
5.1 Supply Voltage (VCC)
The VCC input is a 2.7V to 3.6V positive voltage supplied by the host.
5.2 Clock (SCL/CLK)
When using the asynchronous T = 0 protocol, t he CLK (SCL) input provides the device with a carrier frequency f. The nominal length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/f. When using the synchronous protoc ol, data clocking is done on the positive edge of the clock when writing to the device and on the negative edge of the clock when reading from the device.
5.3 Reset (RST)
The AT88SC0104CA provides an ISO 7816-3 compliant asynchronous Answer-To-Reset (ATR) sequence. Upon activation of the reset sequence, the device outputs bytes contained in the 64- bit Answer-To-Reset register. An internal pull-up on the RST input pad allows the device to oper- ate in synchronous mode without bonding RST. The AT88SC0104CA does not support an Answer-To-Reset sequence in the synchronous mode of operation.
5.4 Serial Data (SDA/IO)
The SDA/IO pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of other open-drain or open-collector devices. An external pull-up resistor should be connected between SDA/IO and VCC. The value of this resistor and the system capac- itance loading the SDA/IO bus will determine the rise time of SDA/IO. This rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher frequency operations while drawing higher average power supply current. SDA/IO infor- mation applies to both asynchronous and synchronous protocols. Random Generator Authentication, Encryption and Certification Unit EEPROM Answer to Reset Data Transfer Password Verification Reset Block Asynchronous ISO Interface Synchronous Interface Power Management VCC GND SCL/CLK SDA/IO RST
5200AS–CRYPT–7/08 AT88SC0104CA 6. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the oper- ational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Absolute Maximum Ratings Voltage on Any Pin Table 6-1. DC Characteristics Applicable over recommended operating range from VCC = +2.7 to 3.6V, TAC = -40⋅C to +85⋅C(unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Units VCC Supply Voltage 2.7 3.6 V ICC Supply Current Async READ at 3.57MHz 5 mA ICC Supply Current Async WRITE at 3.57MHz 5 mA ICC Supply Current Synch READ at 1MHz 5 mA ICC Supply Current Synch WRITE at 1MHz 5 mA ISB Standby Current VIN = VCC or GND 100 uA VIL SDA/IO Input Low Voltage 0 VCC x 0.2 V VIL CLK Input Low Voltage 0 VCC x 0.2 V VIL RST Input Low Voltage 0 VCC x 0.2 V VIH SDA/IO Input High Voltage VCC x 0.7 VCC V VIH SCL/CLK Input High Voltage VCC x 0.7 VCC V VIH RST Input High Voltage VCC x 0.7 VCC V IIL SDA/IO Input Low Current 0 < VIL < VCC x 0.15 15 uA IIL SCL/CLK Input Low Current 0 < VIL < VCC x 0.15 15 uA IIL RST Input Low Current 0 < VIL < VCC x 0.15 50 uA IIH SDA/IO Input High Current VCC x 0.7 < VIH < VCC 20 uA IIH SCL/CLK Input High Current VCC x 0.7 < VIH < VCC 100 uA IIH RST Input High Current VCC x 0.7 < VIH < VCC 150 uA VOH SDA/IO Output High Voltage 20K ohm external pull-up VCC x 0.7 VCC V VOL SDA/IO Output Low Voltage IOL = 1mA 0 VCC x 0.15 V IOH SDA/IO Output High Current VOH 20 uA IOL SDA/IO Output Low Current VOL 10 mA
5200AS–CRYPT–7/08 AT88SC0104CA 7. Device Operations for Synchronous Protocols
7.1 Clock and Data Transitions
The SDA pin is normally pulled high with an exte rnal device. Data on the SDA pin may change only during SCL low time periods (see Figure 7-3 on page 6 ). Data changes during SCL high periods will indicate a start or stop condition as defined below.
7.1.1 Start Condition
A high-to-low transition of SDA with SCL high defines a START condition which must precede all commands (see Figure 7-4 on page 7).
7.1.2 Stop Condition
A low-to-high transition of SDA with SCL high defines a STOP condition. After a read sequence, the STOP condition will place the EE PROM in a standby power mode (see Figure 7-4 on page 7).
7.1.3 ACKNOWLEDGE
All addresses and data words ar e serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens dur- ing the ninth clock cycle (see Figure 7-5 on page 7). Table 6-2. AC Characteristics Applicable over recommended operating range from VCC = +2.7 to 3.6V, TAC = -40⋅C to +85⋅C, CL = 30pF (unless otherwise noted) Parameter Min Max Units fCLK Async Clock Frequency 1 4 MHz fCLK Synch Clock Frequency 0 1 MHz Clock Duty cycle 40 60 % tR “Rise Time - SDA/IO, RST” 1 uS tF “Fall Time - SDA/IO, RST” 1 uS tR Rise Time - SCL/CLK 9% x period uS tF Fall Time - SCL/CLK 9% x period uS tAA Clock Low to Data Out Valid 250 nS tHD.STA Start Hold Time 200 nS tSU.STA Start Set-up Time 200 nS tHD.DAT Data In Hold Time 10 nS tSU.DAT Data In Set-up Time 100 nS tSU.STO Stop Set-up Time 200 nS tDH Data Out Hold Time 20 nS tWR Write Cycle Time 5m S
5200AS–CRYPT–7/08 AT88SC0104CA
7.2 Memory Reset
After an interruption in communication due protocol errors, power loss or any reason, perform "Acknowledge Polling" to properly recover from the condition. Acknowledge polling consists of sending a start condition followed by a valid CryptoMemory command byte and determining if the device responded with an ACKNOWLEDGE. Figure 7-1. Bus Time for 2-Wire Serial Communications. SCL: Serial Clock, SDA: Serial Data I/O Figure 7-2. Write Cycle Timing. SCL: Serial Clock, SDA: Serial Data I/O Note: The Write Cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 7-3. Data Validity tWR (1) STOP CONDITION START CONDITION WORDn ACK8th BIT SCL SDA DATA CHANGE ALLOWED
5200AS–CRYPT–7/08 AT88SC0104CA 8. Device Architecture
8.1 User Zones
The EEPROM user memory is divided into 4 zones of 256 bi ts each. Multiple zones allow for storage of different types of data or files in different zones. Access to user zones is permitted only after meeting proper security requirements. These security requirements are user definable in the configuration memory during device personalization. If the same security requirements are selected for multiple zones, then these zones may effectively be accessed as one larger zone. Figure 8-1. User Zones User 0 $00 - 32 Bytes $18 User 1 $00 - 32 Bytes $18 User 2 $00 - 32 Bytes $18 User 3 $00 - 32 Bytes $18
5200AS–CRYPT–7/08 AT88SC0104CA 9. Control Logic Access to the user zones occur only through the c ontrol logic built into the device. This logic is configurable through access registers, key registers and keys programmed into the configuration memory during device personalization. Also impl emented in the control logic is a cryptographic engine for performing the various higher-level security functions of the device. 10. Configuration Memory The configuration memory consists of 2048 bits of EEPROM memory used for storage of pass- words, keys, codes, and also used for definition of security access rights for the user zones. Access rights to the configurat ion memory are defined in the control logic and are not alterable by the user after completion of personalization. Figure 10-1. Configuration Memory $00 Answer To Reset Identification$08 Fab Code MTZ Card Manufacturer Code $10 Lot History Code Read Only $18 DCR Identification Number Nc Access Control $20 A R 0P R 0A R 1P R 1A R 2P R 2A R 3P R 3 $28 Reserved$30 $38 $40 Issuer Code$48 $50 For Authentication and Encryption use Cryptography $58 $60 $68 $70 $78 $80 $88 $90 For Authentication and Encryption use Secret$98 $A0 $A8 $B0 PAC Write 0 PAC Read 0 Password $B8 PAC Write 1 PAC Read 1 $C0 PAC Write 2 PAC Read 2 $C8 PAC Write 3 PAC Read 3 $D0 PAC Write 4 PAC Read 4 $D8 PAC Write 5 PAC Read 5 $E0 PAC Write 6 PAC Read 6 $E8 PAC Write 7 PAC Read 7 $F0 Reserved Forbidden$F8
5200AS–CRYPT–7/08 AT88SC0104CA
10.1 Security Fuses
There are three fuses on the device that must be blown during the device personalization pro- cess. Each fuse locks certain portions of the configuration zone as OTP (One-Time Programmable) memory. Fuses are designed for the module manufacturer, card manufacturer and card issuer and should be blown in sequenc e, although all programming of the device and blowing of the fuses may be performed at one final step. 11. Communication Security Modes Communications between the device and host operate in three basic modes. Standard mode is the default mode for the device after power-up. Authentication mode is activated by a successful authentication sequence. Encryption mode is activated by a successful encryption activation fol- lowing a successful authentication. Note: 1. Configuration data include viewable areas of the Configuration Zone except the passwords: MDC: Modification Detection Code. MAC: Message Authentication Code. 12. Security Options
12.1 Anti-Tearing
In the event of a power loss during a write cycle, the integrity of the device’s stored data is recov- erable. This function is optional: the host may choose to activate the anti-tearing function, depending on application requirements. When anti-tearing is active, write commands take longer to execute, since more write cycles are required to complete them, and data is limited to a maxi- mum of eight bytes for each write request. Data is written first into a buffer zone in EEPROM instead of the intended destination address, but with the same access conditions. The data is then written in the required location. If this sec- ond write cycle is interrupted due to a power lo ss, the device will automatically recover the data from the system buffer zone at the next power-up. Non-volatile buffering of the data is done automatically by the device. During power-up in applications using Anti-Tearing, the host is required to perform ACK polling in the event that the device needs to carry out the data recovery process. Table 11-1. Communication Security Modes (1) Mode Configuration Data User Data Passwords Data Integrity Check Standard Clear Clear Clear MDC (1) Authentication Clear Clear Encrypted MAC (1) Encryption Clear Encrypted Encrypted MAC (1)
5200AS–CRYPT–7/08 AT88SC0104CA
12.2 Write Lock
If a user zone is configured in the write lock mode, the lowest address byte of an 8-byte page constitutes a write access byte for the bytes of that page. For example, the write lock byte at $080 controls the bytes from $081 to $087. Figure 12-1. Write Lock Example The Write-Lock byte itself may be locked by writing it s least significant (r ightmost) bit to “0”. Moreover, when write lock mode is activated, the write lock byte can only be programmed – that is, bits written to “0” cannot return to “1”. In the write lock configuration, write operations are limited to writing only one byte at a time. Attempts to write more than one byte will result in writing of just the first byte into the device.
12.3 Password Verification
Passwords may be used to protect READ and/or WRITE access of any user zone. When a valid password is presented, it is memorized and active until power is turned off, unless a new pass- word is presented or RST becomes active. There are eight password sets that may be used to protect any user zone. Only one password is active at a time. Presenting the correct WRITE password also grants READ access privileges.
12.4 Authentication Protocol
The access to a user zone may be protected by an authentication protocol. Any one of four keys may be selected to use with a user zone. Authentication success is memorized and active as long as the chip is powered, unless a new authentication is initialized or RST becomes active. If the new authentication request is not vali- dated, the card loses its previous authentication which must be presented again to gain access. Only the latest request is memorized. $080 11011001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx locked locked locked
5200AS–CRYPT–7/08 AT88SC0104CA Figure 12-2. Password and Authentication Operations Note: Authentication and password verification may be attempted at any time and in any order. Exceeding corresponding authentica- tion or password attempts trial limit renders subsequent authentication or password verification attempts futile.
12.5 Cryptographic Messag e Authentication Codes
AT88SC0104CA implements a data validity che ck function in the standard, authentication or encryption modes of operation. In the standard mode, data validity check is done through a Modification Detection Code (MDC), in which the host may read an MDC from the device in order to verify that the data sent was received correctly. In authentication and encryption modes, the data validity check becomes more powerful since it provides a bidirectional data inte grity check and data or igin authentication capability in the form of a Message Authentication Codes (MAC). Only the host/device that carried out a valid authen- tication is capable of computing a valid MAC. While operating in the authentication or encryption modes, the use of MAC is required. For an ingoing command, if the device calculates a MAC dif- ferent from the MAC transmitted by the host, not only is the command abandoned but the security privilege is revoked. A new authenticat ion and/or encryption activation will be required to reactivate the MAC. CSVERIFY CS Write DATA VERIFY RPW DATA Checksum (CS) VERIFY C S
5200AS–CRYPT–7/08 AT88SC0104CA
12.6 Encryption
The data exchanged between the device and the host during read, write and verify password commands may be encrypted to ensure data confidentiality. The issuer may choose to require encryption for a user zone by settings made in the configura- tion memory. Any one of four keys may be selected for use with a user zone. In this case, activation of the encryption mode is required in order to read/write data in the zone and only encrypted data will be transmitted. Even if not required, the host may still elect to activate encryption provided the proper keys are known.
12.7 Supervisor Mode
Enabling this feature allows the holder of one s pecific password to gain full access to all eight password sets, including the ability to change passwords.
12.8 Modify Forbidden
No write access is allowed in a user zone protected with this feature at any time. The user zone must be written during device personalization prior to blowing the security fuses.
12.9 Program Only
For a user zones protected by this feature, data can only be programmed (bits change from a “1” to a “0”), but not erased (bits change from a “0” to a “1”). 13. Protocol Selection The AT88SC0104CA supports two different communication protocols. Smartcard Applications: Smartcard applications use ISO 7816-B protocol in asynchronous T = 0 mode for compatibil- ity and interoperability with industry standard smartcard readers. Embedded Applications: A 2-wire serial interface provides fast and e fficient connectivity with other logic devices or microcontrollers. The power-up sequence determines establishes t he communication protocol for use within that power cycle. Protocol selection is allowed only during power-up.
13.1 Synchronous 2-Wire Serial Interface
The synchronous mode is the default mode after power up. This is due to the presence of an internal pull-up on RST. For embedded applications using CryptoMemory in standard plastic packages, this is the only available communication protocol. Power-up VCC, RST goes high also. After stable VCC, SCL(CLK) and SDA(I/O) may be driven.
5200AS–CRYPT–7/08 AT88SC0104CA Once synchronous mode has been selected, it is not possible to switch to asynchronous mode without first powering off the device. Figure 13-1. Synchronous 2-Wire Protocol Note: Five clock pulses must be sent before the first command is issued.
13.2 Asynchronous T = 0 Protocol
This power-up sequence complies to ISO 7816-3 for a cold reset in smart card applications. VCC goes high; RST, I/O (SDA) and CLK (SCL) are low. Set I/O (SDA) in receive mode. Provide a clock signal to CLK (SCL). RST goes high after 400 clock cycles. The device will respond with a 64-bit ATR code, including historical bytes to indicate the memory density within the CryptoMemory family. Once asynchronous mode has been selected, it is not possible to switch to synchronous mode without first powering off the device. Figure 13-2. Asynchronous T = 0 Protocol (Gemplus Patent) 14. Initial Device Programming Enabling the security features of CryptoMemory requires prior personalization. Personalization entails setting up of desired access rights by z ones, passwords and key values, programming these values into the configuration memory with verification using simple WRITE and READ commands, and then blowing fuses to lock this information in place. Gaining access to the configuration memory requ ires successful presentation of a secure (or transport) code. The initial signature of the secure (transport) code for the AT88SC0104CA Vcc I/O-SDA RST CLK-SCL 1 2 3 45 Vcc I/O-SDA RST CLK-SCL ATR
5200AS–CRYPT–7/08 AT88SC0104CA device is $DD 42 97. This is the same as the WRITE 7 password. The user may elect to change the signature of the secure code anytime after successful presentation. After writing and verifying data in the configurat ion memory, the security fuses MUST be blown to lock this information in the device. For additional information on personalizing CryptoMemory, please see the application notes Programming CryptoMemory for Embedded Applications and Initializing CryptoMemory for Smart Card Applications from the product page at www.atmel.com/products/securemem. 15. Ordering Information Note: 1. Formal drawings may be obtained from an Atmel sales office. Ordering Code Package Voltage Range Temperature Range AT88SC0104CA-MJ AT88SC0104CA-MP M2 – J Module M2 – P Module 2.7V–3.6V Commercia l (0°C to 70°C) AT88SC0104CA-PU AT88SC0104CA-SU AT88SC0104CA-TU 8P3 8S1 8A2 2.7V–3.6V Lead-free/Halogen-free/Industrial (−40°C to 85°C) AT88SC0104CA-WI 7 mil wafer 2.7V–3.6V Industrial ( −40°C to 85°C) Package Type(1) Description M2 – J Module M2 ISO 7816 Smart Card Module M2 – P Module M2 ISO 7816 Smart Card Module with Atmel ® Logo 8P3 8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8A2 8-lead, 4.4mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
5200AS–CRYPT–7/08 AT88SC0104CA 16. Packaging Information. Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Square - 8.8 x 8.8 [mm] Thickness: 0.58 [mm] Pitch: 14.25 mm Ordering Code: MP Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Round - 8.5 [mm] Thickness: 0.58 [mm] Pitch: 14.25 mm Æ Ordering Code: MJ *Note: The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions of the module after excise or punching from the carrier tape are generally 0.4 mm greater in both directions
5200AS–CRYPT–7/08 AT88SC0104CA 17. Ordering Code: SU 17.1 8-lead SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 3/17/05 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1. 35 – 1.75 b 0. 31 – 0.51 C 0.17 – 0.25 D 4. 80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 B SC L 0.40 – 1.27 θ 0° – 8° ØØ EE NN TOP VIEWTOP VIEW CC E1E1 END VIEW AA bb LL A1A1 ee DD SIDE VIEWSIDE VIEW
5200AS–CRYPT–7/08 AT88SC0104CA 18. Ordering Code: PU 18.1 8-lead PDIP
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) 01/09/02 8P3 B Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE D E e Lb2 b A2 A N eA c
4 PLCS
A 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3 D1 0.005 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2 Top View Side View End View
5200AS–CRYPT–7/08 AT88SC0104CA 18.2 8-lead TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e
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