AT87F52 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Compatible with MCS-51™ Products
- 8K Bytes of User Programmable QuickFlash™ Memory
- Fully Static Operation: 0 Hz to 24 MHz
- Three-Level Program Memory Lock
- 256 x 8-Bit Internal RAM
- 32 Programmable I/O Lines
- Three 16-Bit Timer/Counters
- Eight Interrupt Sources
- Programmable Serial Channel
- Low Power Idle and Power Down Modes
Description
The AT87F52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of QuickFlash programmable read only memory. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pinout. The on-chip Quick- Flash allows the program memory to be user programmed by a conventional nonvola- tile memory programmer. By combining a versatile 8-bit CPU with QuickFlash on a monolithic chip, the Atmel AT87F52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. Rev. 1011A–02/98 8-Bit Microcontroller with 8K Bytes QuickFlash™ AT87F52 PDIP (T2) P1.0 V CC (T2 EX) P1.1 P0.0 (AD0) P1.2 (INT0) P3.2 ALE/PROG (RD) P3.7 P2.3 (A11) (TXD) P3.1 EA/VPP (WR) P3.6 P2.4 (A12) (RXD) P3.0 P0.7 (AD7) (T1) P3.5 P2.6 (A14) RST P0.6 (AD6) P0.5 (AD5) P0.4 (AD4) P0.3 (AD3) P0.2 (AD2)P1.3 P0.1 (AD1) (INT1) P3.3 PSEN XTAL2 P2.2 (A10) (T0) P3.4 P2.7 (A15) XTAL1 P2.1 (A9) GND P2.0 (A8) P2.5 (A13) P1.4 P1.5 P1.6 P1.7 Pin Configurations TQFP INDEX CORNER P1.0 (T2)VCCP1.1 (T2 EX)P1.2P1.3 NC 4243 4041 18 19 20 2122 NC 12 13 14 15 16 17 39 38 37 36 35 NC PSEN XTAL1 GND XTAL2 GND P0.0 (AD0) ALE/PROG (RD) P3.7 EA/VPP (WR) P3.6 (RXD) P3.0 P0.7 (AD7) P2.6 (A14) P0.6 (AD6) P0.5 (AD5) P0.4 (AD4) P0.3 (AD3)P0.2 (AD2)P0.1 (AD1) (INT0) P3.2 (TXD) P3.1 (T1) P3.5 (INT1) P3.3 (T0) P3.4 P2.7 (A15) RST P2.5 (A13) P1.4 P1.5 P1.6 P1.7 (continued)
P2.0 - P2.7 QUICK FLASH PORT 0 LATCHRAM PROGRAM ADDRESS REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DPTR RAM ADDR. REGISTER INSTRUCTION REGISTER B REGISTER INTERRUPT, SERIAL PORT, AND TIMER BLOCKS STACK POINTERACC TMP2 TMP1 ALU PSW TIMING AND CONTROL PORT 3 LATCH PORT 3 DRIVERS P3.0 - P3.7 PORT 1 LATCH PORT 1 DRIVERS P1.0 - P1.7 OSC GND VCC PSEN ALE/PROG EA / VPP RST PORT 0 DRIVERS P0.0 - P0.7
The AT87F52 provides the following standard features: 8K bytes of QuickFlash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt archi- tecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT87F52 is designed with static logic for operation down to zero frequency and sup- ports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM con- tents but freezes the oscillator, disabling all other chip func- tions until the next hardware reset. Pin Description VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. Port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external pro- gram and data memory. In this mode, P0 has internal pul- lups. Port 0 also receives the code bytes during QuickFlash pro- gramming and outputs the code bytes during program veri- fication. External pullups are required during program verifi- cation. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during QuickFlash programming and verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pul- lups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during QuickFlash programming and verifi- cation. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table. Port 3 also receives some control signals for QuickFlash programming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external mem- ory. This pin is also the program pulse input (PROG ) during QuickFlash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external tim- ing or clocking purposes. Note, however, that one ALE Port Pin Alternate Functions P1.0 T2 (external count input to Timer/Counter 2), clock-out P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control) Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe)
effect if the microcontroller is in external execution mode. each access to external data memory. gram memory locations starting at 0000H up to FFFFH. internally latched on reset. age (VPP ) during QuickFlash programming. internal clock operating circuit. Output from the inverting oscillator amplifier. Table 1. AT87F52 SFR Map and Reset Values
tion Register (SFR) space is shown in Table 1. cupied addresses may not be implemented on the chip. the new bits will always be 0. 16-bit capture mode or 16-bit auto-reload mode. the six interrupt sources in the IP register. Table 2. T2CON—Timer/Counter 2 Control Register physically separate from SFR space. addressing access SFR space. accesses the SFR at location 0A0H (which is P2).
- When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2
must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer. = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
as Timer 0 and Timer 1 in the AT87F51. in the SFR T2CON (shown in Table 2). modes are selected by bits in T2CON, as shown in Table 3. Table 3. Timer 2 Operating Modes or counter which upon overflow sets bit TF2 in T2CON.
1 X 1 Baud Rate Generator
Figure 1. Timer in Capture Mode
into its baud rate generator mode, as shown in Figure 4. and RCAP2L, which are preset by software. 2’s overflow rate according to the following equation. quency). The baud rate formula is given below. RCAP2L taken as a 16-bit unsigned integer. an extra external interrupt. Figure 5. Timer 2 in Clock-Out Mode
must be set. Bit TR2 (T2CON.2) starts and stops the timer. (RCAP2H, RCAP2L), as shown in the following equation. another since they both use RCAP2H and RCAP2L. rupts are all shown in Figure 6. disables all interrupts at once. tions, since they may be used in future AT89 products. and that bit will have to be cleared in software. same cycle in which the timer overflows. Table 5. Interrupt Enable (IE) Register Figure 6. Interrupt Sources Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. ET2 IE.5 Timer 2 interrupt enable bit. ES IE.4 Serial Port interrupt enable bit. ET1 IE.3 Timer 1 interrupt enable bit. EX1 IE.2 External interrupt 1 enable bit. ET0 IE.1 Timer 0 interrupt enable bit. EX0 IE.0 External interrupt 0 enable bit. because they may be used in future A T89 products.
The AT87F52 has three lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the addi- tional features listed in the following table. Lock Bit Protection Modes When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is pow- ered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly. Programming the QuickFlash The AT87F52 is shipped with the on-chip QuickFlash mem- ory array ready to be programmed. The programming inter- face needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party Flash or EPROM programmers. The AT87F52 code memory array is programmed byte-by- byte. Programming Algorithm: Before programming the AT87F52, the address, data, and control signals should be set up according to the QuickFlash programming mode table and Figures 9 and 10. To program the AT87F52, take the following steps: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA /VPP to 12V . 5. Pulse ALE/PROG once to program a byte in the Quick- Flash array or the lock bits. The byte-write cycle is self- timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT87F52 features Data Polling to indi- cate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the com- plement of the written data on PO.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy : The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY . P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 87H indicates 87F family (032H) = 02H indicates 87F52 Program Lock Bits LB1 LB2 LB3 Protection Type 1 U U U No program lock features.
2 P U U MOVC instructions executed
internal memory, EA is sampled and latched on reset, and further programming of the QuickFlash memory is disabled.
3 P P U Same as mode 2, but verify is
also disabled.
4 P P P Same as mode 3, but external
execution is also disabled.
Every code byte in the QuickFlash array can be pro- grammed by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. QuickFlash Programming Modes Mode RST PSEN ALE/PROG EA /VPP P2.6 P2.7 P3.6 P3.7 Write Code Data H L 12V L H H H Read Code Data H L H H L L H H Write Lock Bit - 1 H L 12V H H H H Bit - 2 H L 12V H H L L Bit - 3 H L 12V H L H L Read Signature Byte H L H H L L L L
QuickFlash Programming and Verification Waveforms tGLGH tGHSL tAVGL tSHGL tDVGL tGHAX tAVQV tGHDX tEHSH tELQV tWC BUSY READY tGHBL tEHQZ P1.0 - P1.7 P2.0 - P2.4 ALE/PROG PORT 0 LOGIC 1 LOGIC 0EA/VPP VPP P2.7 (ENABLE) P3.4 (RDY/BSY) PROGRAMMING ADDRESS VERIFICATION ADDRESS DATA IN DATA OUT (2)
Absolute Maximum Ratings* DC Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ± 20%, unless otherwise noted. Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total I OL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2V . Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin Symbol Parameter Condition Min Max Units VIL Input Low Voltage (Except EA )- 0 . 5 0 . 2 V CC -0.1 V VIL1 Input Low Voltage (EA)- 0 . 5 0 . 2 V CC -0.3 V VIH Input High Voltage (Except XTAL1, RST) 0.2 V CC +0.9 V CC +0.5 V VIH1 Input High Voltage (XT AL1, RST) 0.7 V CC VCC +0.5 V VOL Output Low Voltage(1) (Ports 1,2,3) IOL = 1.6 mA 0.45 V VOL1 Output Low Voltage(1) (Port 0, ALE, PSEN) IOL = 3.2 mA 0.45 V VOH Output High Voltage (Ports 1,2,3, ALE, PSEN) IOH = -60 µA, VCC = 5V ± 10% 2.4 V IOH = -25 µA 0.75 V CC V IOH = -10 µA0 . 9 V CC V VOH1 Output High Voltage (Port 0 in External Bus Mode) IOH = -800 µA, VCC = 5V ± 10% 2.4 V IOH = -300 µA 0.75 V CC V IOH = -80 µA0 . 9 V CC V IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA ITL Logical 1 to 0 T ransition Current (Ports 1,2,3) VIN = 2V , VCC = 5V ± 10% -650 µA ILI Input Leakage Current (Port 0, EA) 0.45 < V IN < VCC ±10 µA RRST Reset Pulldown Resistor 50 300 K Ω C IO Pin Capacitance Test Freq. = 1 MHz, T A = 25°C 10 pF ICC Power Supply Current Active Mode, 12 MHz 25 mA Idle Mode, 12 MHz 6.5 mA Power Down Mode(1) VCC = 6V 100 µA VCC = 3V 40 µA
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. External Program and Data Memory Characteristics Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max 1/tCLCL Oscillator Frequency 0 24 MHz tLHLL ALE Pulse Width 127 2t CLCL -40 ns tAVLL Address Valid to ALE Low 43 t CLCL -13 ns tLLAX Address Hold After ALE Low 48 t CLCL -20 ns tLLIV ALE Low to Valid Instruction In 233 4t CLCL -65 ns tLLPL ALE Low to PSEN Low 43 t CLCL -13 ns tPLPH PSEN Pulse Width 205 3t CLCL -20 ns tPLIV PSEN Low to Valid Instruction In 145 3t CLCL -45 ns tPXIX Input Instruction Hold After PSEN 00 n s tPXIZ Input Instruction Float After PSEN 59 t CLCL -10 ns tPXAV PSEN to Address Valid 75 t CLCL -8 ns tAVIV Address to Valid Instruction In 312 5t CLCL -55 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 400 6t CLCL -100 ns tWLWH WR Pulse Width 400 6t CLCL -100 ns tRLDV RD Low to Valid Data In 252 5t CLCL -90 ns tRHDX Data Hold After RD 00 n s tRHDZ Data Float After RD 97 2t CLCL -28 ns tLLDV ALE Low to Valid Data In 517 8t CLCL -150 ns tAVDV Address to Valid Data In 585 9t CLCL -165 ns tLLWL ALE Low to RD or WR Low 200 300 3t CLCL -50 3t CLCL +50 ns tAVWL Address to RD or WR Low 203 4t CLCL -75 ns tQVWX Data Valid to WR T ransition 23 t CLCL -20 ns tQVWH Data Valid to WR High 433 7t CLCL -120 ns tWHQX Data Hold After WR 33 t CLCL -20 ns tRLAZ RD Low to Address Float 0 0 ns tWHLH RD or WR High to ALE High 43 123 t CLCL -20 t CLCL +25 ns
External Program Memory Read Cycle External Data Memory Read Cycle tLHLL tLLIV tPLIV tLLAX tPXIZ tPLPH tPLAZ tPXAV tAVLL tLLPL tAVIV tPXIX ALE PSEN PORT 0 PORT 2 A8 - A15 A0 - A7 A0 - A7 A8 - A15 INSTR IN tLHLL tLLDV tLLWL tLLAX tWHLH tAVLL tRLRH tAVDV tAVWL tRLAZ tRHDX tRLDV tRHDZ A0 - A7 FROM RI OR DPL ALE PSEN RD PORT 0 PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A0 - A7 FROM PCL A8 - A15 FROM PCH DATA IN INSTR IN
External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Symbol Parameter Min Max Units 1/tCLCL Oscillator Frequency 0 24 MHz tCLCL Clock Period 41.6 ns tCHCX High Time 15 ns tCLCX Low Time 15 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns tLHLL tLLWL tLLAX tWHLH tAVLL tWLWH tAVWL tQVWX tQVWH tWHQX A0 - A7 FROM RI OR DPL ALE PSEN WR PORT 0 PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A0 - A7 FROM PCL A8 - A15 FROM PCH DATA OUT INSTR IN tCHCX tCHCX tCLCX tCLCL tCHCLtCLCH V - 0.5VCC 0.45V 0.2 V - 0.1VCC
0.7 VCC
Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF. Shift Register Mode Timing Waveforms Symbol Parameter 12 MHz Osc Variable Oscillator Units Min Max Min Max tXLXL Serial Port Clock Cycle Time 1.0 12t CLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10t CLCL -133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2t CLCL -117 ns tXHDX Input Data Hold After Clock Rising Edge 0 0 ns tXHDV Clock Rising Edge to Input Data Valid 700 10t CLCL -133 ns tXHDV tQVXH tXLXL tXHDX tXHQX ALE INPUT DATA CLEAR RI OUTPUT DATA WRITE TO SBUF INSTRUCTION CLOCK SET TI SET RI VALID VALID VALID VALIDVALID VALID VALID VALID Float Waveforms(1) Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V OH /VOL level occurs. V LOAD + 0.1V Timing Reference Points V LOAD - 0.1V LOAD V V OL + 0.1V V OL - 0.1V AC Testing Input/Output Waveforms(1) Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing mea- surements are made at VIH min. for a logic 1 and VIL max. for a logic 0. 0.45V TEST POINTS V - 0.5VCC 0.2 V + 0.9VCC 0.2 V - 0.1VCC
Ordering Information
(MHz) Power Supply Ordering Code Package Operation Range 12 5V ± 20% AT87F52-12AC A T87F52-12JC A T87F52-12PC 44A 44J 40P6 Commercial (0°C to 70°C) A T87F52-12AI A T87F52-12JI A T87F52-12PI 44A 44J 40P6 Industrial (-40°C to 85°C) 16 5V ± 20% AT87F52-16AC A T87F52-16JC A T87F52-16PC 44A 44J 40P6 Commercial (0°C to 70°C) A T87F52-16AI A T87F52-16JI A T87F52-16PI 44A 44J 40P6 Industrial (-40°C to 85°C) 20 5V ± 20% AT87F52-20AC A T87F52-20JC A T87F52-20PC 44A 44J 40P6 Commercial (0°C to 70°C) A T87F52-20AI A T87F52-20JI A T87F52-20QI 44A 44J 44Q Industrial (-40°C to 85°C) 24 5V ± 20% AT87F52-24AC A T87F52-24JC A T87F52-24PC 44A 44J 40P6 Commercial (0°C to 70°C) A T87F52-24AI A T87F52-24JI A T87F52-24PI 44A 44J 40P6 Industrial (-40°C to 85°C) Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
*Controlling dimension: millimeters .045(1.14) X 45° PIN NO. 1 IDENTIFY .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) REF SQ .032(.813) .026(.660) .050(1.27) TYP .656(16.7) .650(16.5) .695(17.7) .685(17.4)SQ SQ 2.07(52.6) 2.04(51.8) PIN .566(14.4) .530(13.5) .090(2.29) MAX .005(.127) MIN .065(1.65) .015(.381) .022(.559) .041(1.04)
15 REF
.690(17.5) .610(15.5) .630(16.0) .590(15.0) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) SEATING PLANE .220(5.59) MAX 1.900(48.26) REF 44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) 40P6, 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-011 AC