AT87F51RC ATMEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 25
Technical content
Features
- Compatible with MCS-51™ Products 32K Bytes of One-time Programmable QuickFlash™ Memory 4V to 6V Operating Range Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 512 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Hardware Watchdog Timer Dual Data Pointer Power-off Flag
Description
The AT87F51RC is a low-power, high-performance CMOS 8-bit microcomputer with 32K bytes of QuickFlash one-time programmable (OTP) read only memory and 512 bytes of RAM. The device is manufactured using Atmel ’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C52 instruction set and pinout. The on-chip QuickFlash allows the program memory to be Rev. 1106C–02/00 8-bit Microcontroller with 32K Bytes QuickFlash™ AT87F51RC PreliminaryPDIP (T2) P1.0 (T2EX) P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) Pin Configurations TQFP P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 P1.4 P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3)
user programmed by a conventional nonvolatile memory programmer. A total of 512 bytes of internal RAM are avail- able in the AT87F51RC. The 256-byte expanded internal RAM is accessed via MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The other 256-byte RAM segment is accessed the same way as the Atmel AT89-series and other 8052-compatible products. By com- bining a versatile 8-bit CPU with QuickFlash on a mono- lithic chip, the Atmel AT87F51RC is a powerful microcomputer which provides a highly-flexible and cost- effective solution to many embedded control applications. Block Diagram PORT 2 DRIVERS PORT 2 LATCH P2.0 - P2.7 QUICK FLASH PORT 0 LATCHRAM PROGRAM ADDRESS REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL DPTR RAM ADDR. REGISTER INSTRUCTION REGISTER B REGISTER INTERRUPT, SERIAL PORT, AND TIMER BLOCKS STACK POINTERACC TMP2 TMP1 ALU PSW TIMING AND CONTROL PORT 3 LATCH PORT 3 DRIVERS P3.0 - P3.7 PORT 1 LATCH PORT 1 DRIVERS P1.0 - P1.7 OSC GND VCC PSEN ALE/PROG EA / V PP RST PORT 0 DRIVERS P0.0 - P0.7 WATCH DOG
The AT87F51RC provides the following standard features: 32K bytes of QuickFlash, 512 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT87F51RC is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con- tents but freezes the oscillator, disabling all other chip func- tions until the next external interrupt or hardware reset. Pin Description VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance inputs. Port 0 can also be configured to be the multiplexed low- order address/data bus during accesses to external pro- gram and data memory. In this mode, P0 has internal pul- lups. Port 0 also receives the code bytes during QuickFlash pro- gramming and outputs the code bytes during program veri- fication. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during QuickFlash programming and verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pul- lups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during QuickFlash programming and verifi- cation. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pullups. Port 3 also serves the functions of various special features of the AT87F51RC, as shown in the following table. Port 3 also receives some control signals for QuickFlash programming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISTRO, the RESET HIGH out feature is enabled. ALE/PROG Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external Port Pin Alternate Functions P1.0 T2 (external count input to Timer/Counter 2), clock-out P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control) Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe)
during QuickFlash programming. effect if the microcontroller is in external execution mode. each access to external data memory. gram memory locations starting at 0000H up to FFFFH. internally latched on reset. age (VPP) during QuickFlash programming. internal clock operating circuit. Output from the inverting oscillator amplifier. Table 1. AT87F51RC SFR Map and Reset Values
tion Register (SFR) space is shown in Table 1. cupied addresses may not be implemented on the chip. the new bits will always be 0. ture mode or 16-bit auto-reload mode. the six interrupt sources in the IP register. Table 2. T2CON – Timer/Counter 2 Control Register by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer. Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered). either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Regis- ter. Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset. Table 3a. AUXR: Auxiliary Register AUXR Address = 8EH Reset Value = XXX00X00B Not Bit Addressable ––– WDIDLE DISRTO – EXTRAM DISALE Bit 7 6 5 4 3 2 1 0 – Reserved for future expansion DISALE Disable/Enable ALE DISALE Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
EXTRAM Internal External RAM (00H-FFH) access using MOVX @ Ri/DPTR EXTRAM Operating Mode
0 Internal ERAM (00H-FFH) access using MOVX @ Ri/DPTR
1 External data memory access
DISTRO Disable/Enable Reset out DISRTO
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode WDIDLE
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode
Table 3b. AUXR1: Auxiliary Register 1 AUXR1 Address = A2H Reset Value = XXXXXXX0B Not Bit Addressable Bit 7 6 5 4 3 2 1 0 – Reserved for future expansion DPS Data Pointer Register Select DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H
Program and Data Memory can be addressed. directed to external memory. FFFFH are to external memory. ter (SFR) and 256 bytes expanded RAM (ERAM).
- The Lower 128 bytes of RAM (addresses 00H to
7FH) are directly and indirectly addressable.
- The Upper 128 bytes of RAM (addresses 80H to
FFH) are indirectly addressable only.
- The Special Function Registers, SFRs, (addresses
80H to FFH) are directly addressable only.
- The 256-byte expanded RAM (ERAM, 00H-FFH) is
address 0A0H, rather than P2 (whose address is 0A0H). Figure 1. Internal and External Data Memory Address write and read timing signals. Refer to Figure 1. bits. This is to provide the external paging capability. bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the ERAM.
256 BYTES
128 BYTES
sequence to the WDTRST register (SFR location 0A6H). WDT the user must write 01EH and 0E1H to WDTRST. time required to prevent a WDT reset. just before entering power-down. IDLE, service the WDT, and reenter IDLE mode. IDLE mode and resumes the count upon exit from IDLE. Data Book, page 2-48, section titled, “Serial Interface”. way as Timer 0 and Timer 1 in the AT87F51 and AT87F52. in the SFR T2CON (shown in Table 2). modes are selected by bits in T2CON, as shown in Table 4. Table 4. Timer 2 Operating Modes
1 X 1 Baud Rate Generator
Figure 3. Timer 2 Auto Reload Mode (DCEN = 0) Table 5. T2MOD— Timer 2 Mode Control Register T2OE Timer 2 Output Enable bit. DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.
and RCAP2L, which are preset by software. 2’s overflow rate according to the following equation. quency). The baud rate formula is given below. RCAP2L taken as a 16-bit unsigned integer. an extra external interrupt. Figure 6. Timer 2 in Clock-Out Mode
2 TL2
MHz at a 16 MHz operating frequency. must be set. Bit TR2 (T2CON.2) starts and stops the timer. (RCAP2H, RCAP2L), as shown in the following equation. another since they both use RCAP2H and RCAP2L. interrupts are all shown in Figure 7. disables all interrupts at once. positions, since they may be used in future AT89 products. and that bit will have to be cleared in software. same cycle in which the timer overflows. Figure 7. Interrupt Sources Table 6. Interrupt Enable (IE) Register Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt. ET2 IE.5 Timer 2 interrupt enable bit. ES IE.4 Serial Port interrupt enable bit. ET1 IE.3 Timer 1 interrupt enable bit. EX1 IE.2 External interrupt 1 enable bit. ET0 IE.1 Timer 0 interrupt enable bit. EX0 IE.0 External interrupt 0 enable bit. because they may be used in future AT89 products.
tional features listed in the following table. at that pin in order for the device to function properly.
- Input the desired memory location on the address
- Input the appropriate data byte on the data lines.
- Activate the correct combination of control signals.
- Pulse ALE/PROG once to program a byte in the
of the object file is reached. after a write cycle has been initiated. achieved by observing that their features are enabled. Table 8. Lock Bit Protection Modes 1 U U U No program lock features.
initiated, will automatically time itself to completion. programming vendor for the appropriate software revision. Notes: 1. Each Prog/pulse is 200 ns for Write Code Data and 100 ms for Write Lock Bits.
- RDY/BSY signal is output on P3.0 during programming.
Figure 10. Programming the QuickFlash Memory Figure 11. Verifying the QuickFlash Memory *Programming address line A14 (P3.4) is not the same as the external memory address line A14 (P2.6). Table 9. QuickFlash Programming Modes
QuickFlash Programming and Verification Waveforms QuickFlash Programming and Verification Characteristics TA = 0°C to 70°C, VCC = 5.0 ± 10% Symbol Parameter Min Max Units VPP Programming Supply Voltage 11.5 12.0 V IPP Programming Supply Current 10 mA ICC VCC Supply Current 30 mA 1/tCLCL Oscillator Frequency 3 24 MHz tAVGL Address Setup to PROG Low 48t CLCL tGHAX Address Hold after PROG 48tCLCL tDVGL Data Setup to PROG Low 48t CLCL tGHDX Data Hold after PROG 48tCLCL tEHSH P2.7 (ENABLE) High to VPP 48tCLCL tSHGL VPP Setup to PROG Low 10 µs tGHSL VPP Hold after PROG 10 µs tGLGH PROG Width 0.2 1 µs tAVQV Address to Data Valid 48t CLCL tELQV ENABLE Low to Data Valid 48t CLCL tEHQZ Data Float after ENABLE 04 8 t CLCL tGHBL PROG High to BUSY Low 1.0 µs tWC Byte Write Cycle Time 80 µs tGLGH tGHSL tAVGL tSHGL tDVGL tGHAX tAVQV tGHDX tEHSH tELQV tWC BUSY READY tGHBL tEHQZ P1.0 - P1.7 P2.0 - P2.5 P3.4 ALE/PROG PORT 0 LOGIC 1 LOGIC 0EA/VPP VPP P2.7 (ENABLE) P3.0 (RDY/BSY) PROGRAMMING ADDRESS VERIFICA TION ADDRESS DATA IN DATA OUT
Notes: 1. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum V CC for Power-down is 2V. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin DC Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ± 20%, unless otherwise noted. Symbol Parameter Condition Min Max Units VIL Input Low-voltage (Except EA )- 0 . 5 0 . 2 V CC-0.1 V VIL1 Input Low-voltage (EA)- 0 . 5 0 . 2 V CC-0.3 V VIH Input High-voltage (Except XTAL1, RST) 0.2 V CC+0.9 V CC+0.5 V VIH1 Input High-voltage (XTAL1, RST) 0.7 V CC VCC+0.5 V VOL Output Low-voltage(1) (Ports 1,2,3) I OL = 1.6 mA 0.45 V VOL1 Output Low-voltage(1) (Port 0, ALE, PSEN) IOL = 3.2 mA 0.45 V VOH Output High-voltage (Ports 1,2,3, ALE, PSEN) IOH = -60 µA, VCC = 5V ± 10% 2.4 V IOH = -25 µA 0.75 V CC V IOH = -10 µA0 . 9 V CC V VOH1 Output High-voltage (Port 0 in External Bus Mode) IOH = -800 µA, VCC = 5V ± 10% 2.4 V IOH = -300 µA 0.75 V CC V IOH = -80 µA0 . 9 V CC V IIL Logical 0 Input Current (Ports 1,2,3) V IN = 0.45V -50 µA ITL Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA ILI Input Leakage Current (Port 0, EA ) 0.45 < V IN < VCC ±10 µA RRST Reset Pull-down Resistor 50 300 K Ω CIO Pin Capacitance Test Freq. = 1 MHz, T A = 25°C1 0 p F ICC Power Supply Current Active Mode, 12 MHz 25 mA Idle Mode, 12 MHz 6.5 mA Power-down Mode(1) VCC = 6V 100 µA VCC = 3V 40 µA
Under operating conditions, load capacitance for Port 0, ALE/PROG , and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. External Program and Data Memory Characteristics Symbol Parameter
12 MHz Oscillator Variable Oscillator
1/tCLCL Oscillator Frequency 0 24 MHz tLHLL ALE Pulse Width 127 2t CLCL-40 ns tAVLL Address Valid to ALE Low 43 t CLCL-13 ns tLLAX Address Hold after ALE Low 48 t CLCL-20 ns tLLIV ALE Low to Valid Instruction In 233 4t CLCL-65 ns tLLPL ALE Low to PSEN Low 43 t CLCL-13 ns tPLPH PSEN Pulse Width 205 3t CLCL-20 ns tPLIV PSEN Low to Valid Instruction In 145 3t CLCL-45 ns tPXIX Input Instruction Hold after PSEN 00 n s tPXIZ Input Instruction Float after PSEN 59 t CLCL-10 ns tPXAV PSEN to Address Valid 75 t CLCL-8 ns tAVIV Address to Valid Instruction In 312 5t CLCL-55 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 400 6t CLCL-100 ns tWLWH WR Pulse Width 400 6t CLCL-100 ns tRLDV RD Low to Valid Data In 252 5t CLCL-90 ns tRHDX Data Hold after RD 00 n s tRHDZ Data Float after RD 97 2t CLCL-28 ns tLLDV ALE Low to Valid Data In 517 8t CLCL-150 ns tAVDV Address to Valid Data In 585 9t CLCL-165 ns tLLWL ALE Low to RD or WR Low 200 300 3t CLCL-50 3t CLCL+50 ns tAVWL Address to RD or WR Low 203 4t CLCL-75 ns tQVWX Data Valid to WR T ransition 23 t CLCL-20 ns tQVWH Data Valid to WR High 433 7t CLCL-120 ns tWHQX Data Hold after WR 33 t CLCL-20 ns tRLAZ RD Low to Address Float 0 0 ns tWHLH RD or WR High to ALE High 43 123 t CLCL-20 t CLCL+25 ns
External Program Memory Read Cycle External Data Memory Read Cycle tLHLL tLLIV tPLIV tLLAX tPXIZ tPLPH tPLAZ tPXAV tAVLL tLLPL tAVIV tPXIX ALE PSEN PORT 0 PORT 2 A8 - A15 A0 - A7 A0 - A7 A8 - A15 INSTR IN tLHLL tLLDV tLLWL tLLAX tWHLH tAVLL tRLRH tAVDV tAVWL tRLAZ tRHDX tRLDV tRHDZ A0 - A7 FROM RI OR DPL ALE PSEN RD PORT 0 PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A0 - A7 FROM PCL A8 - A15 FROM PCH DATA IN INSTR IN
External Data Memory Write Cycle External Clock Drive Waveforms tLHLL tLLWL tLLAX tWHLH tAVLL tWLWH tAVWL tQVWX tQVWH tWHQX A0 - A7 FROM RI OR DPL ALE PSEN WR PORT 0 PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A0 - A7 FROM PCL A8 - A15 FROM PCH DATA OUT INSTR IN tCHCX tCHCX tCLCX tCLCL tCHCLtCLCH V - 0.5VCC 0.45V 0.2 V - 0.1VCC
0.7 VCC
Symbol Parameter Min Max Units 1/tCLCL Oscillator Frequency 0 24 MHz tCLCL Clock Period 41.6 ns tCHCX High Time 15 ns tCLCX Low Time 15 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns
Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Note: 1. AC Inputs during testing are driven at V CC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing mea- surements are made at VIH min. for a logic 1 and VIL max. for a logic 0. Float Waveforms(1) Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V OH/VOL level occurs. Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF. Symbol Parameter
12 MHz Osc Variable Oscillator
tXLXL Serial Port Clock Cycle Time 1.0 12t CLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10t CLCL-133 ns tXHQX Output Data Hold after Clock Rising Edge 50 2t CLCL-117 ns tXHDX Input Data Hold after Clock Rising Edge 0 0 ns tXHDV Clock Rising Edge to Input Data Valid 700 10t CLCL-133 ns tXHDV tQVXH tXLXL tXHDX tXHQX ALE INPUT DATA CLEAR RI OUTPUT DATA WRITE TO SBUF INSTRUCTION CLOCK SET TI SET RI VALID VALID VALID VALIDVALID VALID VALID VALID 0.45V TEST POINTS V - 0.5VCC 0.2 V + 0.9VCC 0.2 V - 0.1VCC VLOAD+ 0.1V Timing Reference Points V LOAD- 0.1V LOAD V VOL+ 0.1V VOL - 0.1V
Ordering Information
(MHz) Power Supply Ordering Code Package Operation Range 12 5V ± 20% AT87F51RC-12AC AT87F51RC-12JC AT87F51RC-12PC 44A 44J 40P6 Commercial (0°C to 70°C) AT87F51RC-12AI AT87F51RC-12JI AT87F51RC-12PI 44A 44J 40P6 Industrial (-40°C to 85°C) 16 5V ± 20% AT87F51RC-16AC AT87F51RC-16JC AT87F51RC-16PC 44A 44J 40P6 Commercial (0°C to 70°C) AT87F51RC-16AI AT87F51RC-16JI AT87F51RC-16PI 44A 44J 40P6 Industrial (-40°C to 85°C) 20 5V ± 20% AT87F51RC-20AC AT87F51RC-20JC AT87F51RC-20PC 44A 44J 40P6 Commercial (0°C to 70°C) AT87F51RC-20AI AT87F51RC-20JI AT87F51RC-20PI 44A 44J 44Q Industrial (-40°C to 85°C) 24 5V ± 20% AT87F51RC-24AC AT87F51RC-24JC AT87F51RC-24PC 44A 44J 40P6 Commercial (0°C to 70°C) AT87F51RC-24AI AT87F51RC-24JI AT87F51RC-24PI 44A 44J 40P6 Industrial (-40°C to 85°C)Package Type 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
*Controlling dimension: millimeters 1.20(0.047) MAX 10.10(0.394) 9.90(0.386) SQ 12.21(0.478) 11.75(0.458) SQ 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002) 0.20(.008) 0.09(.003) 0.80(0.031) BSC PIN 1 ID 0.45(0.018) 0.30(0.012) .045(1.14) X 45° PIN NO. 1 IDENTIFY .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) REF SQ .032(.813) .026(.660) .050(1.27) TYP .656(16.7) .650(16.5) .695(17.7) .685(17.4)SQ SQ 2.07(52.6) 2.04(51.8) PIN .566(14.4) .530(13.5) .090(2.29) MAX .005(.127) MIN .065(1.65) .015(.381) .022(.559) .041(1.04)
15 REF
.690(17.5) .610(15.5) .630(16.0) .590(15.0) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) SEATING PLANE .220(5.59) MAX 1.900(48.26) REF 44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 44J, 44-lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) 40P6, 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-011 AC
© Atmel Corporation 1998. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company ’s standard war- ranty which is detailed in Atmel ’s Terms and Conditions located on the Company ’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any tim e without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectu al prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel ’s products are not authorized for use as critical components in life support devices or systems. Atmel Headquarters Atmel Operations Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686677 FAX (44) 1276-686697 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza
77 Mody Road
Kowloon, Hong Kong TEL (852) 27219778 FAX (852) 27221369 Japan Atmel Japan K.K. Tonetsu Shinkawa Bldg., 9F 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4 42 53 60 00 FAX (33) 4 42 53 60 01 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 e-mail literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 Printed on recycled paper. 1106C–02/00/xM Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others.