TS80C32X2_08 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- 80C52 Compatible – 8051 Pin and Instruction Compatible – Four 8-bit I/O Ports – Three 16-bit Timer/Counters – 256 Bytes Scratchpad RAM
- High-speed Architecture
- 40 MHz at 5V, 30 MHz at 3V
- X2 Speed Improvement Capability (6 Clocks/Machine Cycle) – 30 MHz at 5V, 20 MHz at 3V (Equivalent to 60 MHz a t 5V, 40 MHz at 3V)
- Dual Data Pointer
- On-chip ROM/EPROM (8Kbytes)
- Programmable Clock Out and Up/Down Timer/Counter 2
- Asynchronous Port Reset
- Interrupt Structure with – 6 Interrupt Sources – 4 Level Priority Interrupt System
- Full Duplex Enhanced UART – Framing Error Detection – Automatic Address Recognition
- Low EMI (Inhibit ALE)
- Power Control Modes – Idle Mode – Power-down Mode – Power-off Flag
- Once Mode (On-chip Emulation)
- Power Supply: 4.5 - 5.5V, 2.7 - 5.5V
- Temperature Ranges: Commercial (0 to 70 oC) and Industrial (-40 to 85 oC)
- Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 (13.9 footprint)
Description
TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C52X2 retains all features of the 80C51 wit h extended ROM/EPROM capacity (8 Kbytes), 256 bytes of internal RAM, a 6 -source, 4-level interrupt system, an on-chip oscilator and three timer/counters. In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUAR T) and an X2 speed improve- ment mechanism. The fully static design of the TS80C52X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C52X2 has 2 software-selectable modes of re duced activity for further reduction in power consumption. In the idle mode th e CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. 8-bit Microcontroller
8 Kbytes
ROM/OTP , ROMless TS80C32X2 TS87C52X2 TS80C52X2 AT80C32X2 AT80C52X2 AT87C52X2
Table 1. Memory Size
- Alternate function of Port 3
4184I–8051–02/08 SFR Mapping The Special Function Registers (SFRs) of the TS80C5 2X2 fall into the following categories:
- C51 core registers: ACC, B, DPH, DPL, PSW, SP , AUX R1
- I/O port registers: P0, P1, P2, P3
- Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2 , TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
- Serial I/O port registers: SADDR, SADEN, SBUF, SCO N
- Power and clock control registers: PCON
- Interrupt system registers: IE, IP , IPH
- Others: AUXR, CKCON
Table 2. All SFRs with their address and their reset value
4184I–8051–02/08 Pin Configuration 5 4 3 2 1 6 44 43 42 41 40 P1.4 P1.0/T2 P1.1/T2EX P1.3 P1.2 VSS1/NIC* VCC P0.0/AD0 P0.2/AD2 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA/VPP NIC* P2.7/A15 P2.5/A13 P2.6/A14 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 43 42 41 40 39 44 38 37 36 35 34 P1.4 P1.0/T2 P1.1/T2EX P1.3 P1.2 VSS1/NIC* VCC P0.0/AD0 P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA/VPP NIC* P2.7/A15 P2.5/A13 P2.6/A14 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P0.3/AD3 NIC* NIC* *NIC: No Internal Connection PLCC/CQPJ 44 PQFP44 18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22 VQFP44 P1.7 RST P3.0/RxD P3.1/TxD P1.3 P1.5 P3.2/INT0 P3.3/INT1 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 P0.4 / A4 P0.6 / A6 P0.5 / A5 P0.7 / A7 ALE/PROG PSEN EA/VPP P2.7 / A15 P2.5 / A13 P2.6 / A14 P1.0 / T2 P1.1 / T2EX VCC P0.0 / A0 P0.1 / A1 P0.2 / A2 P0.3 / A3 PDIL/ CDIL40 P1.6 P1.4 P1.2 P3.4/T0
4184I–8051–02/08 Mnemonic Pin Number Type Name and Function DIL LCC VQFP 1.4 VSS 20 22 16 I Ground: 0V reference Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down operation P0.0-P0.7 39- 43- 36 37-30 I/O Port 0 : Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs.Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current co nsumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when e mitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes . 1-3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O por t with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as in puts. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 al so receives the low-order address byte during memory programmin g and verification. Alternate functions for Port 1 include: 1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control P2.0-P2.7 21- 24- 31 18-25 I/O Port 2 : Port 2 is an 8-bit bidirectional I/O port with in ternal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as in puts. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high- order address byte during fetches from external pro gram memory and during accesses to external data memory that use 16-bit addresses (MOVX atDPTR).In this applicat ion, it uses strong internal pull-ups emitting 1s. During a ccesses to external data memory that use 8-bit addresses (MOVX atRi), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.4 P3.0-P3.7 10- 11, 13- 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port w ith internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as in puts. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 al so serves the special features of the 80C51 family, as listed below. 10 11 5 I RXD (P3.0): Serial input port 11 13 7 O TXD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 0
4184I–8051–02/08 13 15 9 I INT1 (P3.3): External interrupt 1 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe Reset 9 10 4 I Reset: A high on this pin for two machine cycles while th e oscillator is running, resets the device. An intern al diffused resistor to V SS permits a power-on reset using only an external capacitor to V CC. ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an acce ss to external memory. In normal operation, ALE is emitte d at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (P ROG ) during EPROM programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be in active during internal fetches. PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When executing code from the external progr am memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /V PP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device t o fetch code from external program memory locations 0000H a nd 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is h eld high, the device executes from internal program mem ory unless the program counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must be held low for ROMless devices. This pin also receives the 12.75V programming supply voltage (V PP ) during EPROM programming. If security level 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and inp ut to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier Mnemonic Pin Number Type Name and Function DIL LCC VQFP 1.4
- The X2 option
- The Dual Data Pointer
- The 4 level interrupt priority system
- The power-off flag
- The ONCE mode
- The ALE disabling
- Some enhanced features are also located in the UAR T and the Timer 2 X2 Feature The TS80C52X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages:
- Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power
- Save power consumption while keeping same CPU powe r (oscillator power saving)
- Save power consumption by dividing dynamically ope rating frequency by 2 in operating and idle modes
- Increase CPU power by 2 while keeping same crystal frequency In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core ( phase generator). This divider may be disabled by software. Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cycli c ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. X2 bit is validated on XTAL1 ÷ 2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock Generation Diagram state machine: 6 clock cycles.
Figure 2. Mode Switching Waveforms (STD mode). Setting this bit activates the X2 feature (X2 mode). rate will have 9600 baud rate. Table 3. CKCON Register The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. Set to select 6 clock periods per machine cycle (X2 mode, F OSC =F XTAL ).
Figure 3. Use of Dual Pointer Table 4. AUXR1: Auxiliary Register 1 The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit.
3 GF3 This bit is a general purpose user flag
The value read from this bit is indeterminate. Do n ot set this bit.
0 DPS
4184I–8051–02/08 Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (co py, compare, search ...) are well served by using one data pointer as a ’source’ poin ter and the other one as a "destina- tion" pointer. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added 00A2 AUXR1 EQU 0A2H 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,atDPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX atDPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a par- ticular state, but simply toggles it. In simple rou tines, such as the block move example, only the fact that DPS is toggled in the proper seq uence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR 1), the routine will exit with DPS in the opposite state.
4184I–8051–02/08 Timer 2 The timer 2 in the TS80C52X2 is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintain ed by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON register (See Table 5) and T2MOD register (See Table 6). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F OSC /12 (timer operation) or external pin T2 (counter o peration) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel 8-bit Microcontroller Hardware description. Refer to the Atmel 8-bit Microcontroller Hardware d escription for the description of Cap- ture and Baud Rate Generator Modes. In TS80C52X2 Timer 2 includes the following enhancements:
- Auto-reload mode with up or down counter
- Programmable clock-output Auto-reload Mode The Auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto- matic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 4. In this mode the T2EX pin controls the direction of count. When T2EX is high, timer 2 counts up. Timer overflo w occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The ov erflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underf low occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflows or unde rflows according to the the direc- tion of the count. EXF2 does not generate any inter rupt. This bit can be used to provide 17-bit resolution.
Figure 4. Auto-reload Mode Up/Down Counter (DCEN = 1) (F OSC /2 16) to 4 MHz (F OSC /4). The generated clock signal is brought out to T2 pin (P1.0).
- Set T2OE bit in T2MOD register.
- Clear C/T2 bit in T2CON register.
- Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
- Enter a 16-bit initial value in timer registers TH 2/TL2. It can be the same as the reload value or a different one depending on the application.
- To start the timer, set TR2 run control bit in T2C ON register. It is possible to use timer 2 as a baud rate genera tor and a clock generator simulta- neously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. (DOWN COUNTING RELOAD C/T2 TF2 TR2 EXF2 TH2 (8-bit) TL2 (8-bit) RCAP2H (8-bit) RCAP2L (8-bit) FFh (8-bit) FFh (8-bit) TOGGL (UP COUNTING RELOAD VALUE) TIMER 2 INTERRUPT XTAL1 :12 FOSC FXTAL T2CONreg T2CONreg T2CONreg T2CONreg T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN if DCEN = 0, up counting (:6 in X2 mode) C l oc k O ut F re q ue n c y – Fo sc
Figure 5. Clock-Out Mode C/T2 = 0
Table 5. T2CON Register
7 TF2
Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 an d TCLK = 0.
6 EXF2
5 RCLK
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for se rial port in mode 1 or 3.
4 TCLK
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for s erial port in mode 1 or 3.
3 EXEN2
Clear to ignore events on T2EX pin for timer 2 oper ation. detected, if timer 2 is not used to clock the seria l port.
2 TR2
1 C/T2#
0 CP/RL2#
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Table 6. T2MOD Register The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit.
1 T2OE
Clear to program P1.0/T2 as clock input or I/O port . Set to program P1.0/T2 as clock output.
0 DCEN
Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter.
Figure 8. UART Timings in Modes 2 and 3 nication feature is enabled (SM2 bit in SCON register is set). is not interrupted by command frames addressed to other devices. be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). slaves at a time. The following example illustrates how a given address is formed. The SADEN byte is selected so that each slave may be addressed separately. municate with slave A only, the master must send an address where bit 0 is clear (e.g.
set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). and B, but not slave C, the master can send and address FBh. microcontrollers that do not support automatic address recognition. Table 7. SADEN Register Table 8. SADDR Register
Table 9. SCON Register Clear to reset the error state, not cleared by a va lid stop bit. Set by hardware when an invalid stop bit is detecte d. Refer to SM1 for serial port mode selection.
6 SM1
5 SM2
Clear to disable multiprocessor communication featu re. eventually mode 1. This bit should be cleared in mo de 0.
4 REN
Clear to disable serial reception. Set to enable serial reception.
3 TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.
2 RB8
Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit . In mode 0 RB8 is not used. Clear to acknowledge interrupt. stop bit in the other modes. Clear to acknowledge interrupt.
Table 10. PCON Register doesn’t affect the value of this bit.
7 SMOD1 Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. The value read from this bit is indeterminate. Do n ot set this bit.
4 POF
Clear to recognize next reset type.
3 GF1
Cleared by user for general purpose usage. Set by user for general purpose usage.
2 GF0
Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode.
0 IDL
Clear by hardware when interrupt or reset occurs.
rupts are shown in Figure 9. Figure 9. Interrupt Control System global disable bit, which must be cleared to disable all interrupts at once. associated with each combination. Table 11. Priority Level Bit Values
Table 12. IE Register Clear to disable all interrupts. Set to enable all interrupts. clearing its own interrupt enable bit. The value read from this bit is indeterminate. Do n ot set this bit.
5 ET2
Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. Clear to disable serial port interrupt. Set to enable serial port interrupt.
3 ET1
Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt.
2 EX1
Clear to disable external interrupt 1. Set to enable external interrupt 1.
1 ET0
Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt.
0 EX0
Clear to disable external interrupt 0. Set to enable external interrupt 0.
Table 13. IP Register The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit.
5 PT2 Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4 PS Serial port Priority bit
Refer to PSH for priority level.
3 PT1 Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2 PX1 External interrupt 1 Priority bit
Refer to PX1H for priority level.
1 PT0 Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0 PX0 External interrupt 0 Priority bit
Refer to PX0H for priority level.
Table 14. IPH Register The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit.
5 PT2H
4 PSH
3 PT1H
2 PX1H
1 PT0H
0 PX0H
the instruction that put the device into idle. service routine can examine the flag bits. machine cycles (24 oscillator periods) to complete the reset. long enough for the oscillator to restart and stabilize. interrupt must be enabled and configured as level or edge sensitive interrupt input. one following the instruction that put TS80C52X2 into power-down mode. Figure 10. Power-down Exit Waveform
interrupt does no affect the SFRs. Table 15. The State of Ports During Idle and Power-down Modes Note: 1. Port 0 can force a "zero" level. A "one" wil l leave port floating.
- Pull ALE low while the device is in reset (RST hig h) and PSEN is high.
- Hold ALE low as RST is deactivated. While the TS80C52X2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26. shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied.
Table 16. External Pin Status during ONCE Mode
by software allowing the user to determine the type of reset. reading POF bit will return indeterminate value. Table 17. PCON Register Set to select double baud rate in mode 1, 2 or 3. Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. The value read from this bit is indeterminate. Do n ot set this bit. Clear to recognize next reset type. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode. Clear by hardware when interrupt or reset occurs.
fetches. During ALE disabling, ALE pin is weakly pulled high. Table 18. AUXR Register The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. The value read from this bit is indeterminate. Do n ot set this bit. Clear to restore ALE operation during internal fetc hes. Set to disable ALE operation during internal fetche s.
- the code array:8 Kbytes.
- the encryption array:64 bytes.
- the signature array:4 bytes. ROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. Encryption Array Within the ROM array are 64 bytes of encryption arr ay that are initially unprogrammed (all FF’s). Every time a byte is addressed during p rogram verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted ve rify byte. The algorithm, with the encryption array in the unprogrammed state, will re turn the code in its original, unmodi- fied form. When using the encryption array, one important fact or needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a v erification routine will display the content of the encryption array. For this reason all the unused code bytes should be pro- grammed with random values. This will ensure program protection. Program Lock Bits The lock bits when programmed according to Table 19. will provide different level of pro- tection for the on-chip code and data. U: unprogrammed P: programmed Signature bytes The TS80C52X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 9. Verify Algorithm Refer to Section “Verify Algorithm”.
Table 19. Program Lock bits
1 U U U
2 P U U
sampled and latched on reset.
4184I–8051–02/08 EPROM Structure The TS87C52X2 is divided in two different arrays:
- the code array: 8 Kbytes
- the encryption array: 64 bytes In addition a third non programmable array is implemented:
- the signature array: 4 bytes EPROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. Encryption Array Within the EPROM array are 64 bytes of encryption a rray that are initially unpro- grammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption a rray. This byte is then exclusive- NOR’ed (XNOR) with the code byte, creating an encry pted verify byte. The algorithm, with the encryption array in the unprogrammed state , will return the code in its original, unmodified form. When using the encryption array, one important fact or needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a v erification routine will display the content of the encryption array. For this reason all the unused code bytes should be pro- grammed with random values. This will ensure program protection. Program Lock Bits The three lock bits, when programmed according to T able 1., will provide different level of protection for the on-chip code and data. U: unprogrammed P: programmed WARNING: Security level 2 and 3 should only be prog rammed after EPROM and Core verification. Signature Bytes The TS80/87C52X2 contains 4 factory programmed sign atures bytes. To read these bytes, perform the process described in section 9. EPROM Programming Set-up modes In order to program and verify the EPROM or to read the signature bytes, the TS87C52X2 is placed in specific set-up modes (See Figure 11.). Program Lock Bits Protection Description Security level LB1 LB2 LB3
No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MO VC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program mem ory are disabled from fetching code bytes from internal mem ory, EA is sampled and latched on reset, and further programmi ng of the EPROM is disabled. 3 U P U Same as 2, also verify is disabled. 4 U U P Same as 3, also external execution is disabled.
Control and program signals must be held at the levels indicated in Table 35. Program Signals: ALE/PROG , EA /VPP. Table 20. EPROM Set-up Modes Figure 11. Set-Up Modes Configuration
decreases the number of pulses applied during byte programming from 25 to 1.
- Step 1: Activate the combination of control signal s.
- Step 2: Input the valid address on the address lin es.
- Step 3: Input the appropriate data on the data lin es.
- Step 4: Raise EA /VPP from VCC to VPP (typical 12.75V).
- Step 5: Pulse ALE/PROG once.
- Step 6: Lower EA /VPP from VPP to VCC Repeat step 2 through 6 changing the address and da ta for the entire array or until the end of the object file is reached (See Figure 12.). Verify Algorithm Code array verify must be done after each byte or b lock of bytes is programmed. In either case, a complete verify of the programmed array will ensure reliable programming of the TS87C52X2. P 2.7 is used to enable data output. To verify the TS87C52X2 code the following sequence must be exercised:
- Step 1: Activate the combination of program and co ntrol signals.
- Step 2: Input the valid address on the address lin es.
- Step 3: Read data on the data lines. Repeat step 2 through 3 changing the address for th e entire array verification (See Fig- ure 12.) The encryption array cannot be directly verified. V erification of the encryption array is done by observing that the code array is well encrypted.
Figure 12. Programming and Verification Signal’s Waveform ing the parts to full functionality. Erasure leaves all the EPROM cells in a 1’s state (FF).
- Exposing the EPROM to an ultraviolet lamp of
12,000 µ W/cm 2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers. that an opaque label be placed over the window. signature byte for the TS80/87C52X2. Table 21. Signature Bytes Content
connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc. conditions may affect device reliability.
- This value is based on the maximum allowable die
Table 22. DC Parameters in Standard Voltage
Table 22. DC Parameters in Standard Voltage (Continued)
- Idle I CC is measured with all output pins disconnected; XTAL1 driven with T CLCH , T CHCL = 5 ns, V IL = V SS + 0.5V, V IH = V CC -
0.5V; XTAL2 N.C; Port 0 = V CC ; EA = RST = V SS (see Figure 15.).
- Power Down I CC is measured with all output pins disconnected; EA = V SS , PORT 0 = V CC ; XTAL2 NC.; RST = V SS (see Fig-
- Capacitance loading on Ports 0 and 2 may cause sp urious noise pulses to be superimposed on the V OL s of ALE and Ports 1
0.45V with maxi V OL peak 0.6V. A Schmitt Trigger use is not necessary.
- Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
- Under steady state (non-transient) conditions, I OL must be externally limited as follows:
Table 23. DC Parameters for Low Voltage
0.15 Freq
Table 25. Max frequency for derating formula regarding the speed grade Table 26. Symbol Description
Table 27. AC Parameters for Fix Clock Table 28. AC Parameters for a Variable Clock: derating formula
40 MHz
30 MHz
60 MHz
20 MHz
Figure 18. External Program Memory Read Cycle Table 29. Symbol Description
12 T CLCL
Table 30. AC Parameters for a Fix Clock
Table 31. AC Parameters for a Variable Clock: Derating Formula Figure 19. External Data Memory Write Cycle
Figure 20. External Data Memory Read Cycle Table 32. Symbol Description Table 33. AC Parameters for a Fix Clock
30 MHz Units
Table 34. AC Parameters for a Variable Clock: Derating Formula Figure 21. Shift Register Timing Waveforms
Figure 22. EPROM Programming and Verification Waveforms Table 35. EPROM Programming Parameters
Figure 26. Clock Waveforms WR propagation delays are approximately 50ns. The oth er signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.
4184I–8051–02/08
Ordering Information
Table 37. Possible Ordering Entries
Table 37. Possible Ordering Entries (Continued)
Notes: 1. 20 MHz in X2 Mode.
- Tape and Reel available for SL, PQFP and RL packa ges
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